Changes - j0ke.net Open Build Service

@@ -3,6 +3,9 @@ x86info AMD/fam10h.h AMD/fam11h.h +AMD/fam12h.h +AMD/fam14h.h +AMD/fam15h.h AMD/k8.h generic_msr.h lsmsr

@@ -0,0 +1,1693 @@ +# Author: Andreas Herrmann <andreas.herrmann3@amd.com> +# +# Copyright (C) 2008, 2009 Advanced Micro Devices, Inc. + +# This file contains information from: +# - "41131 Rev 3.00 - June 2011, BIOS and Kernel Developer's Guide (BKDG) +# for AMD Family 12h Processors" + +# See scripts/createheader.py for the general format of this register +# definitions. + +{LSMCAaddr=0x0000;load-store MCA address + ADDR:64 +} # alias of MC3_ADDR + +{LSMCAstatus=0x0001;load-store MCE status + ErrorCode:16 + ErrorCodeExt:4 + :4 + SYND:8 + :13 + UECC:1 + CECC:1 + SYND:8 + :2 + PCC:1 + ADDRV:1 + MISCV:1 + EN:1 + UC:1 + OVER:1 + VAL:1 +} # alias of MC3_STATUS + +{TSC=0x0010;time-stamp counter + TSC:64 +} + +{APIC_BASE=0x001b;APIC base address + :8 + BSC:1 + :2 + ApicEn:1 + ApicBar:28 + :24 +} + +{EBL_CR_POWERON=0x002a;cluster ID + :16 + ClusterID:2 + :46 +} + +{PATCH_LEVEL=0x008b;microcode patch level + PATCH_LEVEL:32 + :32 +} + +{MPERF=0x00e7;max performance frequency clock count + MPERF:64 +} + +{APERF=0x00e8;actual performance frequency clock count + APERF:64 +} + +{MTRRcap=0x00fe;MTRR capabilities + MtrrCapVCnt:8 + MtrrCapFix:1 + :1 + MtrrCapWc:1 + :53 +} + +{SYSENTER_CS=0x0174;SYSENTER/SYSEXIT code segment selector + SYSENTER_CS:16 + :48 +} + +{SYSENTER_ESP=0x0175;SYSENTER/SYSEXIT stack pointer + SYSENTER_ESP:32 + :32 +} + +{SYSENTER_EIP=0x0176;SYSENTER/SYSEXIT instruction pointer + SYSENTER_EIP:32 + :32 +} + +{MCG_CAP=0x0179;global MC capabilities + Count:8 + MCG_CTL_P:1 + :55 +} + +{MCG_STAT=0x017a;global MC status + RIPV:1 + EIPV:1 + MCIP:1 + :61 +} + +{MCG_CTL=0x017b;global MC control + LS:1 + IF:1 + BU:1 + FP:1 + NB:1 + FR:1 + :58 +} + +{DBG_CTL_MSR=0x01d9;debug control + LBR:1 + BTF:1 + PB0:1 + PB1:1 + PB2:1 + PB3:1 + :58 +} + +{BR_FROM=0x01db;last branch from IP + LastBranchFromIP:64 +} + +{BR_TO=0x01dc;last branch to IP + LastBranchToIP:64 +} + +{LastExceptionFromIP=0x01dd;last exception from IP + LastIntFromIP:64 +} + +{LastExceptionToIP=0x01de;last exception to IP + LastIntToIP:64 +} + +{MTRRphysBase0=0x0200;base of variable-size MTRR (0) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:28 + :24 +} + +{MTRRphysMask0=0x0201;mask of variable-size MTRR (0) + :11 + Valid:1 + PhysMask:28 + :24 +} + +{MTRRphysBase1=0x0202;base of variable-size MTRR (1) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:28 + :24 +} + +{MTRRphysMask1=0x0203;mask of variable-size MTRR (1) + :11 + Valid:1 + PhysMask:28 + :24 +} + +{MTRRphysBase2=0x0204;base of variable-size MTRR (2) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:28 + :24 +} + +{MTRRphysMask2=0x0205;mask of variable-size MTRR (2) + :11 + Valid:1 + PhysMask:28 + :24 +} + +{MTRRphysBase3=0x0206;base of variable-size MTRR (3) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:28 + :24 +} + +{MTRRphysMask3=0x0207;mask of variable-size MTRR (3) + :11 + Valid:1 + PhysMask:28 + :24 +} + +{MTRRphysBase4=0x0208;base of variable-size MTRR (4) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:28 + :24 +} + +{MTRRphysMask4=0x0209;mask of variable-size MTRR (4) + :11 + Valid:1 + PhysMask:28 + :24 +} + +{MTRRphysBase5=0x020a;base of variable-size MTRR (5) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:28 + :24 +} + +{MTRRphysMask5=0x020b;mask of variable-size MTRR (5) + :11 + Valid:1 + PhysMask:28 + :24 +} + +{MTRRphysBase6=0x020c;base of variable-size MTRR (6) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:28 + :24 +} + +{MTRRphysMask6=0x020d;mask of variable-size MTRR (6) + :11 + Valid:1 + PhysMask:28 + :24 +} + +{MTRRphysBase7=0x020e;base of variable-size MTRR (7) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:28 + :24 +} + +{MTRRphysMask7=0x020f;mask of variable-size MTRR (7) + :11 + Valid:1 + PhysMask:28 + :24 +} + +{MTRRfix64K_00000=0x0250;fixed range MTRR + 0xxxxMemType:3 + 0xxxxWrDram:1 + 0xxxxRdDram:1 + :3 + 1xxxxMemType:3 + 1xxxxWrDram:1 + 1xxxxRdDram:1 + :3 + 2xxxxMemType:3 + 2xxxxWrDram:1 + 2xxxxRdDram:1 + :3 + 3xxxxMemType:3 + 3xxxxWrDram:1 + 3xxxxRdDram:1 + :3 + 4xxxxMemType:3 + 4xxxxWrDram:1 + 4xxxxRdDram:1 + :3 + 5xxxxMemType:3 + 5xxxxWrDram:1 + 5xxxxRdDram:1 + :3 + 6xxxxMemType:3 + 6xxxxWrDram:1 + 6xxxxRdDram:1 + :3 + 7xxxxMemType:3 + 7xxxxWrDram:1 + 7xxxxRdDram:1 + :3 +} + +{MTRRfix16K_80000=0x0258;fixed range MTRR + 80xxxMemType:3 + 80xxxWrDram:1 + 80xxxRdDram:1 + :3 + 84xxxMemType:3 + 84xxxWrDram:1 + 84xxxRdDram:1 + :3 + 88xxxMemType:3 + 88xxxWrDram:1 + 88xxxRdDram:1 + :3 + 8CxxxMemType:3 + 8CxxxWrDram:1 + 8CxxxRdDram:1 + :3 + 90xxxMemType:3 + 90xxxWrDram:1 + 90xxxRdDram:1 + :3 + 94xxxMemType:3 + 94xxxWrDram:1 + 94xxxRdDram:1 + :3 + 98xxxMemType:3 + 98xxxWrDram:1 + 98xxxRdDram:1 + :3 + 9CxxxMemType:3 + 9CxxxWrDram:1 + 9CxxxRdDram:1 + :3 +} + +{MTRRfix16K_A0000=0x0259;fixed range MTRR + A0xxxMemType:3 + A0xxxWrDram:1 + A0xxxRdDram:1 + :3 + A4xxxMemType:3 + A4xxxWrDram:1 + A4xxxRdDram:1 + :3 + A8xxxMemType:3 + A8xxxWrDram:1 + A8xxxRdDram:1 + :3 + ACxxxMemType:3 + ACxxxWrDram:1 + ACxxxRdDram:1 + :3 + B0xxxMemType:3 + B0xxxWrDram:1 + B0xxxRdDram:1 + :3 + B4xxxMemType:3 + B4xxxWrDram:1 + B4xxxRdDram:1 + :3 + B8xxxMemType:3 + B8xxxWrDram:1 + B8xxxRdDram:1 + :3 + BCxxxMemType:3 + BCxxxWrDram:1 + BCxxxRdDram:1 + :3 +} + +{MTRRfix4K_C0000=0x0268;fixed range MTRR + C0xxxMemType:3 + C0xxxWrDram:1 + C0xxxRdDram:1 + :3 + C1xxxMemType:3 + C1xxxWrDram:1 + C1xxxRdDram:1 + :3 + C2xxxMemType:3 + C2xxxWrDram:1 + C2xxxRdDram:1 + :3 + C3xxxMemType:3 + C3xxxWrDram:1 + C3xxxRdDram:1 + :3 + C4xxxMemType:3 + C4xxxWrDram:1 + C4xxxRdDram:1 + :3 + C5xxxMemType:3 + C5xxxWrDram:1 + C5xxxRdDram:1 + :3 + C6xxxMemType:3 + C6xxxWrDram:1 + C6xxxRdDram:1 + :3 + C7xxxMemType:3 + C7xxxWrDram:1 + C7xxxRdDram:1 + :3 +} + +{MTRRfix4K_C8000=0x0269;fixed range MTRR + C8xxxMemType:3 + C8xxxWrDram:1 + C8xxxRdDram:1 + :3 + C9xxxMemType:3 + C9xxxWrDram:1 + C9xxxRdDram:1 + :3 + CAxxxMemType:3 + CAxxxWrDram:1 + CAxxxRdDram:1 + :3 + CBxxxMemType:3 + CBxxxWrDram:1 + CBxxxRdDram:1 + :3 + CCxxxMemType:3 + CCxxxWrDram:1 + CCxxxRdDram:1 + :3 + CDxxxMemType:3 + CDxxxWrDram:1 + CDxxxRdDram:1 + :3 + CExxxMemType:3 + CExxxWrDram:1 + CExxxRdDram:1 + :3 + CFxxxMemType:3 + CFxxxWrDram:1 + CFxxxRdDram:1 + :3 +} + +{MTRRfix4K_D0000=0x026a;fixed range MTRR + D0xxxMemType:3 + D0xxxWrDram:1 + D0xxxRdDram:1 + :3 + D1xxxMemType:3 + D1xxxWrDram:1 + D1xxxRdDram:1 + :3 + D2xxxMemType:3 + D2xxxWrDram:1 + D2xxxRdDram:1 + :3 + D3xxxMemType:3 + D3xxxWrDram:1 + D3xxxRdDram:1 + :3 + D4xxxMemType:3 + D4xxxWrDram:1 + D4xxxRdDram:1 + :3 + D5xxxMemType:3 + D5xxxWrDram:1 + D5xxxRdDram:1 + :3 + D6xxxMemType:3 + D6xxxWrDram:1 + D6xxxRdDram:1 + :3 + D7xxxMemType:3 + D7xxxWrDram:1 + D7xxxRdDram:1 + :3 +} + +{MTRRfix4K_D8000=0x026b;fixed range MTRR + D8xxxMemType:3 + D8xxxWrDram:1 + D8xxxRdDram:1 + :3 + D9xxxMemType:3 + D9xxxWrDram:1 + D9xxxRdDram:1 + :3 + DAxxxMemType:3 + DAxxxWrDram:1 + DAxxxRdDram:1 + :3 + DBxxxMemType:3 + DBxxxWrDram:1 + DBxxxRdDram:1 + :3 + DCxxxMemType:3 + DCxxxWrDram:1 + DCxxxRdDram:1 + :3 + DDxxxMemType:3 + DDxxxWrDram:1 + DDxxxRdDram:1 + :3 + DExxxMemType:3 + DExxxWrDram:1 + DExxxRdDram:1 + :3 + DFxxxMemType:3 + DFxxxWrDram:1 + DFxxxRdDram:1 + :3 +} + +{MTRRfix4K_E0000=0x026c;fixed range MTRR + E0xxxMemType:3 + E0xxxWrDram:1 + E0xxxRdDram:1 + :3 + E1xxxMemType:3 + E1xxxWrDram:1 + E1xxxRdDram:1 + :3 + E2xxxMemType:3 + E2xxxWrDram:1 + E2xxxRdDram:1 + :3 + E3xxxMemType:3 + E3xxxWrDram:1 + E3xxxRdDram:1 + :3 + E4xxxMemType:3 + E4xxxWrDram:1 + E4xxxRdDram:1 + :3 + E5xxxMemType:3 + E5xxxWrDram:1 + E5xxxRdDram:1 + :3 + E6xxxMemType:3 + E6xxxWrDram:1 + E6xxxRdDram:1 + :3 + E7xxxMemType:3 + E7xxxWrDram:1 + E7xxxRdDram:1 + :3 +} + +{MTRRfix4K_E8000=0x026d;fixed range MTRR + E8xxxMemType:3 + E8xxxWrDram:1 + E8xxxRdDram:1 + :3 + E9xxxMemType:3 + E9xxxWrDram:1 + E9xxxRdDram:1 + :3 + EAxxxMemType:3 + EAxxxWrDram:1 + EAxxxRdDram:1 + :3 + EBxxxMemType:3 + EBxxxWrDram:1 + EBxxxRdDram:1 + :3 + ECxxxMemType:3 + ECxxxWrDram:1 + ECxxxRdDram:1 + :3 + EDxxxMemType:3 + EDxxxWrDram:1 + EDxxxRdDram:1 + :3 + EExxxMemType:3 + EExxxWrDram:1 + EExxxRdDram:1 + :3 + EFxxxMemType:3 + EFxxxWrDram:1 + EFxxxRdDram:1 + :3 +} + +{MTRRfix4K_F0000=0x026e;fixed range MTRR + F0xxxMemType:3 + F0xxxWrDram:1 + F0xxxRdDram:1 + :3 + F1xxxMemType:3 + F1xxxWrDram:1 + F1xxxRdDram:1 + :3 + F2xxxMemType:3 + F2xxxWrDram:1 + F2xxxRdDram:1 + :3 + F3xxxMemType:3 + F3xxxWrDram:1 + F3xxxRdDram:1 + :3 + F4xxxMemType:3 + F4xxxWrDram:1 + F4xxxRdDram:1 + :3 + F5xxxMemType:3 + F5xxxWrDram:1 + F5xxxRdDram:1 + :3 + F6xxxMemType:3 + F6xxxWrDram:1 + F6xxxRdDram:1 + :3 + F7xxxMemType:3 + F7xxxWrDram:1 + F7xxxRdDram:1 + :3 +} + +{MTRRfix4K_F8000=0x026f;fixed range MTRR + F8xxxMemType:3 + F8xxxWrDram:1 + F8xxxRdDram:1 + :3 + F9xxxMemType:3 + F9xxxWrDram:1 + F9xxxRdDram:1 + :3 + FAxxxMemType:3 + FAxxxWrDram:1 + FAxxxRdDram:1 + :3 + FBxxxMemType:3 + FBxxxWrDram:1 + FBxxxRdDram:1 + :3 + FCxxxMemType:3 + FCxxxWrDram:1 + FCxxxRdDram:1 + :3 + FDxxxMemType:3 + FDxxxWrDram:1 + FDxxxRdDram:1 + :3 + FExxxMemType:3 + FExxxWrDram:1 + FExxxRdDram:1 + :3 + FFxxxMemType:3 + FFxxxWrDram:1 + FFxxxRdDram:1 + :3 +} + +{PAT=0x0277;page attribute table + PA0MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA1MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA2MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA3MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA4MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA5MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA6MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA7MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 +} + +{MTRRdefType=0x02ff;MTRR default memory type + MemType:8 + :2 + MtrrDefTypeFixEn:1 + MtrrDefTypeEn:1 + :52 +} + +{MC0_CTL=0x0400;data cache MC control + ECCI:1 + ECCM:1 + DECC:1 + DMTP:1 + DSTP:1 + L1TP:1 + L2TP:1 + :57 +} + +{MC0_STATUS=0x0401;data cache MC status + ErrorCode:16 + ErrorCodeExt:4 + :4 + Syndrome:8 + :13 + UECC:1 + CECC:1 + Syndrome:8 + :2 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + OVER:1 + VAL:1 +} + +{MC0_ADDR=0x0402;data cache MC address + ADDR:64 +} + +{MC0_MISC=0x0403;data cache MC miscellaneous + :64 +} + +{MC1_CTL=0x0404;instruction cache MC control + ECCI:1 + ECCM:1 + IDP:1 + IMTP:1 + ISTP:1 + L1TP:1 + L2TP:1 + :2 + RDDE:1 + :54 +} + +{MC1_STATUS=0x0405;instruction cache MC status + ErrorCode:16 + ErrorCodeExt:4 + :4 + Syndrome:8 + :13 + UECC:1 + CECC:1 + Syndrome:8 + :2 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + OVER:1 + VAL:1 +} + +{MC1_ADDR=0x0406;instruction cache MC address + ADDR:64 +} + +{MC1_MISC=0x0407;instruction cache MC miscellaneous + :64 +} + +{MC2_CTL=0x0408;BU MC control + SRDE_HP:1 + SRDE_TLB:1 + SRDE_ALL:1 + L2T_PAR:1 + L2T_CECC:1 + L2T_UECC:1 + L2D_PAR:1 + L2D_CECC:1 + L2D_UECC:1 + :1 + VB_PAR:1 + PDC_PAR:1 + :52 +} + +{MC2_STATUS=0x0409;BU MC status + ErrorCode:16 + ErrorCodeExt:4 + :4 + Syndrome:8 + :13 + UECC:1 + CECC:1 + Syndrome:8 + :2 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + OVER:1 + VAL:1 +} + +{MC2_ADDR=0x040a;BU MC address register + ADDR:64 +} + +{MC2_MISC=0x040b;BU MC miscellaneous + :64 +} + +{MC3_CTL=0x040c;LS MC control + SRDE_L:1 + SRDE_S:1 + :62 +} + +{MC3_STATUS=0x040d;LS MC status + ErrorCode:16 + ErrorCodeExt:4 + :4 + Syndrome:8 + :13 + UECC:1 + CECC:1 + Syndrome:8 + :2 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + OVER:1 + VAL:1 +} + +{MC3_ADDR=0x040e;LS MC address + ADDR:64 +} + +{MC3_MISC=0x040f;LS MC miscellaneous + :64 +} + +{MC4_CTL=0x0410;NB MC control + :5 + SyncFloodEn:1 + :2 + MstrAbrtEn:1 + TgtAbrtEn:1 + :1 + AtomicRMWEn:1 + WDTRptEn:1 + DevErrEn:1 + :2 + ProtEn:1 + DataEn:1 + :7 + McaUsPwDatErrEn:1 + :38 +} + +{MC4_STATUS=0x0411;NB MC status + ErrorCode:16 + ErrorCodeExt:5 + :11 + ErrCpu0:1 + ErrCpu1:1 + ErrCpu2:1 + ErrCpu3:1 + BusErr:1 + :20 + PCC:1 + AddrV:1 + :1 + En:1 + UC:1 + Over:1 + Val:1 +} + +{MC4_ADDR=0x0412;NB MC address + McaNbAddrLow:32 + McaNbAddrHigh:32 +} + +{MC4_MISC0=0x0413;reserved (NB MC misc) + :64 +} + +{MC5_CTL=0x0414;FR MC control + CPUWDT:1 + :63 +} + +{MC5_STATUS=0x0415;FR MC status + ErrorCode:16 + ErrorCodeExt:4 + :4 + Syndrome:8 + :13 + UECC:1 + CECC:1 + Syndrome:8 + :2 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + OVER:1 + VAL:1 +} + +{MC5_ADDR=0x0416;FR MC address + ADDR:64 +} + +{MC5_MISC=0x0417;FR MC miscellaneous + State:12 + :52 +} + +{EFER=0xc0000080;extended feature enable + SYSCALL:1 + :7 + LME:1 + :1 + LMA:1 + NXE:1 + SVME:1 + LMSLE:1 + FFXSE:1 + :49 +} + +{STAR=0xc0000081;SYSCALL target address + Target:32 + SysCallSel:16 + SysRetSel:16 +} + +{STAR64=0xc0000082;long mode SYSCALL target address + LSTAR:64 +} + +{STARCOMPAT=0xc0000083;compat mode SYSCALL target address + CSTAR:64 +} + +{SYSCALL_FLAG_MASK=0xc0000084;SYSCALL flag mask + MASK:32 + :32 +} + +{FS_BASE=0xc0000100;FS base + FS_BASE:64 +} + +{GS_BASE=0xc0000101;GS base + GS_BASE:64 +} + +{KernelGSbase=0xc0000102;kernel GS base + KernelGSBase:64 +} + +{TSC_AUX=0xc0000103;auxiliary time stamp counter data + TscAux:32 + :32 +} + +{PERF_CTL0=0xc0010000;performance event select (0) + EventSelect:8 + UnitMask:8 + User:1 + OS:1 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + GuestOnly:1 + HostOnly:1 + :22 +} + +{PERF_CTL1=0xc0010001;performance event select (1) + EventSelect:8 + UnitMask:8 + User:1 + OS:1 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + GuestOnly:1 + HostOnly:1 + :22 +} + +{PERF_CTL2=0xc0010002;performance event select (2) + EventSelect:8 + UnitMask:8 + User:1 + OS:1 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + GuestOnly:1 + HostOnly:1 + :22 +} + +{PERF_CTL3=0xc0010003;performance event select (3) + EventSelect:8 + UnitMask:8 + User:1 + OS:1 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + GuestOnly:1 + HostOnly:1 + :22 +} + +{PERF_CTR0=0xc0010004;performance event counter (0) + CTR:48 + :16 +} + +{PERF_CTR1=0xc0010005;performance event counter (1) + CTR:48 + :16 +} + +{PERF_CTR2=0xc0010006;performance event counter (2) + CTR:48 + :16 +} + +{PERF_CTR3=0xc0010007;performance event counter (3) + CTR:48 + :16 +} + +{SYS_CFG=0xc0010010;system configuration + :8 + SetDirtyEnE:1 + SetDirtyEnS:1 + SetDirtyEnO:1 + :5 + ChxToDirtyDis:1 + SysUcLockEn:1 + MtrrFixDramEn:1 + MtrrFixDramModeEn:1 + MtrrVarDramEn:1 + MtrrTom2En:1 + Tom2ForceMemTypeWB:1 + :41 +} + +{HWCR=0xc0010015;hardware configuration + SmmLock:1 + SlowFence:1 + :1 + TlbCacheDis:1 + INVD_WBINVD:1 + :3 + IgnneEm:1 + MonMwaitDis:1 + MonMwaitUserEn:1 + :2 + SmiSpCycDis:1 + RsmSpCycDis:1 + SseDis:1 + :1 + Wrap32Dis:1 + McStatusWrEn:1 + :1 + IoCfgGpFault:1 + MisAlignSseDis:1 + :1 + ForceUsRdWrSzPrb:1 + TscFreqSel:1 + CpbDis:1 + EffFreqCntMwait:1 + :37 +} + +{IORR_BASE0=0xc0010016;base of variable I/O range (0) + :3 + WrMem:1 + RdMem:1 + :7 + PhyBase:28 + :24 +} + +{IORR_MASK0=0xc0010017;mask of variable I/O range (0) + :11 + Valid:1 + PhyMask:28 + :24 +} + +{IORR_BASE1=0xc0010018;base of variable I/O range (1) + :3 + WrMem:1 + RdMem:1 + :7 + PhyBase:28 + :24 +} + +{IORR_MASK1=0xc0010019;mask of variable I/O range (1) + :11 + Valid:1 + PhyMask:28 + :24 +} + +{TOP_MEM=0xc001001a;top of memory address + :23 + TOM:17 + :24 +} + +{TOM2=0xc001001d;second top of memory address + :23 + TOM2:17 + :24 +} + +{NB_CFG=0xc001001f;northbridge configuration + :45 + DisUsSysMgtReqToNcHt:1 + EnableCf8ExtCfg:1 + :11 + EnConvertToNonIsoc:1 + :5 +} + +{MCEredirection=0xc0010022;MCE redirection + RedirVector:8 + RedirVecEn:1 + RedirSmiEn:1 + :54 +} + +{ProcessorNameString0=0xc0010030;processor name string (0) + CpuNameString:64 +} + +{ProcessorNameString1=0xc0010031;processor name string (1) + CpuNameString:64 +} + +{ProcessorNameString2=0xc0010032;processor name string (2) + CpuNameString:64 +} + +{ProcessorNameString3=0xc0010033;processor name string (3) + CpuNameString:64 +} + +{ProcessorNameString4=0xc0010034;processor name string (4) + CpuNameString:64 +} + +{ProcessorNameString5=0xc0010035;processor name string (5) + CpuNameString:64 +} + +{MC0_CTL_MASK=0xc0010044;data cache MC control mask + ECCI:1 + ECCM:1 + DECC:1 + DMTP:1 + DSTP:1 + L1TP:1 + L2TP:1 + :57 +} + +{MC1_CTL_MASK=0xc0010045;instruction cache MC control mask + ECCI:1 + ECCM:1 + IDP:1 + IMTP:1 + ISTP:1 + L1TP:1 + L2TP:1 + :2 + RDDE:1 + :54 +} + +{MC2_CTL_MASK=0xc0010046;BU MC control mask + SRDE_HP:1 + SRDE_TLB:1 + SRDE_ALL:1 + L2T_PAR:1 + L2T_CECC:1 + L2T_UECC:1 + L2D_PAR:1 + L2D_CECC:1 + L2D_UECC:1 + :1 + VB_PAR:1 + PDC_PAR:1 + :52 +} + +{MC3_CTL_MASK=0xc0010047;LS MC control mask + SRDE_L:1 + SRDE_S:1 + :62 +} + +{MC4_CTL_MASK=0xc0010048;NB MC control mask + :5 + SyncFloodEn:1 + :2 + MstrAbrtEn:1 + TgtAbrtEn:1 + :1 + AtomicRMWEn:1 + WDTRptEn:1 + DevErrEn:1 + :2 + ProtEn:1 + DataEn:1 + :7 + McaUsPwDatErrEn:1 + :38 +} + +{MC5_CTL_MASK=0xc0010049;FR MC control mask + CPUWDT:1 + :63 +} + +{SMI_ON_IO_TRAP_0=0xc0010050;IO trap address (0) + SmiAddr:32 + SmiMask:24 + :5 + ConfigSmi:1 + SmiOnWrEn:1 + SmiOnRdEn:1 +} + +{SMI_ON_IO_TRAP_1=0xc0010051;IO trap address (1) + SmiAddr:32 + SmiMask:24 + :5 + ConfigSmi:1 + SmiOnWrEn:1 + SmiOnRdEn:1 +} + +{SMI_ON_IO_TRAP_2=0xc0010052;IO trap address (2) + SmiAddr:32 + SmiMask:24 + :5 + ConfigSmi:1 + SmiOnWrEn:1 + SmiOnRdEn:1 +} + +{SMI_ON_IO_TRAP_3=0xc0010053;IO trap address (3) + SmiAddr:32 + SmiMask:24 + :5 + ConfigSmi:1 + SmiOnWrEn:1 + SmiOnRdEn:1 +} + +{SMI_ON_IO_TRAP_CTL_STS=0xc0010054;IO trap control + :1 + SmiEn_0:1 + :1 + SmiEn_1:1 + :1 + SmiEn_2:1 + :1 + SmiEn_3:1 + :7 + IoTrapEn:1 + :48 +} + +{SmiTriggerIoCycle=0xc0010056;SMI trigger IO cycle + IoPortAddress:16 + IoData:8 + :1 + IoCycleEn:1 + IoRd:1 + :37 +} + +{MmioConfigBase=0xc0010058;MMIO configuration base address + Enable:1 + :1 + SegBusRange:4;0=1;1=2;2=4;3=8;4=16;5=32;6=64;7=128;8=256 + :14 + MmiocCfgBaseAddr:20 + :24 +} + +{BistResults=0xc0010060;BIST results + BistResults:32 + :32 +} + +{PstateCurrentLimit=0xc0010061;P-state current limit + CurPstateLimit:3 + :1 + PstateMaxVal:3 + :57 +} + +{PstateControl=0xc0010062;P-state control + PstateCmd:3 + :61 +} + +{PstateStatus=0xc0010063;P-state status + CurPstate:3 + :61 +} + +{Pstate0=0xc0010064;P-state 0 + CpuDid:4 + CpuFid:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate1=0xc0010065;P-state 1 + CpuDid:4 + CpuFid:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate2=0xc0010066;P-state 2 + CpuDid:4 + CpuFid:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate3=0xc0010067;P-state 3 + CpuDid:4 + CpuFid:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate4=0xc0010068;P-state 4 + CpuDid:4 + CpuFid:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate5=0xc0010069;P-state 5 + CpuDid:4 + CpuFid:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate6=0xc001006a;P-state 6 + CpuDid:4 + CpuFid:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate7=0xc001006b;P-state 7 + CpuDid:4 + CpuFid:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{COFVIDcontrol=0xc0010070;COFVID control + CpuDid:4 + CpuFid:5 + CpuVid:7 + PstateId:3 + IgnorVidFidDid:1 + :44 +} + +{COFVIDstatus=0xc0010071;COFVID status + CurCpuDid:4 + CurCpuFid:5 + CurCpuVid:7 + CurPstate:3 + :1 + PstateInProgress:1 + :4 + CurNbVid:7 + StartupPstate:3 + MaxVid:7 + MinVid:7 + MainPllOpFreqIdMax:6 + :1 + CurPstateLimit:3 + :5 +} + +{CstateAddress=0xc0010073;C-state address + CstateAddr:16 + :48 +} + +{CpuWdTmrCfg=0xc0010074;CPU watchdog timer + CpuWdtEn:1 + CpuWdtTimeBase:2 + CpuWdtCountSel:4 + :57 +} + +{SMM_BASE=0xc0010111;SMM base address + SMM_BASE:32 + :32 +} + +{SMMAddr=0xc0010112;SMM TSeg base address + :17 + TSegBase:23 + :24 +} + +{SMMMask=0xc0010113;SMM Tseg mask + AValid:1 + TValid:1 + AClose:1 + TClose:1 + AMTypeIoWc:1 + TMTypeIoWc:1 + :2 + AMTypeDram:3 + :1 + TMTypeDram:3 + :2 + TSegMask:23 + :24 +} + +{VM_CR=0xc0010114;virtual machine control + dpd:1 + r_init:1 + dis_a20m:1 + Lock:1 + Svme_Disable:1 + :59 +} + +{IGNNE=0xc0010115;IGNNE + IGNNE:1 + :63 +} + +# {SMM_CTL=0xc0010116;SMM control +# smm_dismiss:1 +# smm_enter:1 +# smi_cyle:1 +# smm_exit:1 +# rsm_cycle:1 +# :59 +# } # write-only + +{VM_HSAVE_PA=0xc0010117;virtual machine host save physical address + :12 + VM_HSAVE_PA:28 + :24 +} + +# {SVMLock=0xc0010118;SVM lock key +# SvmLockKey:64 +# } # write-only + +# {SMMLock=0xc0010119;SMM lock key +# SmmLockKey:64 +# } # write-only + +{SMIstatus=0xc001011a;local SMI status + IoTrapSts:4 + :4 + MceRedirSts:1 + :7 + SmiSrcLvtLcy:1 + SmiSrcLvtExt:1 + :46 +} + +{OSVW_ID_Length=0xc0010140;OS visible work-around + OSVW_ID_Length:16 + :48 +} + +{OsvwStatus=0xc0010141;OS visible work-around status bits + OsvwStatusBits:64 +} + +{CPUIDFeatures=0xc0011004;CPUID features + FeaturesEdx:32 + FeaturesEcx:32 +} + +{CPUIDExtFeatures=0xc0011005;extended CPUID features + ExtFeaturesEdx:32 + ExtFeaturesEcx:32 +} + +{LS_CFG=0xc0011020;load store configuration + :28 + DIS_SS:1 + :35 +} + +{IC_CFG=0xc0011021;instruction cache configuration + :9 + DIS_SPEC_TLB_RLD:1 + :54 +} + +{DC_CFG=0xc0011022;data cache configuration + :4 + DIS_SPEC_TLB_RLD:1 + :3 + DIS_CLR_WBTOL2_SMC_HIT:1 + :4 + DIS_HW_PF:1 + :50 +} + +{DE_CFG=0xc0011029;decode configuration + :23 + ClflushSerialize:1 + :13 +} + +{BU_CFG2=0xc001102A;bus unit configuration 2 + :35 + IcDisSpecTlbWr:1 + :14 + RdMmExtCfgDwDis:1 + :5 + L2ClkGatingEn:1 + L2HystCnt:2 + :5 +} + +{IbsFetchCtl=0xc0011030;IBS fetch control + IbsFetchMaxCnt:16 + IbsFetchCnt:16 + IbsFetchLat:16 + IbsFetchEn:1 + IbsFetchVal:1 + IbsFetchComp:1 + IbsIcMiss:1 + IbsPhyAddrValid:1 + IbsL1TlbPgSz:2 + IbsL1TlbMiss:1 + IbsL2TlbMiss:1 + IbsRandEn:1 + :6 +} + +{IbsFetchLinAd=0xc0011031;IBS fetch linear address + IbsFetchLinAd:64 +} + +{IbsFetchPhysAd=0xc0011032;IBS fetch physical address + IbsFetchPhysAd:64 +} + +{IbsOpCtl=0xc0011033;IBS execution control + IbsOpMaxCnt:16 + :1 + IbsOpEn:1 + IbsOpVal:1 + IbsOpCntCtl:1 + IbsOpMaxCntExt:7 + :5 + IbsOpCurCnt:20 + IbsOpCurCntExt:7 + :5 +} + +{IbsOpRip=0xc0011034;IBS Op logical address + IbsOpRip:64 +} + +{IbsOpData=0xc0011035;IBS Op data + IbsCompToRetCtr:16 + IbsTagToRetCtr:16 + IbsOpBrnResync:1 + IbsOpMispReturn:1 + IbsOpReturn:1 + IbsOpBrnTaken:1 + IbsOpBrnMisp:1 + IbsOpBrnRet:1 + IbsRipInvalid:1 + :25 +} + +{IbsOpData2=0xc0011036;IBS Op data 2 + NbIbsReqSrc:3 + :61 +} + +{IbsOpData3=0xc0011037;IBS Op data 3 + IbsLdOp:1 + IbsStOp:1 + IbsDcL1tlbMiss:1 + IbsDcL2tlbMiss:1 + IbsDcL1tlbHit2M:1 + IbsDcL1tlbHit1G:1 + IbsDcL2tlbHit2M:1 + IbsDcMiss:1 + IbsDcMisAcc:1 + IbsDcLdBnkCon:1 + IbsDcStBnkCon:1 + IbsDcStToLdFwd:1 + IbsDcStToLdCan:1 + IbsDcWcMemAcc:1 + IbsDcUcMemAcc:1 + IbsDcLockedOp:1 + IbsDcMabHit:1 + IbsDcLinAddrValid:1 + IbsDcPhyAddrValid:1 + IbsDcL2tlbHit1G:1 + :12 + IbsDcMissLat:16 + :16 +} + +{IbsDcLinAd=0xc0011038;IBS DC linear address + IbsDcLinAd:64 +} + +{IbsDcPhysAd=0xc0011039;IBS DC physical address + IbsDcPhysAd:64 +} + +{IbsControl=0xc001103a;IBS control + LvtOffset:4 + :4 + LvtOffsetVal:1 + :55 +} + +{IbsBranchTargetAddress=0xc001103b;IBS branch target address + IbsBrTarget:64 +} + +### Local Variables: ### +### mode:shell-script ### +### End: ###

@@ -0,0 +1,1612 @@ +# Author: Andreas Herrmann <andreas.herrmann3@amd.com> +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. + +# This file contains information from: +# - "43170 Rev 3.09 - May 02, 2011, BIOS and Kernel Developer's Guide (BKDG) +# for AMD Family 14h Models 00h-0Fh Processors" + +# See scripts/createheader.py for the general format of this register +# definitions. + +{LSMCAaddr=0x0000;load-store MCA address + ADDR:48 + :16 +} # alias of MC0_ADDR + +{LSMCAstatus=0x0001;load-store MCE status + ErrorCode:16 + ErrorCodeExt:4 + :37 + PCC:1 + AddrV:1 + :1 + En:1 + UC:1 + OVER:1 + VAL:1 +} # alias of MC0_STATUS + +{TSC=0x0010;time-stamp counter + TSC:64 +} + +{APIC_BASE=0x001b;APIC base address + :8 + BSC:1 + :2 + ApicEn:1 + ApicBar:28 + :24 +} + +{EBL_CR_POWERON=0x002a;cluster ID + :16 + ClusterID:2 + :46 +} + +{PATCH_LEVEL=0x008b;microcode patch level + PATCH_LEVEL:32 + :32 +} + +{MPERF=0x00e7;max performance frequency clock count + MPERF:64 +} + +{APERF=0x00e8;actual performance frequency clock count + APERF:64 +} + +{MTRRcap=0x00fe;MTRR capabilities + MtrrCapVCnt:8 + MtrrCapFix:1 + :1 + MtrrCapWc:1 + :53 +} + +{SYSENTER_CS=0x0174;SYSENTER/SYSEXIT code segment selector + SYSENTER_CS:16 + :48 +} + +{SYSENTER_ESP=0x0175;SYSENTER/SYSEXIT stack pointer + SYSENTER_ESP:32 + :32 +} + +{SYSENTER_EIP=0x0176;SYSENTER/SYSEXIT instruction pointer + SYSENTER_EIP:32 + :32 +} + +{MCG_CAP=0x0179;global MC capabilities + Count:8 + MCG_CTL_P:1 + :55 +} + +{MCG_STAT=0x017a;global MC status + RIPV:1 + EIPV:1 + MCIP:1 + :61 +} + +{MCG_CTL=0x017b;global MC control + MC0En:1 + MC1En:1 + MC2En:1 + MC3En:1 + MC4En:1 + MC5En:1 + :58 +} + +{DBG_CTL_MSR=0x01d9;debug control + LBR:1 + BTF:1 + PB0:1 + PB1:1 + PB2:1 + PB3:1 + :58 +} + +{BR_FROM=0x01db;last branch from IP + LastBranchFromIP:64 +} + +{BR_TO=0x01dc;last branch to IP + LastBranchToIP:64 +} + +{LastExceptionFromIP=0x01dd;last exception from IP + LastIntFromIP:64 +} + +{LastExceptionToIP=0x01de;last exception to IP + LastIntToIP:64 +} + +{MTRRphysBase0=0x0200;base of variable-size MTRR (0) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:24 + :28 +} + +{MTRRphysMask0=0x0201;mask of variable-size MTRR (0) + :11 + Valid:1 + PhysMask:24 + :28 +} + +{MTRRphysBase1=0x0202;base of variable-size MTRR (1) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:24 + :28 +} + +{MTRRphysMask1=0x0203;mask of variable-size MTRR (1) + :11 + Valid:1 + PhysMask:24 + :28 +} + +{MTRRphysBase2=0x0204;base of variable-size MTRR (2) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:24 + :28 +} + +{MTRRphysMask2=0x0205;mask of variable-size MTRR (2) + :11 + Valid:1 + PhysMask:24 + :28 +} + +{MTRRphysBase3=0x0206;base of variable-size MTRR (3) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:24 + :28 +} + +{MTRRphysMask3=0x0207;mask of variable-size MTRR (3) + :11 + Valid:1 + PhysMask:24 + :28 +} + +{MTRRphysBase4=0x0208;base of variable-size MTRR (4) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:24 + :28 +} + +{MTRRphysMask4=0x0209;mask of variable-size MTRR (4) + :11 + Valid:1 + PhysMask:24 + :28 +} + +{MTRRphysBase5=0x020a;base of variable-size MTRR (5) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:24 + :28 +} + +{MTRRphysMask5=0x020b;mask of variable-size MTRR (5) + :11 + Valid:1 + PhysMask:24 + :28 +} + +{MTRRphysBase6=0x020c;base of variable-size MTRR (6) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:24 + :28 +} + +{MTRRphysMask6=0x020d;mask of variable-size MTRR (6) + :11 + Valid:1 + PhysMask:24 + :28 +} + +{MTRRphysBase7=0x020e;base of variable-size MTRR (7) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:24 + :28 +} + +{MTRRphysMask7=0x020f;mask of variable-size MTRR (7) + :11 + Valid:1 + PhysMask:24 + :28 +} + +{MTRRfix64K_00000=0x0250;fixed range MTRR + 0xxxxMemType:3 + 0xxxxWrDram:1 + 0xxxxRdDram:1 + :3 + 1xxxxMemType:3 + 1xxxxWrDram:1 + 1xxxxRdDram:1 + :3 + 2xxxxMemType:3 + 2xxxxWrDram:1 + 2xxxxRdDram:1 + :3 + 3xxxxMemType:3 + 3xxxxWrDram:1 + 3xxxxRdDram:1 + :3 + 4xxxxMemType:3 + 4xxxxWrDram:1 + 4xxxxRdDram:1 + :3 + 5xxxxMemType:3 + 5xxxxWrDram:1 + 5xxxxRdDram:1 + :3 + 6xxxxMemType:3 + 6xxxxWrDram:1 + 6xxxxRdDram:1 + :3 + 7xxxxMemType:3 + 7xxxxWrDram:1 + 7xxxxRdDram:1 + :3 +} + +{MTRRfix16K_80000=0x0258;fixed range MTRR + 80xxxMemType:3 + 80xxxWrDram:1 + 80xxxRdDram:1 + :3 + 84xxxMemType:3 + 84xxxWrDram:1 + 84xxxRdDram:1 + :3 + 88xxxMemType:3 + 88xxxWrDram:1 + 88xxxRdDram:1 + :3 + 8CxxxMemType:3 + 8CxxxWrDram:1 + 8CxxxRdDram:1 + :3 + 90xxxMemType:3 + 90xxxWrDram:1 + 90xxxRdDram:1 + :3 + 94xxxMemType:3 + 94xxxWrDram:1 + 94xxxRdDram:1 + :3 + 98xxxMemType:3 + 98xxxWrDram:1 + 98xxxRdDram:1 + :3 + 9CxxxMemType:3 + 9CxxxWrDram:1 + 9CxxxRdDram:1 + :3 +} + +{MTRRfix16K_A0000=0x0259;fixed range MTRR + A0xxxMemType:3 + A0xxxWrDram:1 + A0xxxRdDram:1 + :3 + A4xxxMemType:3 + A4xxxWrDram:1 + A4xxxRdDram:1 + :3 + A8xxxMemType:3 + A8xxxWrDram:1 + A8xxxRdDram:1 + :3 + ACxxxMemType:3 + ACxxxWrDram:1 + ACxxxRdDram:1 + :3 + B0xxxMemType:3 + B0xxxWrDram:1 + B0xxxRdDram:1 + :3 + B4xxxMemType:3 + B4xxxWrDram:1 + B4xxxRdDram:1 + :3 + B8xxxMemType:3 + B8xxxWrDram:1 + B8xxxRdDram:1 + :3 + BCxxxMemType:3 + BCxxxWrDram:1 + BCxxxRdDram:1 + :3 +} + +{MTRRfix4K_C0000=0x0268;fixed range MTRR + C0xxxMemType:3 + C0xxxWrDram:1 + C0xxxRdDram:1 + :3 + C1xxxMemType:3 + C1xxxWrDram:1 + C1xxxRdDram:1 + :3 + C2xxxMemType:3 + C2xxxWrDram:1 + C2xxxRdDram:1 + :3 + C3xxxMemType:3 + C3xxxWrDram:1 + C3xxxRdDram:1 + :3 + C4xxxMemType:3 + C4xxxWrDram:1 + C4xxxRdDram:1 + :3 + C5xxxMemType:3 + C5xxxWrDram:1 + C5xxxRdDram:1 + :3 + C6xxxMemType:3 + C6xxxWrDram:1 + C6xxxRdDram:1 + :3 + C7xxxMemType:3 + C7xxxWrDram:1 + C7xxxRdDram:1 + :3 +} + +{MTRRfix4K_C8000=0x0269;fixed range MTRR + C8xxxMemType:3 + C8xxxWrDram:1 + C8xxxRdDram:1 + :3 + C9xxxMemType:3 + C9xxxWrDram:1 + C9xxxRdDram:1 + :3 + CAxxxMemType:3 + CAxxxWrDram:1 + CAxxxRdDram:1 + :3 + CBxxxMemType:3 + CBxxxWrDram:1 + CBxxxRdDram:1 + :3 + CCxxxMemType:3 + CCxxxWrDram:1 + CCxxxRdDram:1 + :3 + CDxxxMemType:3 + CDxxxWrDram:1 + CDxxxRdDram:1 + :3 + CExxxMemType:3 + CExxxWrDram:1 + CExxxRdDram:1 + :3 + CFxxxMemType:3 + CFxxxWrDram:1 + CFxxxRdDram:1 + :3 +} + +{MTRRfix4K_D0000=0x026a;fixed range MTRR + D0xxxMemType:3 + D0xxxWrDram:1 + D0xxxRdDram:1 + :3 + D1xxxMemType:3 + D1xxxWrDram:1 + D1xxxRdDram:1 + :3 + D2xxxMemType:3 + D2xxxWrDram:1 + D2xxxRdDram:1 + :3 + D3xxxMemType:3 + D3xxxWrDram:1 + D3xxxRdDram:1 + :3 + D4xxxMemType:3 + D4xxxWrDram:1 + D4xxxRdDram:1 + :3 + D5xxxMemType:3 + D5xxxWrDram:1 + D5xxxRdDram:1 + :3 + D6xxxMemType:3 + D6xxxWrDram:1 + D6xxxRdDram:1 + :3 + D7xxxMemType:3 + D7xxxWrDram:1 + D7xxxRdDram:1 + :3 +} + +{MTRRfix4K_D8000=0x026b;fixed range MTRR + D8xxxMemType:3 + D8xxxWrDram:1 + D8xxxRdDram:1 + :3 + D9xxxMemType:3 + D9xxxWrDram:1 + D9xxxRdDram:1 + :3 + DAxxxMemType:3 + DAxxxWrDram:1 + DAxxxRdDram:1 + :3 + DBxxxMemType:3 + DBxxxWrDram:1 + DBxxxRdDram:1 + :3 + DCxxxMemType:3 + DCxxxWrDram:1 + DCxxxRdDram:1 + :3 + DDxxxMemType:3 + DDxxxWrDram:1 + DDxxxRdDram:1 + :3 + DExxxMemType:3 + DExxxWrDram:1 + DExxxRdDram:1 + :3 + DFxxxMemType:3 + DFxxxWrDram:1 + DFxxxRdDram:1 + :3 +} + +{MTRRfix4K_E0000=0x026c;fixed range MTRR + E0xxxMemType:3 + E0xxxWrDram:1 + E0xxxRdDram:1 + :3 + E1xxxMemType:3 + E1xxxWrDram:1 + E1xxxRdDram:1 + :3 + E2xxxMemType:3 + E2xxxWrDram:1 + E2xxxRdDram:1 + :3 + E3xxxMemType:3 + E3xxxWrDram:1 + E3xxxRdDram:1 + :3 + E4xxxMemType:3 + E4xxxWrDram:1 + E4xxxRdDram:1 + :3 + E5xxxMemType:3 + E5xxxWrDram:1 + E5xxxRdDram:1 + :3 + E6xxxMemType:3 + E6xxxWrDram:1 + E6xxxRdDram:1 + :3 + E7xxxMemType:3 + E7xxxWrDram:1 + E7xxxRdDram:1 + :3 +} + +{MTRRfix4K_E8000=0x026d;fixed range MTRR + E8xxxMemType:3 + E8xxxWrDram:1 + E8xxxRdDram:1 + :3 + E9xxxMemType:3 + E9xxxWrDram:1 + E9xxxRdDram:1 + :3 + EAxxxMemType:3 + EAxxxWrDram:1 + EAxxxRdDram:1 + :3 + EBxxxMemType:3 + EBxxxWrDram:1 + EBxxxRdDram:1 + :3 + ECxxxMemType:3 + ECxxxWrDram:1 + ECxxxRdDram:1 + :3 + EDxxxMemType:3 + EDxxxWrDram:1 + EDxxxRdDram:1 + :3 + EExxxMemType:3 + EExxxWrDram:1 + EExxxRdDram:1 + :3 + EFxxxMemType:3 + EFxxxWrDram:1 + EFxxxRdDram:1 + :3 +} + +{MTRRfix4K_F0000=0x026e;fixed range MTRR + F0xxxMemType:3 + F0xxxWrDram:1 + F0xxxRdDram:1 + :3 + F1xxxMemType:3 + F1xxxWrDram:1 + F1xxxRdDram:1 + :3 + F2xxxMemType:3 + F2xxxWrDram:1 + F2xxxRdDram:1 + :3 + F3xxxMemType:3 + F3xxxWrDram:1 + F3xxxRdDram:1 + :3 + F4xxxMemType:3 + F4xxxWrDram:1 + F4xxxRdDram:1 + :3 + F5xxxMemType:3 + F5xxxWrDram:1 + F5xxxRdDram:1 + :3 + F6xxxMemType:3 + F6xxxWrDram:1 + F6xxxRdDram:1 + :3 + F7xxxMemType:3 + F7xxxWrDram:1 + F7xxxRdDram:1 + :3 +} + +{MTRRfix4K_F8000=0x026f;fixed range MTRR + F8xxxMemType:3 + F8xxxWrDram:1 + F8xxxRdDram:1 + :3 + F9xxxMemType:3 + F9xxxWrDram:1 + F9xxxRdDram:1 + :3 + FAxxxMemType:3 + FAxxxWrDram:1 + FAxxxRdDram:1 + :3 + FBxxxMemType:3 + FBxxxWrDram:1 + FBxxxRdDram:1 + :3 + FCxxxMemType:3 + FCxxxWrDram:1 + FCxxxRdDram:1 + :3 + FDxxxMemType:3 + FDxxxWrDram:1 + FDxxxRdDram:1 + :3 + FExxxMemType:3 + FExxxWrDram:1 + FExxxRdDram:1 + :3 + FFxxxMemType:3 + FFxxxWrDram:1 + FFxxxRdDram:1 + :3 +} + +{PAT=0x0277;page attribute table + PA0MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA1MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA2MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA3MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA4MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA5MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA6MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA7MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 +} + +{MTRRdefType=0x02ff;MTRR default memory type + MemType:8 + :2 + MtrrDefTypeFixEn:1 + MtrrDefTypeEn:1 + :52 +} + +{MC0_CTL=0x0400;data cache MC control + :2 + DDP:1 + DTP:1 + :2 + TLBP:1 + :1 + SRDEL:1 + SRDES:1 + SRDET:1 + SRDE_ALL:1 + :52 +} + +{MC0_STATUS=0x0401;data cache MC status + ErrorCode:16 + ErrorCodeExt:4 + :37 + PCC:1 + AddrV:1 + :1 + En:1 + UC:1 + OVER:1 + VAL:1 +} + +{MC0_ADDR=0x0402;data cache MC address + ADDR:48 + :16 +} + +{MC0_MISC=0x0403;data cache MC miscellaneous + :64 +} + +{MC1_CTL=0x0404;instruction cache MC control + :2 + IDP:1 + ITP:1 + ISTP:1 + :1 + TLBP:1 + :2 + SRDE:1 + :54 +} + +{MC1_STATUS=0x0405;instruction cache MC status + ErrorCode:16 + ErrorCodeExt:4 + :37 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + OVER:1 + VAL:1 +} + +{MC1_ADDR=0x0406;instruction cache MC address + ADDR:48 + :16 +} + +{MC1_MISC=0x0407;instruction cache MC miscellaneous + :64 +} + +{MC2_CTL=0x0408;bus unit MC control + :4 + TagCor:1 + TagUncor:1 + DataParity:1 + DataCor:1 + DataUncor:1 + :3 + TagMultiHit:1 + AttrParity:1 + :50 +} + +{MC2_STATUS=0x0409;bus unit MC status + ErrorCode:16 + ErrorCodeExt:5 + :24 + UECC:1 + CECC:1 + :10 + PCC:1 + AddrV:1 + :1 + En:1 + UC:1 + OVER:1 + VAL:1 +} + +{MC2_ADDR=0x040a;bus unit MC address register + ADDR:36 + :28 +} + +{MC2_MISC=0x040b;bus unit MC miscellaneous + :64 +} + +{MC3_CTL=0x040c;reserved + :64 +} + +{MC3_STATUS=0x040d;reserved + :64 +} + +{MC3_ADDR=0x040e;reserved + :64 +} + +{MC3_MISC=0x040f;reserved + :64 +} + +{MC4_CTL=0x0410;northbridge MC control + :5 + SyncFloodEn:1 + :2 + MstrAbrtEn:1 + TgtAbrtEn:1 + :1 + AtomicRMWEn:1 + WDTRptEn:1 + DevErrEn:1 + :2 + NbIntProtEn:1 + CpPktDatEn:1 + :7 + UsPwDatErrEn:1 + :38 +} + +{MC4_STATUS=0x0411;northbridge MC status + ErrorCode:16 + ErrorCodeExt:5 + :11 + ErrCpu0:1 + ErrCpu1:1 + :2 + BusErr:1 + :20 + PCC:1 + AddrV:1 + :1 + En:1 + UC:1 + Over:1 + Val:1 +} + +{MC4_ADDR=0x0412;northbridge MC address + McaNbAddrLow:32 + McaNbAddrHigh:32 +} + +{MC4_MISC0=0x0413;reserved (northbridge MC misc) + :64 +} + +{MC5_CTL=0x0414;reorder buffer MC control + CPUWDT:1 + :63 +} + +{MC5_STATUS=0x0415;reorder buffer MC status + ErrorCode:16 + :41 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + OVER:1 + VAL:1 +} + +{MC5_ADDR=0x0416;reorder buffer MC address + ADDR:48 + :16 +} + +{MC5_MISC=0x0417;reorder buffer MC miscellaneous + FrCompl:8 + :56 +} + +{EFER=0xc0000080;extended feature enable + SYSCALL:1 + :7 + LME:1 + :1 + LMA:1 + NXE:1 + SVME:1 + LMSLE:1 + FFXSE:1 + :49 +} + +{STAR=0xc0000081;SYSCALL target address + Target:32 + SysCallSel:16 + SysRetSel:16 +} + +{STAR64=0xc0000082;long mode SYSCALL target address + LSTAR:64 +} + +{STARCOMPAT=0xc0000083;compat mode SYSCALL target address + CSTAR:64 +} + +{SYSCALL_FLAG_MASK=0xc0000084;SYSCALL flag mask + MASK:32 + :32 +} + +{FS_BASE=0xc0000100;FS base + FS_BASE:64 +} + +{GS_BASE=0xc0000101;GS base + GS_BASE:64 +} + +{KernelGSbase=0xc0000102;kernel GS base + KernelGSBase:64 +} + +{TSC_AUX=0xc0000103;auxiliary time stamp counter data + TscAux:32 + :32 +} + +{PERF_CTL0=0xc0010000;performance event select (0) + EventSelect:8 + UnitMask:8 + User:1 + OS:1 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + GuestOnly:1 + HostOnly:1 + :22 +} + +{PERF_CTL1=0xc0010001;performance event select (1) + EventSelect:8 + UnitMask:8 + User:1 + OS:1 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + GuestOnly:1 + HostOnly:1 + :22 +} + +{PERF_CTL2=0xc0010002;performance event select (2) + EventSelect:8 + UnitMask:8 + User:1 + OS:1 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + GuestOnly:1 + HostOnly:1 + :22 +} + +{PERF_CTL3=0xc0010003;performance event select (3) + EventSelect:8 + UnitMask:8 + User:1 + OS:1 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + GuestOnly:1 + HostOnly:1 + :22 +} + +{PERF_CTR0=0xc0010004;performance event counter (0) + CTR:48 + :16 +} + +{PERF_CTR1=0xc0010005;performance event counter (1) + CTR:48 + :16 +} + +{PERF_CTR2=0xc0010006;performance event counter (2) + CTR:48 + :16 +} + +{PERF_CTR3=0xc0010007;performance event counter (3) + CTR:48 + :16 +} + +{SYS_CFG=0xc0010010;system configuration + :17 + SysUcLockEn:1 + MtrrFixDramEn:1 + MtrrFixDramModeEn:1 + MtrrVarDramEn:1 + MtrrTom2En:1 + Tom2ForceMemTypeWB:1 + :41 +} + +{HWCR=0xc0010015;hardware configuration + SmmLock:1 + :2 + TlbCacheDis:1 + INVD_WBINVD:1 + :3 + IgnneEm:1 + MonMwaitDis:1 + MonMwaitUserEn:1 + :2 + SmiSpCycDis:1 + RsmSpCycDis:1 + SseDis:1 + :1 + Wrap32Dis:1 + McStatusWrEn:1 + :1 + IoCfgGpFault:1 + MisAlignSseDis:1 + :1 + ForceUsRdWrSzPrb:1 + TscFreqSel:1 + :1 + EffFreqCntMwait:1 + :37 +} + +{IORR_BASE0=0xc0010016;base of variable I/O range (0) + :3 + WrMem:1 + RdMem:1 + :7 + PhyBase:24 + :28 +} + +{IORR_MASK0=0xc0010017;mask of variable I/O range (0) + :11 + Valid:1 + PhyMask:24 + :28 +} + +{IORR_BASE1=0xc0010018;base of variable I/O range (1) + :3 + WrMem:1 + RdMem:1 + :7 + PhyBase:24 + :28 +} + +{IORR_MASK1=0xc0010019;mask of variable I/O range (1) + :11 + Valid:1 + PhyMask:24 + :28 +} + +{TOP_MEM=0xc001001a;top of memory address + :23 + TOM:13 + :28 +} + +{TOM2=0xc001001d;second top of memory address + :23 + TOM2:13 + :28 +} + +{NB_CFG=0xc001001f;northbridge configuration + :45 + DisUsSysMgtReqToNcHt:1 + EnableCf8ExtCfg:1 + :11 + EnConvertToNonIsoc:1 + :5 +} + +{MCEredirection=0xc0010022;MCE redirection + RedirVector:8 + RedirVecEn:1 + RedirSmiEn:1 + :54 +} + +{ProcessorNameString0=0xc0010030;processor name string (0) + CpuNameString:64 +} + +{ProcessorNameString1=0xc0010031;processor name string (1) + CpuNameString:64 +} + +{ProcessorNameString2=0xc0010032;processor name string (2) + CpuNameString:64 +} + +{ProcessorNameString3=0xc0010033;processor name string (3) + CpuNameString:64 +} + +{ProcessorNameString4=0xc0010034;processor name string (4) + CpuNameString:64 +} + +{ProcessorNameString5=0xc0010035;processor name string (5) + CpuNameString:64 +} + +{MC0_CTL_MASK=0xc0010044;data cache MC control mask + :2 + DDP:1 + DTP:1 + :2 + TLBP:1 + :1 + SRDEL:1 + SRDES:1 + SRDET:1 + SRDE_ALL:1 + :52 +} + +{MC1_CTL_MASK=0xc0010045;instruction cache MC control mask + :2 + IDP:1 + ITP:1 + ISTP:1 + :1 + TLBP:1 + :2 + SRDE:1 + :54 +} + +{MC2_CTL_MASK=0xc0010046;bus unit MC control mask + :4 + TagCor:1 + TagUncor:1 + DataParity:1 + DataCor:1 + DataUncor:1 + :3 + TagMultiHit:1 + AttrParity:1 + :50 +} + +{MC3_CTL_MASK=0xc0010047;reserved + :64 +} + +{MC4_CTL_MASK=0xc0010048;northbridge MC control mask + :5 + SyncFloodEn:1 + :2 + MstrAbrtEn:1 + TgtAbrtEn:1 + :1 + AtomicRMWEn:1 + WDTRptEn:1 + DevErrEn:1 + :2 + NbIntProtEn:1 + CpPktDatEn:1 + :7 + UsPwDatErrEn:1 + :38 +} + +{MC5_CTL_MASK=0xc0010049;reorder buffer MC control mask + CPUWDT:1 + :63 +} + +{SMI_ON_IO_TRAP_0=0xc0010050;IO trap address (0) + SmiAddr:32 + SmiMask:24 + :5 + ConfigSmi:1 + SmiOnWrEn:1 + SmiOnRdEn:1 +} + +{SMI_ON_IO_TRAP_1=0xc0010051;IO trap address (1) + SmiAddr:32 + SmiMask:24 + :5 + ConfigSmi:1 + SmiOnWrEn:1 + SmiOnRdEn:1 +} + +{SMI_ON_IO_TRAP_2=0xc0010052;IO trap address (2) + SmiAddr:32 + SmiMask:24 + :5 + ConfigSmi:1 + SmiOnWrEn:1 + SmiOnRdEn:1 +} + +{SMI_ON_IO_TRAP_3=0xc0010053;IO trap address (3) + SmiAddr:32 + SmiMask:24 + :5 + ConfigSmi:1 + SmiOnWrEn:1 + SmiOnRdEn:1 +} + +{SMI_ON_IO_TRAP_CTL_STS=0xc0010054;IO trap control + :1 + SmiEn_0:1 + :1 + SmiEn_1:1 + :1 + SmiEn_2:1 + :1 + SmiEn_3:1 + :7 + IoTrapEn:1 + :48 +} + +{IntPendingMessage=0xc0010055;reserved + :64 +} + +{SmiTriggerIoCycle=0xc0010056;SMI trigger IO cycle + IoPortAddress:16 + IoData:8 + :1 + IoCycleEn:1 + IoRd:1 + :37 +} + +{MmioConfigBase=0xc0010058;MMIO configuration base address + Enable:1 + :1 + SegBusRange:4;0=1;1=2;2=4;3=8;4=16;5=32;6=64;7=128;8=256 + :14 + MmiocCfgBaseAddr:16 + :28 +} + +{BISTResults=0xc0010060;BIST Results + BistResults:30 + :34 +} + +{PstateCurrentLimit=0xc0010061;P-state current limit + CurPstateLimit:3 + :1 + PstateMaxVal:3 + :57 +} + +{PstateControl=0xc0010062;P-state control + PstateCmd:3 + :61 +} + +{PstateStatus=0xc0010063;P-state status + CurPstate:3 + :61 +} + +{Pstate0=0xc0010064;P-state 0 + CpuDidLSD:4 + CpuDidMSD:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate1=0xc0010065;P-state 1 + CpuDidLSD:4 + CpuDidMSD:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate2=0xc0010066;P-state 2 + CpuDidLSD:4 + CpuDidMSD:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate3=0xc0010067;P-state 3 + CpuDidLSD:4 + CpuDidMSD:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate4=0xc0010068;P-state 4 + CpuDidLSD:4 + CpuDidMSD:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate5=0xc0010069;P-state 5 + CpuDidLSD:4 + CpuDidMSD:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate6=0xc001006a;P-state 6 + CpuDidLSD:4 + CpuDidMSD:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate7=0xc001006b;P-state 7 + CpuDidLSD:4 + CpuDidMSD:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{COFVIDstatus=0xc0010071;COFVID status + CurCpuDidLSD:4 + CurCpuDidMSD:5 + CurCpuVid:7 + CurPstate:3 + :1 + PstateInProgress:1 + :4 + CurNbVid:7 + StartupPstate:3 + MaxVid:7 + MinVid:7 + MainPllOpFreqIdMax:6 + :1 + CurPstateLimit:3 + :5 +} + +{CstateAddress=0xc0010073;C-state address + CstateAddr:16 + :48 +} + +{CpuWdTmrCfg=0xc0010074;CPU watchdog timer + CpuWdtEn:1 + CpuWdtTimeBase:2 + CpuWdtCountSel:4 + :57 +} + +{SMM_BASE=0xc0010111;SMM base address + SMM_BASE:32 + :32 +} + +{SMMAddr=0xc0010112;SMM TSeg base address + :17 + TSegBase:19 + :28 +} + +{SMMMask=0xc0010113;SMM Tseg mask + AValid:1 + TValid:1 + AClose:1 + TClose:1 + AMTypeIoWc:1 + TMTypeIoWc:1 + :2 + AMTypeDram:3 + :1 + TMTypeDram:3 + :2 + TSegMask:19 + :28 +} + +{VM_CR=0xc0010114;virtual machine control + dpd:1 + r_init:1 + dis_a20m:1 + Lock:1 + Svme_Disable:1 + :59 +} + +{IGNNE=0xc0010115;IGNNE + IGNNE:1 + :63 +} + +# {SMM_CTL=0xc0010116;SMM control +# smm_dismiss:1 +# smm_enter:1 +# smi_cyle:1 +# smm_exit:1 +# rsm_cycle:1 +# :59 +# } # write-only + +{VM_HSAVE_PA=0xc0010117;virtual machine host save physical address + :12 + VM_HSAVE_PA:24 + :28 +} + +# {SVMLock=0xc0010118;SVM lock key +# SvmLockKey:64 +# } # write-only + +{SMIstatus=0xc001011a;local SMI status + IoTrapSts:4 + :4 + MceRedirSts:1 + :7 + SmiSrcLvtLcy:1 + SmiSrcLvtExt:1 + :46 +} + +{OSVW_ID_Length=0xc0010140;OS visible work-around + OSVW_ID_Length:16 + :48 +} + +{OsvwStatus=0xc0010141;OS visible work-around status bits + OsvwStatusBits:64 +} + +{CPUIDFeatures=0xc0011004;CPUID features + FeaturesEdx:32 + FeaturesEcx:32 +} + +{CPUIDExtFeatures=0xc0011005;extended CPUID features + ExtFeaturesEdx:32 + ExtFeaturesEcx:32 +} + +{LS_CFG=0xc0011020;load store configuration + :28 + DisStreamSt:1 + :35 +} + +{IC_CFG=0xc0011021;instruction cache configuration + :9 + DIS_SPEC_TLB_RLD:1 + :54 +} + +{DC_CFG=0xc0011022;data cache configuration + :13 + DIS_HW_PF:1 + :50 +} + +{IbsFetchCtl=0xc0011030;IBS fetch control + IbsFetchMaxCnt:16 + IbsFetchCnt:16 + IbsFetchLat:16 + IbsFetchEn:1 + IbsFetchVal:1 + IbsFetchComp:1 + IbsIcMiss:1 + IbsPhyAddrValid:1 + IbsL1TlbPgSz:2 + IbsL1TlbMiss:1 + IbsL2TlbMiss:1 + IbsRandEn:1 + :6 +} + +{IbsFetchLinAd=0xc0011031;IBS fetch linear address + IbsFetchLinAd:64 +} + +{IbsFetchPhysAd=0xc0011032;IBS fetch physical address + IbsFetchPhysAd:36 + :28 +} + +{IbsOpCtl=0xc0011033;IBS execution control + IbsOpMaxCnt:16 + :1 + IbsOpEn:1 + IbsOpVal:1 + IbsOpCntCtl:1 + IbsOpMaxCntExt:7 + :5 + IbsOpCurCnt:20 + IbsOpCurCntExt:7 + :5 +} + +{IbsOpRip=0xc0011034;IBS Op logical address + IbsOpRip:64 +} + +{IbsOpData=0xc0011035;IBS Op data + IbsCompToRetCtr:16 + IbsTagToRetCtr:16 + IbsOpBrnResync:1 + IbsOpMispReturn:1 + IbsOpReturn:1 + IbsOpBrnTaken:1 + IbsOpBrnMisp:1 + IbsOpBrnRet:1 + IbsRipInvalid:1 + :25 +} + +{IbsOpData2=0xc0011036;IBS Op data 2 + NbIbsReqSrc:3 + :61 +} + +{IbsOpData3=0xc0011037;IBS Op data 3 + IbsLdOp:1 + IbsStOp:1 + IbsDcL1tlbMiss:1 + IbsDcL2tlbMiss:1 + IbsDcL1tlbHit2M:1 + :1 + IbsDcL2tlbHit2M:1 + IbsDcMiss:1 + IbsDcMisAcc:1 + :2 + IbsDcStToLdFwd:1 + :1 + IbsDcWcMemAcc:1 + IbsDcUcMemAcc:1 + IbsDcLockedOp:1 + IbsDcMabHit:1 + IbsDcLinAddrValid:1 + IbsDcPhyAddrValid:1 + :13 + IbsDcMissLat:16 + :16 +} + +{IbsDcLinAd=0xc0011038;IBS DC linear address + IbsDcLinAd:64 +} + +{IbsDcPhysAd=0xc0011039;IBS DC physical address + IbsDcPhysAd:36 + :28 +} + +{IbsControl=0xc001103a;IBS control + LvtOffset:4 + :4 + LvtOffsetVal:1 + :55 +} + +{IbsBranchTargetAddress=0xc001103b;IBS branch target address + IbsBrTarget:64 +} + +### Local Variables: ### +### mode:shell-script ### +### End: ###

@@ -0,0 +1,2167 @@ +# Author: Andreas Herrmann <andreas.herrmann3@amd.com> +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This file contains information from: +# - "42301 Rev 3.02 - October 18, 2011, BIOS and Kernel Developer's +# Guide (BKDG) for AMD Family 15h Models 00h-0Fh Processors" + +# See scripts/createheader.py for the general format of this register +# definitions. + +{LSMCAaddr=0x0000;load-store MCA address + ADDR:64 +} # alias of MC0_ADDR + +{LSMCAstatus=0x0001;load-store MCE status + ErrorCode:16 + ErrorCodeExt:5 + :15 + Way:4 + :3 + Poison:1 + Deferred:1 + :12 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + Overflow:1 + Val:1 +} # alias of MC0_STATUS + +{TSC=0x0010;time-stamp counter + TSC:64 +} + +{APIC_BASE=0x001b;APIC base address + :8 + BSC:1 + :1 + Apicx2En:1 + ApicEn:1 + ApicBar:28 + :24 +} + +{EBL_CR_POWERON=0x002a;cluster ID + :16 + ClusterID:2 + :46 +} + +{PATCH_LEVEL=0x008b;microcode patch level (sharedC) + PATCH_LEVEL:32 + :32 +} + +{MPERF=0x00e7;max performance frequency clock count + MPERF:64 +} + +{APERF=0x00e8;actual performance frequency clock count + APERF:64 +} + +{MTRRcap=0x00fe;MTRR capabilities + MtrrCapVCnt:8 + MtrrCapFix:1 + :1 + MtrrCapWc:1 + :53 +} + +{SYSENTER_CS=0x0174;SYSENTER/SYSEXIT code segment selector + SYSENTER_CS:16 + :48 +} + +{SYSENTER_ESP=0x0175;SYSENTER/SYSEXIT stack pointer + SYSENTER_ESP:32 + :32 +} + +{SYSENTER_EIP=0x0176;SYSENTER/SYSEXIT instruction pointer + SYSENTER_EIP:32 + :32 +} + +{MCG_CAP=0x0179;global MC capabilities + Count:8 + MCG_CTL_P:1 + :55 +} + +{MCG_STAT=0x017a;global MC status + RIPV:1 + EIPV:1 + MCIP:1 + :61 +} + +{MCG_CTL=0x017b;global MC control + LS:1 + IF:1 + CU:1 + :1 + NB:1 + EX:1 + FP:1 + :57 +} + +{DBG_CTL_MSR=0x01d9;debug control + LBR:1 + BTF:1 + PB0:1 + PB1:1 + PB2:1 + PB3:1 + :58 +} + +{BR_FROM=0x01db;last branch from IP + LastBranchFromIP:64 +} + +{BR_TO=0x01dc;last branch to IP + LastBranchToIP:64 +} + +{LastExceptionFromIP=0x01dd;last exception from IP + LastIntFromIP:64 +} + +{LastExceptionToIP=0x01de;last exception to IP + LastIntToIP:64 +} + +{MTRRphysBase0=0x0200;base of variable-size MTRR (0) (sharedC) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:36 + :16 +} + +{MTRRphysMask0=0x0201;mask of variable-size MTRR (0) (sharedC) + :11 + Valid:1 + PhysMask:36 + :16 +} + +{MTRRphysBase1=0x0202;base of variable-size MTRR (1) (sharedC) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:36 + :16 +} + +{MTRRphysMask1=0x0203;mask of variable-size MTRR (1) (sharedC) + :11 + Valid:1 + PhysMask:36 + :16 +} + +{MTRRphysBase2=0x0204;base of variable-size MTRR (2) (sharedC) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:36 + :16 +} + +{MTRRphysMask2=0x0205;mask of variable-size MTRR (2) (sharedC) + :11 + Valid:1 + PhysMask:36 + :16 +} + +{MTRRphysBase3=0x0206;base of variable-size MTRR (3) (sharedC) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:36 + :16 +} + +{MTRRphysMask3=0x0207;mask of variable-size MTRR (3) (sharedC) + :11 + Valid:1 + PhysMask:36 + :16 +} + +{MTRRphysBase4=0x0208;base of variable-size MTRR (4) (sharedC) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:36 + :16 +} + +{MTRRphysMask4=0x0209;mask of variable-size MTRR (4) (sharedC) + :11 + Valid:1 + PhysMask:36 + :16 +} + +{MTRRphysBase5=0x020a;base of variable-size MTRR (5) (sharedC) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:36 + :16 +} + +{MTRRphysMask5=0x020b;mask of variable-size MTRR (5) (sharedC) + :11 + Valid:1 + PhysMask:36 + :16 +} + +{MTRRphysBase6=0x020c;base of variable-size MTRR (6) (sharedC) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:36 + :16 +} + +{MTRRphysMask6=0x020d;mask of variable-size MTRR (6) (sharedC) + :11 + Valid:1 + PhysMask:36 + :16 +} + +{MTRRphysBase7=0x020e;base of variable-size MTRR (7) (sharedC) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:36 + :16 +} + +{MTRRphysMask7=0x020f;mask of variable-size MTRR (7) (sharedC) + :11 + Valid:1 + PhysMask:36 + :16 +} + +{MTRRfix64K_00000=0x0250;fixed range MTRR (sharedC) + 0xxxxMemType:3 + 0xxxxWrDram:1 + 0xxxxRdDram:1 + :3 + 1xxxxMemType:3 + 1xxxxWrDram:1 + 1xxxxRdDram:1 + :3 + 2xxxxMemType:3 + 2xxxxWrDram:1 + 2xxxxRdDram:1 + :3 + 3xxxxMemType:3 + 3xxxxWrDram:1 + 3xxxxRdDram:1 + :3 + 4xxxxMemType:3 + 4xxxxWrDram:1 + 4xxxxRdDram:1 + :3 + 5xxxxMemType:3 + 5xxxxWrDram:1 + 5xxxxRdDram:1 + :3 + 6xxxxMemType:3 + 6xxxxWrDram:1 + 6xxxxRdDram:1 + :3 + 7xxxxMemType:3 + 7xxxxWrDram:1 + 7xxxxRdDram:1 + :3 +} + +{MTRRfix16K_80000=0x0258;fixed range MTRR (sharedC) + 80xxxMemType:3 + 80xxxWrDram:1 + 80xxxRdDram:1 + :3 + 84xxxMemType:3 + 84xxxWrDram:1 + 84xxxRdDram:1 + :3 + 88xxxMemType:3 + 88xxxWrDram:1 + 88xxxRdDram:1 + :3 + 8CxxxMemType:3 + 8CxxxWrDram:1 + 8CxxxRdDram:1 + :3 + 90xxxMemType:3 + 90xxxWrDram:1 + 90xxxRdDram:1 + :3 + 94xxxMemType:3 + 94xxxWrDram:1 + 94xxxRdDram:1 + :3 + 98xxxMemType:3 + 98xxxWrDram:1 + 98xxxRdDram:1 + :3 + 9CxxxMemType:3 + 9CxxxWrDram:1 + 9CxxxRdDram:1 + :3 +} + +{MTRRfix16K_A0000=0x0259;fixed range MTRR (sharedC) + A0xxxMemType:3 + A0xxxWrDram:1 + A0xxxRdDram:1 + :3 + A4xxxMemType:3 + A4xxxWrDram:1 + A4xxxRdDram:1 + :3 + A8xxxMemType:3 + A8xxxWrDram:1 + A8xxxRdDram:1 + :3 + ACxxxMemType:3 + ACxxxWrDram:1 + ACxxxRdDram:1 + :3 + B0xxxMemType:3 + B0xxxWrDram:1 + B0xxxRdDram:1 + :3 + B4xxxMemType:3 + B4xxxWrDram:1 + B4xxxRdDram:1 + :3 + B8xxxMemType:3 + B8xxxWrDram:1 + B8xxxRdDram:1 + :3 + BCxxxMemType:3 + BCxxxWrDram:1 + BCxxxRdDram:1 + :3 +} + +{MTRRfix4K_C0000=0x0268;fixed range MTRR (sharedC) + C0xxxMemType:3 + C0xxxWrDram:1 + C0xxxRdDram:1 + :3 + C1xxxMemType:3 + C1xxxWrDram:1 + C1xxxRdDram:1 + :3 + C2xxxMemType:3 + C2xxxWrDram:1 + C2xxxRdDram:1 + :3 + C3xxxMemType:3 + C3xxxWrDram:1 + C3xxxRdDram:1 + :3 + C4xxxMemType:3 + C4xxxWrDram:1 + C4xxxRdDram:1 + :3 + C5xxxMemType:3 + C5xxxWrDram:1 + C5xxxRdDram:1 + :3 + C6xxxMemType:3 + C6xxxWrDram:1 + C6xxxRdDram:1 + :3 + C7xxxMemType:3 + C7xxxWrDram:1 + C7xxxRdDram:1 + :3 +} + +{MTRRfix4K_C8000=0x0269;fixed range MTRR (sharedC) + C8xxxMemType:3 + C8xxxWrDram:1 + C8xxxRdDram:1 + :3 + C9xxxMemType:3 + C9xxxWrDram:1 + C9xxxRdDram:1 + :3 + CAxxxMemType:3 + CAxxxWrDram:1 + CAxxxRdDram:1 + :3 + CBxxxMemType:3 + CBxxxWrDram:1 + CBxxxRdDram:1 + :3 + CCxxxMemType:3 + CCxxxWrDram:1 + CCxxxRdDram:1 + :3 + CDxxxMemType:3 + CDxxxWrDram:1 + CDxxxRdDram:1 + :3 + CExxxMemType:3 + CExxxWrDram:1 + CExxxRdDram:1 + :3 + CFxxxMemType:3 + CFxxxWrDram:1 + CFxxxRdDram:1 + :3 +} + +{MTRRfix4K_D0000=0x026a;fixed range MTRR (sharedC) + D0xxxMemType:3 + D0xxxWrDram:1 + D0xxxRdDram:1 + :3 + D1xxxMemType:3 + D1xxxWrDram:1 + D1xxxRdDram:1 + :3 + D2xxxMemType:3 + D2xxxWrDram:1 + D2xxxRdDram:1 + :3 + D3xxxMemType:3 + D3xxxWrDram:1 + D3xxxRdDram:1 + :3 + D4xxxMemType:3 + D4xxxWrDram:1 + D4xxxRdDram:1 + :3 + D5xxxMemType:3 + D5xxxWrDram:1 + D5xxxRdDram:1 + :3 + D6xxxMemType:3 + D6xxxWrDram:1 + D6xxxRdDram:1 + :3 + D7xxxMemType:3 + D7xxxWrDram:1 + D7xxxRdDram:1 + :3 +} + +{MTRRfix4K_D8000=0x026b;fixed range MTRR (sharedC) + D8xxxMemType:3 + D8xxxWrDram:1 + D8xxxRdDram:1 + :3 + D9xxxMemType:3 + D9xxxWrDram:1 + D9xxxRdDram:1 + :3 + DAxxxMemType:3 + DAxxxWrDram:1 + DAxxxRdDram:1 + :3 + DBxxxMemType:3 + DBxxxWrDram:1 + DBxxxRdDram:1 + :3 + DCxxxMemType:3 + DCxxxWrDram:1 + DCxxxRdDram:1 + :3 + DDxxxMemType:3 + DDxxxWrDram:1 + DDxxxRdDram:1 + :3 + DExxxMemType:3 + DExxxWrDram:1 + DExxxRdDram:1 + :3 + DFxxxMemType:3 + DFxxxWrDram:1 + DFxxxRdDram:1 + :3 +} + +{MTRRfix4K_E0000=0x026c;fixed range MTRR (sharedC) + E0xxxMemType:3 + E0xxxWrDram:1 + E0xxxRdDram:1 + :3 + E1xxxMemType:3 + E1xxxWrDram:1 + E1xxxRdDram:1 + :3 + E2xxxMemType:3 + E2xxxWrDram:1 + E2xxxRdDram:1 + :3 + E3xxxMemType:3 + E3xxxWrDram:1 + E3xxxRdDram:1 + :3 + E4xxxMemType:3 + E4xxxWrDram:1 + E4xxxRdDram:1 + :3 + E5xxxMemType:3 + E5xxxWrDram:1 + E5xxxRdDram:1 + :3 + E6xxxMemType:3 + E6xxxWrDram:1 + E6xxxRdDram:1 + :3 + E7xxxMemType:3 + E7xxxWrDram:1 + E7xxxRdDram:1 + :3 +} + +{MTRRfix4K_E8000=0x026d;fixed range MTRR (sharedC) + E8xxxMemType:3 + E8xxxWrDram:1 + E8xxxRdDram:1 + :3 + E9xxxMemType:3 + E9xxxWrDram:1 + E9xxxRdDram:1 + :3 + EAxxxMemType:3 + EAxxxWrDram:1 + EAxxxRdDram:1 + :3 + EBxxxMemType:3 + EBxxxWrDram:1 + EBxxxRdDram:1 + :3 + ECxxxMemType:3 + ECxxxWrDram:1 + ECxxxRdDram:1 + :3 + EDxxxMemType:3 + EDxxxWrDram:1 + EDxxxRdDram:1 + :3 + EExxxMemType:3 + EExxxWrDram:1 + EExxxRdDram:1 + :3 + EFxxxMemType:3 + EFxxxWrDram:1 + EFxxxRdDram:1 + :3 +} + +{MTRRfix4K_F0000=0x026e;fixed range MTRR (sharedC) + F0xxxMemType:3 + F0xxxWrDram:1 + F0xxxRdDram:1 + :3 + F1xxxMemType:3 + F1xxxWrDram:1 + F1xxxRdDram:1 + :3 + F2xxxMemType:3 + F2xxxWrDram:1 + F2xxxRdDram:1 + :3 + F3xxxMemType:3 + F3xxxWrDram:1 + F3xxxRdDram:1 + :3 + F4xxxMemType:3 + F4xxxWrDram:1 + F4xxxRdDram:1 + :3 + F5xxxMemType:3 + F5xxxWrDram:1 + F5xxxRdDram:1 + :3 + F6xxxMemType:3 + F6xxxWrDram:1 + F6xxxRdDram:1 + :3 + F7xxxMemType:3 + F7xxxWrDram:1 + F7xxxRdDram:1 + :3 +} + +{MTRRfix4K_F8000=0x026f;fixed range MTRR (sharedC) + F8xxxMemType:3 + F8xxxWrDram:1 + F8xxxRdDram:1 + :3 + F9xxxMemType:3 + F9xxxWrDram:1 + F9xxxRdDram:1 + :3 + FAxxxMemType:3 + FAxxxWrDram:1 + FAxxxRdDram:1 + :3 + FBxxxMemType:3 + FBxxxWrDram:1 + FBxxxRdDram:1 + :3 + FCxxxMemType:3 + FCxxxWrDram:1 + FCxxxRdDram:1 + :3 + FDxxxMemType:3 + FDxxxWrDram:1 + FDxxxRdDram:1 + :3 + FExxxMemType:3 + FExxxWrDram:1 + FExxxRdDram:1 + :3 + FFxxxMemType:3 + FFxxxWrDram:1 + FFxxxRdDram:1 + :3 +} + +{PAT=0x0277;page attribute table + PA0MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA1MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA2MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA3MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA4MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA5MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA6MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA7MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 +} + +{MTRRdefType=0x02ff;MTRR default memory type (sharedC) + MemType:8 + :2 + MtrrDefTypeFixEn:1 + MtrrDefTypeEn:1 + :52 +} + +{MC0_CTL=0x0400;load store MC control + TagP:1 + TLBP:1 + DatP:1 + LQP:1 + SQP:1 + SCBP:1 + LineFillPoison:1 + SRDE:1 + IntErrType2:1 + IntErrType1:1 + :54 +} + +{MC0_STATUS=0x0401;load store MC status + ErrorCode:16 + ErrorCodeExt:5 + :15 + Way:4 + :3 + Poison:1 + Deferred:1 + :12 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + Overflow:1 + Val:1 +} + +{MC0_ADDR=0x0402;load store MC address + ADDR:64 +} + +{MC0_MISC=0x0403;load store MC miscellaneous + :24 + BlkPtr:8 + ErrCnt:12 + :4 + Ovrflw:1 + :2 + CntEn:1 + :10 + CntP:1 + Valid:1 +} + +{MC1_CTL=0x0404;instruction fetch MC control (sharedC) + :2 + IDP:1 + IMTP:1 + ISTP:1 + L2TP:1 + L1TP:1 + LineFillPoison:1 + :1 + SRDE:1 + :2 + PFBP:1 + PQP:1 + :1 + BSRP:1 + DEPRP:1 + DEUOPQP:1 + DEIBP:1 + DPDBE:1 + DFIFOE:1 + L2TLBM:1 + L1TLBM:1 + IVP:1 + :40 +} + +{MC1_STATUS=0x0405;instruction fetch MC status + ErrorCode:16 + ErrorCodeExt:5 + :15 + Way:4 + :3 + Poison:1 + Deferred:1 + :12 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + Overflow:1 + Val:1 +} + +{MC1_ADDR=0x0406;instruction fetch MC address + ADDR:64 +} + +{MC1_MISC=0x0407;instruction fetch MC miscellaneous + :24 + BlkPtr:8 + ErrCnt:12 + :4 + Ovrflw:1 + :2 + CntEn:1 + :10 + CntP:1 + Valid:1 +} + +{MC2_CTL=0x0408;combined unit MC control (sharedC) + L2TagMultiHit:1 + VbData:1 + WcbData:1 + WccData:1 + WccAddr:1 + PrqData:1 + PrqAddr:1 + FillData:1 + PrbAddr:1 + XabAddr:1 + L2Prefetch:1 + L2TlbData:1 + L2Tag:1 + RdData:1 + L2TlbPoison:1 + :49 +} + +{MC2_STATUS=0x0409;combined unit MC status + ErrorCode:16 + ErrorCodeExt:5 + :3 + Syndrome:4 + :8 + Way:4 + :3 + Poison:1 + Deferred:1 + UECC:1 + CECC:1 + Syndrome:8 + :2 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + Overflow:1 + Val:1 +} + +{MC2_ADDR=0x040a;combined unit MC address register + ADDR:64 +} + +{MC2_MISC=0x040b;combined unit MC miscellaneous + :24 + BlkPtr:8 + ErrCnt:12 + :4 + Ovrflw:1 + :2 + CntEn:1 + :10 + CntP:1 + Valid:1 +} + +{MC3_CTL=0x040c;reserved + :64 +} + +{MC3_STATUS=0x040d;reserved + :64 +} + +{MC3_ADDR=0x040e;reserved + :64 +} + +{MC3_MISC=0x040f;reserved + :64 +} + +{MC4_CTL=0x0410;northbridge MC control + CECCEn:1 + UECCEn:1 + CrcErrEn:3 + SyncPktEn:3 + MstrAbrtEn:1 + TgtAbrtEn:1 + GartTblWkEn:1 + AtomicRMWEn:1 + WDTRptEn:1 + :1 + L3ArrayCorEn:1 + L3ArrayUCEn:1 + ProtEn:1 + HtDataEn:1 + DramParEn:1 + RtryHtEn:4 + CrcErrEn:1 + SyncPktEn:1 + McaUsPwDatErrEn:1 + NbArrayParEn:1 + TblWlkDatErrEn:1 + :3 + McaCpuDatErrEn:1 + :32 +} + +{MC4_STATUS=0x0411;northbridge MC status + ErrorCode:16 + ErrorCodeExt:5 + :3 + Syndrome:8 + ErrCoreId:4 + Link:4 + Scrub:1 + SubLink:1 + McaStatSubCache:2 + :1 + UECC:1 + CECC:1 + Syndrome:8 + :1 + ErrCoreIdVal:1 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + Overflow:1 + Val:1 +} + +{MC4_ADDR=0x0412;northbridge MC address + :1 + ErrAddr:47 + :16 +} + +{MC4_MISC0=0x0413;northbridge MC misc (DRAM Thresholding) (0) + :24 + BlkPtr:8 + ErrCnt:12 + :4 + Ovrflw:1 + IntType:2 + CntEn:1 + LvtOffset:4 + :5 + Locked:1 + CntP:1 + Valid:1 +} + +{MC5_CTL=0x0414;execution unit MC control + :1 + PICWAK:1 + PLDAG:1 + PLDEX:1 + IDF:1 + RETDISP:1 + MAP:1 + EX0PRF:1 + EX1PRF:1 + AG0PRF:1 + AG1PRF:1 + FRF:1 + DE:1 + :51 +} + +{MC5_STATUS=0x0415;execution unit MC status + ErrorCode:16 + ErrorCodeExt:5 + :36 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + Overflow:1 + Val:1 +} + +{MC5_ADDR=0x0416;execution unit MC address + ADDR:64 +} + +{MC5_MISC=0x0417;execution unit MC miscellaneous + :24 + BlkPtr:8 + ErrCnt:12 + :4 + Ovrflw:1 + :2 + CntEn:1 + :10 + CntP:1 + Valid:1 +} + +{MC6_CTL=0x0418;floating point unit MC control (sharedC) + PRF:1 + FreeList:1 + Sched:1 + :1 + RetireQ:1 + SRF:1 + :58 +} + +{MC6_STATUS=0x0419;floating point unit MC status + ErrorCode:16 + ErrorCodeExt:5 + :36 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + Overflow:1 + Val:1 +} + +{MC6_ADDR=0x041a;floating point unit MC address + :64 +} + +{MC6_MISC=0x041b;floating point unit MC miscellaneous + :64 +} + +{EFER=0xc0000080;extended feature enable + SYSCALL:1 + :7 + LME:1 + :1 + LMA:1 + NXE:1 + SVME:1 + LMSLE:1 + FFXSE:1 + :49 +} + +{STAR=0xc0000081;SYSCALL target address + Target:32 + SysCallSel:16 + SysRetSel:16 +} + +{STAR64=0xc0000082;long mode SYSCALL target address + LSTAR:64 +} + +{STARCOMPAT=0xc0000083;compat mode SYSCALL target address + CSTAR:64 +} + +{SYSCALL_FLAG_MASK=0xc0000084;SYSCALL flag mask + MASK:32 + :32 +} + +{FS_BASE=0xc0000100;FS base + FS_BASE:64 +} + +{GS_BASE=0xc0000101;GS base + GS_BASE:64 +} + +{KernelGSbase=0xc0000102;kernel GS base + KernelGSBase:64 +} + +{TSC_AUX=0xc0000103;auxiliary time stamp counter data + TscAux:32 + :32 +} + +{TscRateMsr=0xc0000104;time stamp counter ratio + TscRateMsrFrac:32 + TscRateMsrInt:32 +} + +{LWP_CFG=0xc0000105;lightweight profile configuration + :1 + LwpVAL:1 + LwpIRE:1 + LwpBRE:1 + LwpDME:1 + LwpCNH:1 + LwpRNH:1 + :24 + LwpInt:1 + LwpCoreId:8 + LwpVector:8 + :16 +} + +{LWP_CBADDR=0xc0000106;leightweight profile control block address + :6 + LwpCbAddr:58 +} + +{MC4_MISC1=0xc0000408;northbridge MC misc (Link Thresholding) (1) + :24 + BlkPtr:8 + ErrCnt:12 + :4 + Ovrflw:1 + IntType:2 + CntEn:1 + LvtOffset:4 + :5 + Locked:1 + CntP:1 + Valid:1 +} + +{MC4_MISC2=0xc0000409;northbridge MC misc (L3 Thresholding) (2) + :24 + BlkPtr:8 + ErrCnt:12 + :4 + Ovrflw:1 + IntType:2 + CntEn:1 + LvtOffset:4 + :5 + Locked:1 + CntP:1 + Valid:1 +} + +{MC4_MISC3=0xc000040a;reserved + :64 +} + +{LEG_PERF_CTL0=0xc0010000;performance event select (0) + EventSelect:8 + UnitMask:8 + OsUserMode:2 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + HostGuestOnly:2 + :22 +} # alias of PERF_CTL0 + +{LEG_PERF_CTL1=0xc0010001;performance event select (1) + EventSelect:8 + UnitMask:8 + OsUserMode:2 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + HostGuestOnly:2 + :22 +} # alias of PERF_CTL1 + +{LEG_PERF_CTL2=0xc0010002;performance event select (2) + EventSelect:8 + UnitMask:8 + OsUserMode:2 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + HostGuestOnly:2 + :22 +} # alias of PERF_CTL2 + +{LEG_PERF_CTL3=0xc0010003;performance event select (3) + EventSelect:8 + UnitMask:8 + OsUserMode:2 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + HostGuestOnly:2 + :22 +} # alias of PERF_CTL3 + +{LEG_PERF_CTR0=0xc0010004;performance event counter (0) + CTR:48 + :16 +} # alias of PERF_CTR0 + +{LEG_PERF_CTR1=0xc0010005;performance event counter (1) + CTR:48 + :16 +} # alias of PERF_CTR1 + +{LEG_PERF_CTR2=0xc0010006;performance event counter (2) + CTR:48 + :16 +} # alias of PERF_CTR2 + +{LEG_PERF_CTR3=0xc0010007;performance event counter (3) + CTR:48 + :16 +} # alias of PERF_CTR3 + +{SYS_CFG=0xc0010010;system configuration (sharedC) + :16 + ChxToDirtyDis:1 + :1 + MtrrFixDramEn:1 + MtrrFixDramModeEn:1 + MtrrVarDramEn:1 + MtrrTom2En:1 + Tom2ForceMemTypeWB:1 + :41 +} + +{HWCR=0xc0010015;hardware configuration + SmmLock:1 + :2 + TlbCacheDis:1 + INVDWBINVD:1 + :3 + IgnneEm:1 + MonMwaitDis:1 + MonMwaitUserEn:1 + :1 + HltXSpCycEn:1 + SmiSpCycDis:1 + RsmSpCycDis:1 + :2 + Wrap32Dis:1 + McStatusWrEn:1 + :1 + IoCfgGpFault:1 + :2 + ForceRdWrSzPrb:1 + TscFreqSel:1 + CpbDis:1 + EffFreqCntMwait:1 + :37 +} + +{IORR_BASE0=0xc0010016;base of variable I/O range (0) (sharedC) + :3 + WrMem:1 + RdMem:1 + :7 + PhyBase:36 + :16 +} + +{IORR_MASK0=0xc0010017;mask of variable I/O range (0) (sharedC) + :11 + Valid:1 + PhyMask:36 + :16 +} + +{IORR_BASE1=0xc0010018;base of variable I/O range (1) (sharedC) + :3 + WrMem:1 + RdMem:1 + :7 + PhyBase:36 + :16 +} + +{IORR_MASK1=0xc0010019;mask of variable I/O range (1) (sharedC) + :11 + Valid:1 + PhyMask:36 + :16 +} + +{TOP_MEM=0xc001001a;top of memory address (sharedC) + :23 + TOM:25 + :16 +} + +{TOM2=0xc001001d;second top of memory address (sharedC) + :23 + TOM2:25 + :16 +} + +{NB_CFG=0xc001001f;northbridge configuration + :9 + DisRefUseFreeBuf:1 + DisXdsBypass:1 + :20 + DisCohLdtCfg:1 + :4 + DisDatMsk:1 + :8 + DisUsSysMgtReqToNcHt:1 + EnableCf8ExtCfg:1 + :3 + DisOrderRdRsp:1 + :3 + InitApicIdCpuIdLo:1 + :9 +} + +{MCEredirection=0xc0010022;MCE redirection + RedirVector:8 + RedirVecEn:1 + RedirSmiEn:1 + :54 +} + +{ProcessorNameString0=0xc0010030;processor name string (0) (sharedNC) + CpuNameString:64 +} + +{ProcessorNameString1=0xc0010031;processor name string (1) (sharedNC) + CpuNameString:64 +} + +{ProcessorNameString2=0xc0010032;processor name string (2) (sharedNC) + CpuNameString:64 +} + +{ProcessorNameString3=0xc0010033;processor name string (3) (sharedNC) + CpuNameString:64 +} + +{ProcessorNameString4=0xc0010034;processor name string (4) (sharedNC) + CpuNameString:64 +} + +{ProcessorNameString5=0xc0010035;processor name string (5) (sharedNC) + CpuNameString:64 +} + +{HTC=0xc001003e;hardware thermal control + HtcEn:1 + :3 + HtcAct:1 + HtcActSts:1 + PslApicHiEn:1 + PslApicLoEn:1 + :8 + HtcTmpLmt:7 + HtcSlewSel:1 + HtcHystLmt:4 + HtcPstateLimit:3 + :33 +} + +{MC0_CTL_MASK=0xc0010044;load store MC control mask + TagP:1 + TLBP:1 + DatP:1 + LQP:1 + SQP:1 + SCBP:1 + LineFillPoison:1 + SRDE:1 + IntErrType2:1 + :55 +} + +{MC1_CTL_MASK=0xc0010045;instruction fetch MC control mask (sharedC) + :2 + IDP:1 + IMTP:1 + ISTP:1 + L2TP:1 + L1TP:1 + LineFillPoison:1 + :1 + SRDE:1 + :2 + PFBP:1 + PQP:1 + :1 + BSRP:1 + DEPRP:1 + DEUOPQP:1 + DEIBP:1 + DPDBE:1 + DFIFOE:1 + L2TLBM:1 + L1TLBM:1 + IVP:1 + :40 +} + +{MC2_CTL_MASK=0xc0010046;bus unit MC control mask (sharedC) + L2TagMultiHit:1 + VbData:1 + WcbData:1 + WccData:1 + WccAddr:1 + PrqData:1 + PrqAddr:1 + FillData:1 + PrbAddr:1 + XabAddr:1 + L2Prefetch:1 + L2TlbData:1 + L2Tag:1 + RdData:1 + L2TlbPoison:1 + :49 +} + +{MC3_CTL_MASK=0xc0010047;reserved + :64 +} + +{MC4_CTL_MASK=0xc0010048;northbridge MC control mask + CECCEn:1 + UECCEn:1 + CrcErrEn:3 + SyncPktEn:3 + MstrAbrtEn:1 + TgtAbrtEn:1 + GartTblWkEn:1 + AtomicRMWEn:1 + WDTRptEn:1 + :1 + L3ArrayCorEn:1 + L3ArrayUCEn:1 + ProtEn:1 + HtDataEn:1 + DramParEn:1 + RtryHtEn:4 + CrcErrEn:1 + SyncPktEn:1 + McaUsPwDatErrEn:1 + NbArrayParEn:1 + TblWlkDatErrEn:1 + :3 + McaCpuDatErrEn:1 + :32 +} + +{MC5_CTL_MASK=0xc0010049;execution unit MC control mask + :1 + PICWAK:1 + PLDAG:1 + PLDEX:1 + IDF:1 + RETDISP:1 + MAP:1 + EX0PRF:1 + EX1PRF:1 + AG0PRF:1 + AG1PRF:1 + FRF:1 + DE:1 + :51 +} + +{MC6_CTL_MASK=0xc001004a;floating point unit MC control mask (sharedC) + PRF:1 + FreeList:1 + Sched:1 + :1 + RetireQ:1 + SRF:1 + :58 +} + +{SMI_ON_IO_TRAP_0=0xc0010050;IO trap address (0) (sharedNC) + SmiAddr:32 + SmiMask:24 + :5 + ConfigSmi:1 + SmiOnWrEn:1 + SmiOnRdEn:1 +} + +{SMI_ON_IO_TRAP_1=0xc0010051;IO trap address (1) (sharedNC) + SmiAddr:32 + SmiMask:24 + :5 + ConfigSmi:1 + SmiOnWrEn:1 + SmiOnRdEn:1 +} + +{SMI_ON_IO_TRAP_2=0xc0010052;IO trap address (2) (sharedNC) + SmiAddr:32 + SmiMask:24 + :5 + ConfigSmi:1 + SmiOnWrEn:1 + SmiOnRdEn:1 +} + +{SMI_ON_IO_TRAP_3=0xc0010053;IO trap address (3) (sharedNC) + SmiAddr:32 + SmiMask:24 + :5 + ConfigSmi:1 + SmiOnWrEn:1 + SmiOnRdEn:1 +} + +{SMI_ON_IO_TRAP_CTL_STS=0xc0010054;IO trap control (sharedNC) + :1 + SmiEn_0:1 + :1 + SmiEn_1:1 + :1 + SmiEn_2:1 + :1 + SmiEn_3:1 + :7 + IoTrapEn:1 + :48 +} + +{IntPendingMessage=0xc0010055;interrupt pending (sharedNC) + IOMsgAddr:16 + IOMsgData:8 + IntrPndMsgDis:1 + IntrPndMsg:1 + IORd:1 + :2 + BmStsClrOnHaltEn:1 + :34 +} + +{SmiTriggerIoCycle=0xc0010056;SMI trigger IO cycle + IoPortAddress:16 + IoData:8 + :1 + IoCycleEn:1 + IoRd:1 + :37 +} + +{MmioConfigBase=0xc0010058;MMIO configuration base address + Enable:1 + :1 + SegBusRange:4;0=1;1=2;2=4;3=8;4=16;5=32;6=64;7=128;8=256 + :14 + MmiocCfgBaseAddr:28 + :16 +} + +{BistResults=0xc0010060;BIST results + :64 +} + +{PstateCurrentLimit=0xc0010061;P-state current limit (sharedC) + CurPstateLimit:3 + :1 + PstateMaxVal:3 + :57 +} + +{PstateControl=0xc0010062;P-state control + PstateCmd:3 + :61 +} + +{PstateStatus=0xc0010063;P-state status (sharedC) + CurPstate:3 + :61 +} + +{Pstate0=0xc0010064;P-state 0 (sharedC) + CpuFid:6 + CpuDid:3 + CpuVid:7 + :6 + NbPstate:1 + :9 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate1=0xc0010065;P-state 1 (sharedC) + CpuFid:6 + CpuDid:3 + CpuVid:7 + :6 + NbPstate:1 + :9 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate2=0xc0010066;P-state 2 (sharedC) + CpuFid:6 + CpuDid:3 + CpuVid:7 + :6 + NbPstate:1 + :9 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate3=0xc0010067;P-state 3 (sharedC) + CpuFid:6 + CpuDid:3 + CpuVid:7 + :6 + NbPstate:1 + :9 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate4=0xc0010068;P-state 4 (sharedC) + CpuFid:6 + CpuDid:3 + CpuVid:7 + :6 + NbPstate:1 + :9 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate5=0xc0010069;P-state 5 (sharedC) + CpuFid:6 + CpuDid:3 + CpuVid:7 + :6 + NbPstate:1 + :9 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate6=0xc001006a;P-state 6 (sharedC) + CpuFid:6 + CpuDid:3 + CpuVid:7 + :6 + NbPstate:1 + :9 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate7=0xc001006b;P-state 7 (sharedC) + CpuFid:6 + CpuDid:3 + CpuVid:7 + :6 + NbPstate:1 + :9 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{COFVIDcontrol=0xc0010070;COFVID control + CpuFid:6 + CpuDid:3 + CpuVid:7 + PstateId:3 + :3 + NbPstate:1 + :1 + NbVid:8 + :32 +} + +{COFVIDstatus=0xc0010071;COFVID status + CurCpuFid:6 + CurCpuDid:3 + CurCpuVid:7 + CurPstate:3 + :4 + NbPstateDis:1 + :1 + CurNbVid:7 + StartupPstate:3 + MaxVid:7 + MinVid:7 + MaxCpuCof:6 + :1 + CurPstateLimit:3 + MaxNbCof:5 +} + +{CstateAddress=0xc0010073;C-state address + CstateAddr:16 + :48 +} + +{SMM_BASE=0xc0010111;SMM base address + SMM_BASE:32 + :32 +} + +{SMMAddr=0xc0010112;SMM TSeg base address + :17 + TSegBase:31 + :16 +} + +{SMMMask=0xc0010113;SMM Tseg mask + AValid:1 + TValid:1 + AClose:1 + TClose:1 + AMTypeIoWc:1 + TMTypeIoWc:1 + :2 + AMTypeDram:3 + :1 + TMTypeDram:3 + :2 + TSegMask:31 + :16 +} + +{VM_CR=0xc0010114;virtual machine control + dpd:1 + InterceptInit:1 + DisA20m:1 + Lock:1 + SvmeDisable:1 + :59 +} + +{IGNNE=0xc0010115;IGNNE + IGNNE:1 + :63 +} + +{VM_HSAVE_PA=0xc0010117;virtual machine host save physical address + :12 + VM_HSAVE_PA:36 + :16 +} + +{SMIstatus=0xc001011a;local SMI status + IoTrapSts:4 + :4 + MceRedirSts:1 + :1 + IntPendSmiSts:1 + :5 + SmiSrcLvtLcy:1 + SmiSrcLvtExt:1 + SmiSrcThrCntDram:1 + SmiSrcThrCntHt:1 + SmiSrcThrCntL3:1 + :1 + SmiSrcOnLineSpare:1 + :41 +} + +{OSVW_ID_Length=0xc0010140;OS visible work-around + OSVW_ID_Length:16 + :48 +} + +{OsvwStatus=0xc0010141;OS visible work-around status bits + OsvwStatusBits:64 +} + +{PERF_CTL0=0xc0010200;performance event select (0) + EventSelect:8 + UnitMask:8 + OsUserMode:2 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + HostGuestOnly:2 + :22 +} + +{PERF_CTR0=0xc0010201;performance event counter (0) + CTR:48 + :16 +} + +{PERF_CTL1=0xc0010202;performance event select (1) + EventSelect:8 + UnitMask:8 + OsUserMode:2 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + HostGuestOnly:2 + :22 +} + +{PERF_CTR1=0xc0010203;performance event counter (1) + CTR:48 + :16 +} + +{PERF_CTL2=0xc0010204;performance event select (2) + EventSelect:8 + UnitMask:8 + OsUserMode:2 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + HostGuestOnly:2 + :22 +} + +{PERF_CTR2=0xc0010205;performance event counter (2) + CTR:48 + :16 +} + +{PERF_CTL3=0xc0010206;performance event select (3) + EventSelect:8 + UnitMask:8 + OsUserMode:2 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + HostGuestOnly:2 + :22 +} + +{PERF_CTR3=0xc0010207;performance event counter (3) + CTR:48 + :16 +} + +{PERF_CTL4=0xc0010208;performance event select (4) + EventSelect:8 + UnitMask:8 + OsUserMode:2 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + HostGuestOnly:2 + :22 +} + +{PERF_CTR4=0xc0010209;performance event counter (4) + CTR:48 + :16 +} + +{PERF_CTL5=0xc001020a;performance event select (5) + EventSelect:8 + UnitMask:8 + OsUserMode:2 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + HostGuestOnly:2 + :22 +} + +{PERF_CTR5=0xc001020b;performance event counter (5) + CTR:48 + :16 +} + +{NB_PERF_CTL0=0xc0010240;northbridge performance event select (0) + EventSelect:8 + UnitMask:8 + :4 + Int:1 + :1 + En:1 + :9 + EventSelect:4 + :28 +} + +{NB_PERF_CTR0=0xc0010241;northbridge performance event counter (0) + CTR:48 + :16 +} + +{NB_PERF_CTL1=0xc0010242;northbridge performance event select (1) + EventSelect:8 + UnitMask:8 + :4 + Int:1 + :1 + En:1 + :9 + EventSelect:4 + :28 +} + +{NB_PERF_CTR1=0xc0010243;northbridge performance event counter (1) + CTR:48 + :16 +} + +{NB_PERF_CTL2=0xc0010244;northbridge performance event select (2) + EventSelect:8 + UnitMask:8 + :4 + Int:1 + :1 + En:1 + :9 + EventSelect:4 + :28 +} + +{NB_PERF_CTR2=0xc0010245;northbridge performance event counter (2) + CTR:48 + :16 +} + +{NB_PERF_CTL3=0xc0010246;northbridge performance event select (3) + EventSelect:8 + UnitMask:8 + :4 + Int:1 + :1 + En:1 + :9 + EventSelect:4 + :28 +} + +{NB_PERF_CTR3=0xc0010247;northbridge performance event counter (3) + CTR:48 + :16 +} + +{CPUIDPmFeatures=0xc0011003;thermal and power management CPUID features + FeaturesEcx:32 + :32 +} + +{CPUIDFeatures=0xc0011004;CPUID features + FeaturesEdx:32 + FeaturesEcx:32 +} + +{CPUIDExtFeatures=0xc0011005;extended CPUID features + ExtFeaturesEdx:32 + ExtFeaturesEcx:32 +} + +{LS_CFG=0xc0011020;load store configuration + :28 + DIS_SS:1 + :35 +} + +{IC_CFG=0xc0011021;instruction cache configuration (sharedC) + :9 + DIS_SPEC_TLB_RLD:1 + :54 +} + +{DC_CFG=0xc0011022;data cache configuration + :4 + DIS_SPEC_TLB_RLD:1 + :8 + DIS_HW_PF:1 + :50 +} + +{CU_CFG=0xc0011023;combined unit configuration (sharedC) + :10 + DcacheAgressivePriority:1 + :8 + L2FirstLockedWay:4 + L2WayLock:1 + :40 +} + +{FP_CFG=0xc0011028;floating point configuration (sharedC) + :16 + DiDtMode:1 + :1 + DiDtCfg0:5 + :2 + DiDtCfg2:2 + DiDtCfg1:8 + :29 +} + +{DE_CFG=0xc0011029;decode configuration (sharedC) + :10 + ResyncPredSingleDispDis:1 + :53 +} + +{CU_CFG2=0xc001102A;combined unit configuration 2 (sharedC) + :6 + ThrottleNbInterface:2 + :2 + VicResyncChkEn:1 + :25 + ThrottleNbInterface:2 + :4 + ProbeFilterSupEn:1 + :7 + RdMmExtCfgQwEn:1 + :13 +} + +{CU_CFG3=0xc001102B;combined unit configuration 3 (sharedC) + :42 + PwcDisableWalkerSharing:1 + :6 + CombineCr0Cd:1 + AsidIncrScaleFactor:1 + AsidDecrScaleFactor:2 + :11 +} + +{EX_CFG=0xc001102C;execution unit configuration + :64 +} + +{IbsFetchCtl=0xc0011030;IBS fetch control + IbsFetchMaxCnt:16 + IbsFetchCnt:16 + IbsFetchLat:16 + IbsFetchEn:1 + IbsFetchVal:1 + IbsFetchComp:1 + IbsIcMiss:1 + IbsPhyAddrValid:1 + IbsL1TlbPgSz:2 + IbsL1TlbMiss:1 + IbsL2TlbMiss:1 + IbsRandEn:1 + :6 +} + +{IbsFetchLinAd=0xc0011031;IBS fetch linear address + IbsFetchLinAd:64 +} + +{IbsFetchPhysAd=0xc0011032;IBS fetch physical address + IbsFetchPhysAd:64 +} + +{IbsOpCtl=0xc0011033;IBS execution control + IbsOpMaxCnt:16 + :1 + IbsOpEn:1 + IbsOpVal:1 + IbsOpCntCtl:1 + IbsOpMaxCnt:7 + :5 + IbsOpCurCnt:27 + :5 +} + +{IbsOpRip=0xc0011034;IBS Op logical address + IbsOpRip:64 +} + +{IbsOpData=0xc0011035;IBS Op data + IbsCompToRetCtr:16 + IbsTagToRetCtr:16 + IbsOpBrnResync:1 + IbsOpMispReturn:1 + IbsOpReturn:1 + IbsOpBrnTaken:1 + IbsOpBrnMisp:1 + IbsOpBrnRet:1 + IbsRipInvalid:1 + :25 +} + +{IbsOpData2=0xc0011036;IBS Op data 2 + NbIbsReqSrc:3 + :1 + NbIbsReqDstNode:1 + NbIbsReqCacheHitSt:1 + :58 +} + +{IbsOpData3=0xc0011037;IBS Op data 3 + IbsLdOp:1 + IbsStOp:1 + IbsDcL1tlbMiss:1 + IbsDcL2tlbMiss:1 + IbsDcL1tlbHit2M:1 + IbsDcL1tlbHit1G:1 + IbsDcL2tlbHit2M:1 + IbsDcMiss:1 + IbsDcMisAcc:1 + IbsDcLdBnkCon:1 + :1 + IbsDcStToLdFwd:1 + IbsDcStToLdCan:1 + IbsDcWcMemAcc:1 + IbsDcUcMemAcc:1 + IbsDcLockedOp:1 + IbsDcMabHit:1 + IbsDcLinAddrValid:1 + IbsDcPhyAddrValid:1 + IbsDcL2tlbHit1G:1 + :12 + IbsDcMissLat:16 + :16 +} + +{IbsDcLinAd=0xc0011038;IBS DC linear address + IbsDcLinAd:64 +} + +{IbsDcPhysAd=0xc0011039;IBS DC physical address + IbsDcPhysAd:64 +} + +{IbsControl=0xc001103a;IBS control + LvtOffset:4 + :4 + LvtOffsetVal:1 + :55 +} + +{IbsBranchTargetAddress=0xc001103b;IBS branch target address + IbsBrTarget:64 +} + +### Local Variables: ### +### mode:shell-script ### +### End: ###

@@ -91,26 +91,51 @@ cpuid(c->number, 0x80000001, &eax, &ebx, &ecx, &edx); pkg_id = (ebx >> 28) & 0xf; - switch (pkg_id) { - case 0: - c->connector = CONN_SOCKET_F_R2; - break; - case 1: - c->connector = CONN_SOCKET_AM3; - break; - case 2: - c->connector = CONN_SOCKET_S1G3; - break; - case 3: - c->connector = CONN_SOCKET_G34; - break; - case 4: - c->connector = CONN_SOCKET_ASB2; - break; - case 5: - c->connector = CONN_SOCKET_C32; - default: - c->connector = 0; + if ((family(c) == 0x10) || (family(c) == 0x11) || (family(c) == 0x15)) { + switch (pkg_id) { + case 0: + c->connector = CONN_SOCKET_F_R2; + break; + case 1: + c->connector = CONN_SOCKET_AM3; + break; + case 2: + c->connector = CONN_SOCKET_S1G3; + break; + case 3: + c->connector = CONN_SOCKET_G34; + break; + case 4: + c->connector = CONN_SOCKET_ASB2; + break; + case 5: + c->connector = CONN_SOCKET_C32; + break; + default: + c->connector = 0; + } + } else if(family(c) == 0x12) { + switch (pkg_id) { + case 0: + c->connector = CONN_SOCKET_FP1; + break; + case 1: + c->connector = CONN_SOCKET_FS1; + break; + case 2: + c->connector = CONN_SOCKET_FM1; + break; + default: + c->connector = 0; + } + } else if (family(c) == 0x14) { + switch (pkg_id) { + case 0: + c->connector = CONN_SOCKET_FT1; + break; + default: + c->connector = 0; + } } } @@ -143,6 +168,49 @@ set_connector(c); } +static void set_fam12h_revinfo(int id, struct cpudata *c) +{ + const char *p; + + p = get_fam12h_revision_name(id); + if(p) + snprintf(c->name, CPU_NAME_LEN, + "AMD A/E2-Series Processor (%s)", p); + else + snprintf(c->name, CPU_NAME_LEN, "Unknown CPU"); + + set_connector(c); +} + +static void set_fam14h_revinfo(int id, struct cpudata *c) +{ + const char *p; + + p = get_fam14h_revision_name(id); + if (p) + snprintf(c->name, CPU_NAME_LEN, + "AMD C/E/G-Series Processor (%s)", p); + else + snprintf(c->name, CPU_NAME_LEN, "Unknown CPU"); + + + set_connector(c); +} + +static void set_fam15h_revinfo(int id, struct cpudata *c) +{ + const char *p; + + p = get_fam15h_revision_name(id); + if (p) + snprintf(c->name, CPU_NAME_LEN, + "AMD FX Series Processor (%s)", p); + else + snprintf(c->name, CPU_NAME_LEN, "Unknown CPU"); + set_connector(c); +} + + static void do_assoc(unsigned long assoc) { switch (assoc & 0xff) { @@ -294,12 +362,12 @@ printf("\n\t"); printf("lines per tag=%u\t", (ecx >> 8) & 0x0f); printf("line size=%u bytes.\n", ecx & 0xff); - if (family(cpu) == 0x10) { + if ((family(cpu) == 0x10) || (family(cpu) == 0x15)) { printf("L3 (shared) cache:\n\t"); if (!(edx >> 18)) printf("none/disabled\n"); else { - /* family 0x10 has shared L3 cache */ + /* shared L3 cache */ printf("Size: %uKb\t", (edx >> 18) * 512); do_l2assoc((edx >> 12) & 0x0f); @@ -369,8 +437,8 @@ if (cpu->cpuid_level < 1) return; + cpuid(cpu->number, 0x00000001, &eax, &ebx, &ecx, &edx); if (cpu->family == 0xf) { - cpuid(cpu->number, 0x00000001, &eax, &ebx, &ecx, &edx); cpu->emodel = (eax >> 16) & 0xf; cpu->efamily= (eax >> 20) & 0xff; } else { @@ -378,14 +446,32 @@ cpu->efamily = 0; } - if (family(cpu) == 0xf) { - set_k8_revinfo(eax, cpu); - return; - } else if (family(cpu) == 0x10) { - set_fam10h_revinfo(eax, cpu); - return; - } else if (family(cpu) == 0x11) { - set_fam11h_revinfo(eax, cpu); + if (family(cpu) >= 0xf) { + switch family(cpu) { + case 0xf: + set_k8_revinfo(eax, cpu); + break; + case 0x10: + set_fam10h_revinfo(eax, cpu); + break; + case 0x11: + set_fam11h_revinfo(eax, cpu); + break; + case 0x12: + set_fam12h_revinfo(eax, cpu); + break; + case 0x14: + set_fam14h_revinfo(eax, cpu); + break; + case 0x15: + set_fam15h_revinfo(eax, cpu); + break; + default: + printf("Unknown CPU family: 0x%x\n", + family(cpu)); + break; + } + return; }

@@ -132,6 +132,33 @@ return t; } +static int get_main_pll_fid(void) +{ + struct pci_filter filter_nb_misc = { -1, -1, -1, -1, 0x1022, 0x1703}; + struct pci_access *pacc; + struct pci_dev *z = NULL; + u8 val; + + pacc = pci_alloc(); + pci_init(pacc); + pci_scan_bus(pacc); + + for (z=pacc->devices; z; z=z->next) { + if (pci_filter_match(&filter_nb_misc, z)) + break; + } + + val = 0; + if (z) { + val = pci_read_byte(z, 0xd4); + val &= 0x3f; + } + + pci_cleanup(pacc); + + return val; +} + static int get_cof(int family, union msr_pstate pstate) { int t; @@ -141,16 +168,57 @@ t = 0x10; fid = pstate.bits.fid; - if (family == 0x11) + if ((family == 0x10) || (family == 0x15)) + goto out; + + if (family == 0x11) { t = 0x8; + goto out; + } + if (family == 0x12) { + int f, d; + t = 0x10; + fid = (pstate.val >> 4) & 0x1f; + + switch (did) { + case 0: + goto out; + case 2: + did = 1; goto out; + case 4: + did = 2; goto out; + case 6: + did = 3; goto out; + case 8: + did = 4; goto out; + case 1: + f = 2; d = 3; break; + case 3: + f = 1; d = 3; break; + case 5: + f = 1; d = 6; break; + case 7: + f = 1; d = 12; break; + default: + printf("Invalid divisor ID: %d\n", did); + return 0; + } + return (100 * (fid + t) * f / d); + } + if (family == 0x14) { + fid = get_main_pll_fid(); //from PCI + return (((fid + 0x10) *100) * 4 / did); + } + + out: return ((100 * (fid + t)) >> did); } static int get_num_boost_states(void) { struct pci_filter filter_nb_link = { -1, -1, -1, -1, 0x1022, 0}; - int dev_ids[3] = {0x1204}; + int dev_ids[3] = {0x1204, 0x1604, 0x1704}; struct pci_access *pacc; struct pci_dev *z = NULL; u8 val; @@ -176,7 +244,7 @@ printf("Boosting enabled\n"); else printf("Boosting disabled\n"); - val = (val >> 2) & 1; + val = (val >> 2) & 7; printf("Number of boost states: %d\n", val); } @@ -218,13 +286,15 @@ i); return; } - if (i < boost_states) + if (i < boost_states) { printf("Pstate-Pb%d: %dMHz (boost state)\n", i, get_cof(fam, pstate)); - else + } else if (pstate.bits.en) { + /* show information only if pstate is enabled */ printf("Pstate-P%d: %dMHz%s\n", i - boost_states, get_cof(fam, pstate), (i == pscur) ? " (current)" : ""); + } } printf("\n"); }

@@ -147,4 +147,20 @@ }; get_name(fam11h_revision, int, fam11h_revisions); +struct id_string fam12h_revisions[] = { + {0x0300f10, "LN1-B0"}, +}; +get_name(fam12h_revision, int, fam12h_revisions); + +struct id_string fam14h_revisions[] = { + {0x00500f10, "ON-B0"}, +}; +get_name(fam14h_revision, int, fam14h_revisions); + +struct id_string fam15h_revisions[] = { + + {0x00600f12, "OR-B2"}, +}; +get_name(fam15h_revision, int, fam15h_revisions); + #endif /* _amd_revision_h_ */

@@ -289,10 +289,18 @@ add_to_cpuname("Core i7 (Nehalem) [Gulftown/Westmere-EP]"); break; + case 0x2d: + add_to_cpuname("Core i7 (Sandybridge) [Romely-EP]"); + break; + case 0x2e: add_to_cpuname("Core i7 (Nehalem) [Beckton]"); break; + case 0x2f: + add_to_cpuname("Core i7 (Nehalem-EX) [Westmere] [Xeon E7]"); + break; + default: add_to_cpuname("Unknown model. "); }

@@ -131,8 +131,8 @@ if (show_eblcr) { if (cpu->family == 6 && cpu->model >= 3) { unsigned long long eblcr; - read_msr(cpu->number, 0x2A, &eblcr); - interpret_eblcr(eblcr); + if (read_msr(cpu->number, 0x2A, &eblcr) == 1) + interpret_eblcr(eblcr); } }

@@ -1,4 +1,4 @@ -VERSION=1.29 +VERSION=1.30 CFLAGS = -g -O2 -Werror -Wall -Wshadow -Wextra -Wmissing-declarations -Wdeclaration-after-statement -Wredundant-decls LDFLAGS = -Wl,-z,relro,-z,now @@ -9,7 +9,8 @@ all: x86info test lsmsr -LSMSR_TMP_HEADERS=AMD/k8.h AMD/fam10h.h AMD/fam11h.h generic_msr.h +LSMSR_TMP_HEADERS=AMD/k8.h AMD/fam10h.h AMD/fam11h.h AMD/fam12h.h \ + AMD/fam14h.h AMD/fam15h.h generic_msr.h %.h: %.regs scripts/createheader.py python scripts/createheader.py $< `basename $< .regs` >$@ @@ -23,6 +24,8 @@ lsmsr.c: $(LSMSR_TMP_HEADERS) +lsmsr.o: $(LSMSR_TMP_HEADERS) + lsmsr: $(LSMSR_TMP_HEADERS) $(LSMSR_OBJS) $(CC) $(CFLAGS) $(LDFLAGS) -o lsmsr $(LSMSR_OBJS)

@@ -1,4 +1,4 @@ -x86info v1.29 http://www.codemonkey.org.uk/projects/x86info +x86info v1.30 http://www.codemonkey.org.uk/projects/x86info Dave Jones <davej@redhat.com> Somewhere in the mists of time, there was a program by Phil Karn (KA9Q)

@@ -1,5 +1,6 @@ higher priority stuff --------------------- +- handle error better in mptable. Propagate values up. - feature flag handling code could use more cleanup. - Would be nice to have something similar to the kernels CPU_HAS macros too. - Make intel cache sizing use cpuid(4) where present.

@@ -39,6 +39,10 @@ {CONN_SOCKET_G34, "Socket G34"}, {CONN_SOCKET_ASB2, "Socket ASB2"}, {CONN_SOCKET_C32, "Socket C32"}, + {CONN_SOCKET_FP1, "Socket FP1"}, + {CONN_SOCKET_FS1, "Socket FS1"}, + {CONN_SOCKET_FM1, "Socket FM1"}, + {CONN_SOCKET_FT1, "Socket FT1"}, /* Intel specific sockets */ {CONN_SOCKET_57B, "Socket 5/7 (320 Pin PGA)"}, {CONN_MOBILE_7, "Mobile Module (320 Lead TCP)"},

@@ -372,8 +372,8 @@ "3dnowPref", "osvw", "ibs", "xop", "skinit", "wdt", NULL, "lwp", "fma4", NULL, NULL, "NodeId", - NULL, "tbm", "TopoExt", NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL + NULL, "tbm", "TopoExt", "PerfCtrExtCore", + "PerfCtrExtNB", NULL, NULL, NULL, NULL, NULL, NULL, NULL }; const char *centaur_cap_extended_ecx_flags[] = { @@ -469,7 +469,7 @@ died = sigsetjmp(out, 1); if (!died) - asm volatile("nopl 0(%eax)"); + asm volatile(".byte 0x0f,0x1f,0x00 /* nopl 0(%eax) */"); printf("Long NOPs supported: %s\n", died ? "no" : "yes"); }

@@ -29,6 +29,9 @@ #include "AMD/k8.h" #include "AMD/fam10h.h" #include "AMD/fam11h.h" +#include "AMD/fam12h.h" +#include "AMD/fam14h.h" +#include "AMD/fam15h.h" #include "generic_msr.h" /* Todos: @@ -284,6 +287,15 @@ case 0x11: g.msr_table = fam11h_spec; break; + case 0x12: + g.msr_table = fam12h_spec; + break; + case 0x14: + g.msr_table = fam14h_spec; + break; + case 0x15: + g.msr_table = fam15h_spec; + break; default: g.msr_table = generic_msr_spec; } @@ -304,6 +316,8 @@ return 0; } +struct reg_spec unknown_msr = {0, "unknown", "(at your own risk)", NULL, NULL}; + #define OPT_MAX 32 int main(int argc, char *argv[]) { @@ -360,7 +374,12 @@ } } - if((optind > -1) && argv[optind]) { + if (argc < 2) { + usage(); + goto out; + } + + if ((optind > -1) && argv[optind]) { if ((argc - optind) != 1) usage(); if (strlen(argv[optind]) >= OPT_MAX) { @@ -391,8 +410,10 @@ reg = get_reg_spec(g.reg, g.msr_table); if (!reg) { fflush(stdout); - fprintf(stderr, "error: unknown MSR %x\n", g.reg); - goto out; + fprintf(stderr, "warning: unknown MSR %x\n", g.reg); + g.verbosity = 0; + unknown_msr.address = g.reg; + reg = &unknown_msr; } if (_show_msr(reg)) goto out;

@@ -140,12 +140,13 @@ } } -static void readEntry(void* entry, int size) +static int readEntry(void* entry, int size) { if (read(pfd, entry, size) != size) { perror("readEntry"); - exit(EXIT_FAILURE); + return -1; } + return 0; } static int readType(void) @@ -171,7 +172,10 @@ int t, family, model; /* read it into local memory */ - readEntry(&entry, sizeof(entry)); + if (readEntry(&entry, sizeof(entry)) < 0) { + printf("Error reading processor entry\n"); + exit(EXIT_FAILURE); + } /* count it */ ++ncpu; @@ -216,7 +220,10 @@ /* read in cth structure */ seekEntry(paddr); - readEntry(&cth, sizeof(cth)); + if(readEntry(&cth, sizeof(cth))) { + printf("error reading MP Config table header structure\n"); + exit(EXIT_FAILURE); + } totalSize = cth.base_table_length - sizeof(struct MPCTH); count = cth.entry_count; @@ -260,11 +267,23 @@ /* search Extended Bios Data Area, if present */ seekEntry((vm_offset_t)EBDA_POINTER); - readEntry(&segment, 2); + if (readEntry(&segment, 2)) { + printf("error reading EBDA pointer\n"); + exit(EXIT_FAILURE); + } + if (debug) + printf("\nEBDA points to: %x\n", segment); + if (segment) { /* search EBDA */ target = (vm_offset_t)segment << 4; seekEntry(target); - readEntry(buffer, ONE_KBYTE); + if (debug) + printf("EBDA segment ptr: %lx\n", target); + if (readEntry(buffer, ONE_KBYTE)) { + printf("error reading 1K from %p\n", (void *)target); + exit(EXIT_FAILURE); + } + for (x = 0; x < ONE_KBYTE / 4; NEXT(x)) { if (!strncmp((char *)&buffer[x], MP_SIG, 4)) { @@ -276,11 +295,19 @@ /* read CMOS for real top of mem */ seekEntry((vm_offset_t)TOPOFMEM_POINTER); - readEntry(&segment, 2); + if (readEntry(&segment, 2)) { + printf("error reading CMOS for real top of mem (%p)\n", (void *) TOPOFMEM_POINTER); + exit(EXIT_FAILURE); + } + --segment; /* less ONE_KBYTE */ target = segment * 1024; seekEntry(target); - readEntry(buffer, ONE_KBYTE); + if (readEntry(buffer, ONE_KBYTE)) { + printf("error reading 1KB from %p\n", (void *)target); + exit(EXIT_FAILURE); + } + for (x = 0; x < ONE_KBYTE/4; NEXT(x)) { if (!strncmp((char *)&buffer[x], MP_SIG, 4)) { @@ -293,7 +320,10 @@ if (target != (DEFAULT_TOPOFMEM - 1024)) { target = (DEFAULT_TOPOFMEM - 1024); seekEntry(target); - readEntry(buffer, ONE_KBYTE); + if (readEntry(buffer, ONE_KBYTE)) { + printf("error reading DEFAULT_TOPOFMEM - 1024 from %p\n", (void *) target); + exit(EXIT_FAILURE); + } for (x = 0; x < ONE_KBYTE/4; NEXT(x)) { if (!strncmp((char *)&buffer[x], MP_SIG, 4)) { @@ -305,7 +335,11 @@ /* search the BIOS */ seekEntry(BIOS_BASE); - readEntry(buffer, BIOS_SIZE); + if (readEntry(buffer, BIOS_SIZE)) { + printf("error reading BIOS_BASE from %p\n", (void *)BIOS_BASE); + exit(EXIT_FAILURE); + } + for (x = 0; x < BIOS_SIZE/4; NEXT(x)) { if (!strncmp((char *)&buffer[x], MP_SIG, 4)) { @@ -316,7 +350,11 @@ /* search the extended BIOS */ seekEntry(BIOS_BASE2); - readEntry(buffer, BIOS_SIZE); + if (readEntry(buffer, BIOS_SIZE)) { + printf("error reading BIOS_BASE2 from %p\n", (void *)BIOS_BASE2); + exit(EXIT_FAILURE); + } + for (x = 0; x < BIOS_SIZE/4; NEXT(x)) { if (!strncmp((char *)&buffer[x], MP_SIG, 4)) { @@ -328,7 +366,11 @@ /* search additional memory */ target = GROPE_AREA1; seekEntry(target); - readEntry(buffer, GROPE_SIZE); + if (readEntry(buffer, GROPE_SIZE)) { + printf("error reading GROPE_AREA1 from %p\n", (void *)target); + exit(EXIT_FAILURE); + } + for (x = 0; x < GROPE_SIZE/4; NEXT(x)) { if (!strncmp((char *)&buffer[x], MP_SIG, 4)) { @@ -339,7 +381,11 @@ target = GROPE_AREA2; seekEntry(target); - readEntry(buffer, GROPE_SIZE); + if (readEntry(buffer, GROPE_SIZE)) { + printf("error reading GROPE_AREA2 from %p\n", (void *)target); + exit(EXIT_FAILURE); + } + for (x = 0; x < GROPE_SIZE/4; NEXT(x)) { if (!strncmp((char *)&buffer[x], MP_SIG, 4)) { @@ -372,7 +418,11 @@ /* read in mpfps structure*/ seekEntry(paddr); - readEntry(&mpfps, sizeof(mpfps_t)); + if (readEntry(&mpfps, sizeof(mpfps_t))) { + printf("error reading mpfpsfrom %p\n", (void *)paddr); + exit(EXIT_FAILURE); + } + /* check whether an MP config table exists */ if (!mpfps.mpfb1) @@ -401,7 +451,11 @@ /* read in mpfps structure*/ seekEntry(paddr); - readEntry(&mpfps, sizeof(mpfps_t)); + if (readEntry(&mpfps, sizeof(mpfps_t))) { + printf("error reading mpfps from %p\n", (void *)paddr); + exit(EXIT_FAILURE); + } + /* parse an MP config table if it exists */ if (!mpfps.mpfb1)

@@ -70,10 +70,10 @@ { char cpuname[16]; unsigned char buffer[8]; - unsigned long lo, hi; + unsigned long long lo, hi; int fh; static int nodriver=0; - unsigned long *ptr = (unsigned long *) buffer; + unsigned int *ptr = (unsigned int *) buffer; if (nodriver==1) return 0; @@ -101,10 +101,9 @@ return 0; } - lo = *(ptr)++; - hi = *(ptr); - *val = hi; - *val = (*val<<32) | lo; + lo = *ptr; + hi = *(++ptr); + *val = (hi << 32) | lo; } if (close(fh) == -1) { perror("close");

@@ -39,27 +39,27 @@ progname=os.path.basename(sys.argv[0]) if len(sys.argv) < 3: - print progname + ": invalid number of argumenst" - print "\nUSAGE:" - print progname + " <input file> <struct name>" - print "\nEXAMPLE:" - print progname + " k8regs.txt k8 >k8.h" + print(progname + ": invalid number of argumenst") + print("\nUSAGE:") + print(progname + " <input file> <struct name>") + print("\nEXAMPLE:") + print(progname + " k8regs.txt k8 >k8.h") sys.exit(1) f=open(sys.argv[1]) family=sys.argv[2] -print \ +print(\ "/*\n"\ " * Licensed under the terms of the GNU GENERAL PUBLIC LICENSE version 2.\n"\ " * See file COPYING for details.\n"\ -" */\n" -print "#ifndef " + family + "_h" -print "#define " + family + "_h\n" +" */\n") +print("#ifndef " + family + "_h") +print("#define " + family + "_h\n") if (re.search("/", sys.argv[1])): - print "#include \"../msr.h\"\n" + print("#include \"../msr.h\"\n") else: - print "#include \"msr.h\"\n" + print("#include \"msr.h\"\n") struct=[] for line in f: if (re.search("^#",line)): @@ -88,8 +88,8 @@ str1 += "," + e[1] str1 += ",0);" str2 += ");" - print str1 - print str2 + print(str1) + print(str2) str3 = "_SPEC(" + reg_addr + ", " + reg_name + ", " if reg_desc != "": str3 += "\"" + reg_desc + "\", " @@ -104,10 +104,10 @@ fwidth=field[1].strip() spec.append([fname, fwidth]) -print "\nstruct reg_spec " + family + "_spec [] = {" +print("\nstruct reg_spec " + family + "_spec [] = {") for i in struct: - print "\t" + i + "," -print " {0, NULL, NULL, NULL, NULL}," -print "};\n" -print "#endif /* " + family + "_h */" + print("\t" + i + ",") +print(" {0, NULL, NULL, NULL, NULL},") +print("};\n") +print("#endif /* " + family + "_h */") f.close()

@@ -114,4 +114,6 @@ if (cpu->flags_edx & X86_FEATURE_HT && cpu->num_siblings > 1) printf(" with hyper-threading (%d threads per core)", cpu->num_siblings); + + free(sockets); }

@@ -169,7 +169,7 @@ parse_command_line(argc, argv); - printf("x86info v1.29. Dave Jones 2001-2011\n"); + printf("x86info v1.30. Dave Jones 2001-2011\n"); printf("Feedback to <davej@redhat.com>.\n\n"); if ((HaveCPUID()) == 0) {

@@ -58,6 +58,10 @@ CONN_SOCKET_G34, CONN_SOCKET_ASB2, CONN_SOCKET_C32, + CONN_SOCKET_FP1, + CONN_SOCKET_FS1, + CONN_SOCKET_FM1, + CONN_SOCKET_FT1, }; #define CPU_NAME_LEN 80

[-] [+]	Changed	x86info.changes
@@ -1,4 +1,9 @@ ------------------------------------------------------------------- +Wed Oct 3 10:34:18 UTC 2012 - cs@linux-administrator.com + +- update to release 1.30 + +------------------------------------------------------------------- Sun Apr 17 10:45:50 UTC 2011 - cs@linux-administrator.com - update to release 1.29
[-] [+]	Changed	x86info.spec ^
@@ -1,5 +1,5 @@ # -# spec file for package x86info (Version 1.29) +# spec file for package x86info (Version 1.30) # # Copyright (c) 2009 SUSE LINUX Products GmbH, Nuernberg, Germany. # @@ -22,7 +22,7 @@ Url: http://www.codemonkey.org.uk/projects/x86info/ Group: System/Monitoring AutoReqProv: on -Version: 1.29 +Version: 1.30 Release: 1 Summary: Show x86 CPU Information Source: http://www.codemonkey.org.uk/x86info/%{name}-%{version}.tar.bz2
[-] [+]	Changed	x86info-1.30.tar.bz2/.gitignore ^
@@ -3,6 +3,9 @@ x86info AMD/fam10h.h AMD/fam11h.h +AMD/fam12h.h +AMD/fam14h.h +AMD/fam15h.h AMD/k8.h generic_msr.h lsmsr
[-] [+]	Added	x86info-1.30.tar.bz2/AMD/fam12h.regs ^
@@ -0,0 +1,1693 @@ +# Author: Andreas Herrmann <andreas.herrmann3@amd.com> +# +# Copyright (C) 2008, 2009 Advanced Micro Devices, Inc. + +# This file contains information from: +# - "41131 Rev 3.00 - June 2011, BIOS and Kernel Developer's Guide (BKDG) +# for AMD Family 12h Processors" + +# See scripts/createheader.py for the general format of this register +# definitions. + +{LSMCAaddr=0x0000;load-store MCA address + ADDR:64 +} # alias of MC3_ADDR + +{LSMCAstatus=0x0001;load-store MCE status + ErrorCode:16 + ErrorCodeExt:4 + :4 + SYND:8 + :13 + UECC:1 + CECC:1 + SYND:8 + :2 + PCC:1 + ADDRV:1 + MISCV:1 + EN:1 + UC:1 + OVER:1 + VAL:1 +} # alias of MC3_STATUS + +{TSC=0x0010;time-stamp counter + TSC:64 +} + +{APIC_BASE=0x001b;APIC base address + :8 + BSC:1 + :2 + ApicEn:1 + ApicBar:28 + :24 +} + +{EBL_CR_POWERON=0x002a;cluster ID + :16 + ClusterID:2 + :46 +} + +{PATCH_LEVEL=0x008b;microcode patch level + PATCH_LEVEL:32 + :32 +} + +{MPERF=0x00e7;max performance frequency clock count + MPERF:64 +} + +{APERF=0x00e8;actual performance frequency clock count + APERF:64 +} + +{MTRRcap=0x00fe;MTRR capabilities + MtrrCapVCnt:8 + MtrrCapFix:1 + :1 + MtrrCapWc:1 + :53 +} + +{SYSENTER_CS=0x0174;SYSENTER/SYSEXIT code segment selector + SYSENTER_CS:16 + :48 +} + +{SYSENTER_ESP=0x0175;SYSENTER/SYSEXIT stack pointer + SYSENTER_ESP:32 + :32 +} + +{SYSENTER_EIP=0x0176;SYSENTER/SYSEXIT instruction pointer + SYSENTER_EIP:32 + :32 +} + +{MCG_CAP=0x0179;global MC capabilities + Count:8 + MCG_CTL_P:1 + :55 +} + +{MCG_STAT=0x017a;global MC status + RIPV:1 + EIPV:1 + MCIP:1 + :61 +} + +{MCG_CTL=0x017b;global MC control + LS:1 + IF:1 + BU:1 + FP:1 + NB:1 + FR:1 + :58 +} + +{DBG_CTL_MSR=0x01d9;debug control + LBR:1 + BTF:1 + PB0:1 + PB1:1 + PB2:1 + PB3:1 + :58 +} + +{BR_FROM=0x01db;last branch from IP + LastBranchFromIP:64 +} + +{BR_TO=0x01dc;last branch to IP + LastBranchToIP:64 +} + +{LastExceptionFromIP=0x01dd;last exception from IP + LastIntFromIP:64 +} + +{LastExceptionToIP=0x01de;last exception to IP + LastIntToIP:64 +} + +{MTRRphysBase0=0x0200;base of variable-size MTRR (0) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:28 + :24 +} + +{MTRRphysMask0=0x0201;mask of variable-size MTRR (0) + :11 + Valid:1 + PhysMask:28 + :24 +} + +{MTRRphysBase1=0x0202;base of variable-size MTRR (1) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:28 + :24 +} + +{MTRRphysMask1=0x0203;mask of variable-size MTRR (1) + :11 + Valid:1 + PhysMask:28 + :24 +} + +{MTRRphysBase2=0x0204;base of variable-size MTRR (2) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:28 + :24 +} + +{MTRRphysMask2=0x0205;mask of variable-size MTRR (2) + :11 + Valid:1 + PhysMask:28 + :24 +} + +{MTRRphysBase3=0x0206;base of variable-size MTRR (3) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:28 + :24 +} + +{MTRRphysMask3=0x0207;mask of variable-size MTRR (3) + :11 + Valid:1 + PhysMask:28 + :24 +} + +{MTRRphysBase4=0x0208;base of variable-size MTRR (4) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:28 + :24 +} + +{MTRRphysMask4=0x0209;mask of variable-size MTRR (4) + :11 + Valid:1 + PhysMask:28 + :24 +} + +{MTRRphysBase5=0x020a;base of variable-size MTRR (5) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:28 + :24 +} + +{MTRRphysMask5=0x020b;mask of variable-size MTRR (5) + :11 + Valid:1 + PhysMask:28 + :24 +} + +{MTRRphysBase6=0x020c;base of variable-size MTRR (6) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:28 + :24 +} + +{MTRRphysMask6=0x020d;mask of variable-size MTRR (6) + :11 + Valid:1 + PhysMask:28 + :24 +} + +{MTRRphysBase7=0x020e;base of variable-size MTRR (7) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:28 + :24 +} + +{MTRRphysMask7=0x020f;mask of variable-size MTRR (7) + :11 + Valid:1 + PhysMask:28 + :24 +} + +{MTRRfix64K_00000=0x0250;fixed range MTRR + 0xxxxMemType:3 + 0xxxxWrDram:1 + 0xxxxRdDram:1 + :3 + 1xxxxMemType:3 + 1xxxxWrDram:1 + 1xxxxRdDram:1 + :3 + 2xxxxMemType:3 + 2xxxxWrDram:1 + 2xxxxRdDram:1 + :3 + 3xxxxMemType:3 + 3xxxxWrDram:1 + 3xxxxRdDram:1 + :3 + 4xxxxMemType:3 + 4xxxxWrDram:1 + 4xxxxRdDram:1 + :3 + 5xxxxMemType:3 + 5xxxxWrDram:1 + 5xxxxRdDram:1 + :3 + 6xxxxMemType:3 + 6xxxxWrDram:1 + 6xxxxRdDram:1 + :3 + 7xxxxMemType:3 + 7xxxxWrDram:1 + 7xxxxRdDram:1 + :3 +} + +{MTRRfix16K_80000=0x0258;fixed range MTRR + 80xxxMemType:3 + 80xxxWrDram:1 + 80xxxRdDram:1 + :3 + 84xxxMemType:3 + 84xxxWrDram:1 + 84xxxRdDram:1 + :3 + 88xxxMemType:3 + 88xxxWrDram:1 + 88xxxRdDram:1 + :3 + 8CxxxMemType:3 + 8CxxxWrDram:1 + 8CxxxRdDram:1 + :3 + 90xxxMemType:3 + 90xxxWrDram:1 + 90xxxRdDram:1 + :3 + 94xxxMemType:3 + 94xxxWrDram:1 + 94xxxRdDram:1 + :3 + 98xxxMemType:3 + 98xxxWrDram:1 + 98xxxRdDram:1 + :3 + 9CxxxMemType:3 + 9CxxxWrDram:1 + 9CxxxRdDram:1 + :3 +} + +{MTRRfix16K_A0000=0x0259;fixed range MTRR + A0xxxMemType:3 + A0xxxWrDram:1 + A0xxxRdDram:1 + :3 + A4xxxMemType:3 + A4xxxWrDram:1 + A4xxxRdDram:1 + :3 + A8xxxMemType:3 + A8xxxWrDram:1 + A8xxxRdDram:1 + :3 + ACxxxMemType:3 + ACxxxWrDram:1 + ACxxxRdDram:1 + :3 + B0xxxMemType:3 + B0xxxWrDram:1 + B0xxxRdDram:1 + :3 + B4xxxMemType:3 + B4xxxWrDram:1 + B4xxxRdDram:1 + :3 + B8xxxMemType:3 + B8xxxWrDram:1 + B8xxxRdDram:1 + :3 + BCxxxMemType:3 + BCxxxWrDram:1 + BCxxxRdDram:1 + :3 +} + +{MTRRfix4K_C0000=0x0268;fixed range MTRR + C0xxxMemType:3 + C0xxxWrDram:1 + C0xxxRdDram:1 + :3 + C1xxxMemType:3 + C1xxxWrDram:1 + C1xxxRdDram:1 + :3 + C2xxxMemType:3 + C2xxxWrDram:1 + C2xxxRdDram:1 + :3 + C3xxxMemType:3 + C3xxxWrDram:1 + C3xxxRdDram:1 + :3 + C4xxxMemType:3 + C4xxxWrDram:1 + C4xxxRdDram:1 + :3 + C5xxxMemType:3 + C5xxxWrDram:1 + C5xxxRdDram:1 + :3 + C6xxxMemType:3 + C6xxxWrDram:1 + C6xxxRdDram:1 + :3 + C7xxxMemType:3 + C7xxxWrDram:1 + C7xxxRdDram:1 + :3 +} + +{MTRRfix4K_C8000=0x0269;fixed range MTRR + C8xxxMemType:3 + C8xxxWrDram:1 + C8xxxRdDram:1 + :3 + C9xxxMemType:3 + C9xxxWrDram:1 + C9xxxRdDram:1 + :3 + CAxxxMemType:3 + CAxxxWrDram:1 + CAxxxRdDram:1 + :3 + CBxxxMemType:3 + CBxxxWrDram:1 + CBxxxRdDram:1 + :3 + CCxxxMemType:3 + CCxxxWrDram:1 + CCxxxRdDram:1 + :3 + CDxxxMemType:3 + CDxxxWrDram:1 + CDxxxRdDram:1 + :3 + CExxxMemType:3 + CExxxWrDram:1 + CExxxRdDram:1 + :3 + CFxxxMemType:3 + CFxxxWrDram:1 + CFxxxRdDram:1 + :3 +} + +{MTRRfix4K_D0000=0x026a;fixed range MTRR + D0xxxMemType:3 + D0xxxWrDram:1 + D0xxxRdDram:1 + :3 + D1xxxMemType:3 + D1xxxWrDram:1 + D1xxxRdDram:1 + :3 + D2xxxMemType:3 + D2xxxWrDram:1 + D2xxxRdDram:1 + :3 + D3xxxMemType:3 + D3xxxWrDram:1 + D3xxxRdDram:1 + :3 + D4xxxMemType:3 + D4xxxWrDram:1 + D4xxxRdDram:1 + :3 + D5xxxMemType:3 + D5xxxWrDram:1 + D5xxxRdDram:1 + :3 + D6xxxMemType:3 + D6xxxWrDram:1 + D6xxxRdDram:1 + :3 + D7xxxMemType:3 + D7xxxWrDram:1 + D7xxxRdDram:1 + :3 +} + +{MTRRfix4K_D8000=0x026b;fixed range MTRR + D8xxxMemType:3 + D8xxxWrDram:1 + D8xxxRdDram:1 + :3 + D9xxxMemType:3 + D9xxxWrDram:1 + D9xxxRdDram:1 + :3 + DAxxxMemType:3 + DAxxxWrDram:1 + DAxxxRdDram:1 + :3 + DBxxxMemType:3 + DBxxxWrDram:1 + DBxxxRdDram:1 + :3 + DCxxxMemType:3 + DCxxxWrDram:1 + DCxxxRdDram:1 + :3 + DDxxxMemType:3 + DDxxxWrDram:1 + DDxxxRdDram:1 + :3 + DExxxMemType:3 + DExxxWrDram:1 + DExxxRdDram:1 + :3 + DFxxxMemType:3 + DFxxxWrDram:1 + DFxxxRdDram:1 + :3 +} + +{MTRRfix4K_E0000=0x026c;fixed range MTRR + E0xxxMemType:3 + E0xxxWrDram:1 + E0xxxRdDram:1 + :3 + E1xxxMemType:3 + E1xxxWrDram:1 + E1xxxRdDram:1 + :3 + E2xxxMemType:3 + E2xxxWrDram:1 + E2xxxRdDram:1 + :3 + E3xxxMemType:3 + E3xxxWrDram:1 + E3xxxRdDram:1 + :3 + E4xxxMemType:3 + E4xxxWrDram:1 + E4xxxRdDram:1 + :3 + E5xxxMemType:3 + E5xxxWrDram:1 + E5xxxRdDram:1 + :3 + E6xxxMemType:3 + E6xxxWrDram:1 + E6xxxRdDram:1 + :3 + E7xxxMemType:3 + E7xxxWrDram:1 + E7xxxRdDram:1 + :3 +} + +{MTRRfix4K_E8000=0x026d;fixed range MTRR + E8xxxMemType:3 + E8xxxWrDram:1 + E8xxxRdDram:1 + :3 + E9xxxMemType:3 + E9xxxWrDram:1 + E9xxxRdDram:1 + :3 + EAxxxMemType:3 + EAxxxWrDram:1 + EAxxxRdDram:1 + :3 + EBxxxMemType:3 + EBxxxWrDram:1 + EBxxxRdDram:1 + :3 + ECxxxMemType:3 + ECxxxWrDram:1 + ECxxxRdDram:1 + :3 + EDxxxMemType:3 + EDxxxWrDram:1 + EDxxxRdDram:1 + :3 + EExxxMemType:3 + EExxxWrDram:1 + EExxxRdDram:1 + :3 + EFxxxMemType:3 + EFxxxWrDram:1 + EFxxxRdDram:1 + :3 +} + +{MTRRfix4K_F0000=0x026e;fixed range MTRR + F0xxxMemType:3 + F0xxxWrDram:1 + F0xxxRdDram:1 + :3 + F1xxxMemType:3 + F1xxxWrDram:1 + F1xxxRdDram:1 + :3 + F2xxxMemType:3 + F2xxxWrDram:1 + F2xxxRdDram:1 + :3 + F3xxxMemType:3 + F3xxxWrDram:1 + F3xxxRdDram:1 + :3 + F4xxxMemType:3 + F4xxxWrDram:1 + F4xxxRdDram:1 + :3 + F5xxxMemType:3 + F5xxxWrDram:1 + F5xxxRdDram:1 + :3 + F6xxxMemType:3 + F6xxxWrDram:1 + F6xxxRdDram:1 + :3 + F7xxxMemType:3 + F7xxxWrDram:1 + F7xxxRdDram:1 + :3 +} + +{MTRRfix4K_F8000=0x026f;fixed range MTRR + F8xxxMemType:3 + F8xxxWrDram:1 + F8xxxRdDram:1 + :3 + F9xxxMemType:3 + F9xxxWrDram:1 + F9xxxRdDram:1 + :3 + FAxxxMemType:3 + FAxxxWrDram:1 + FAxxxRdDram:1 + :3 + FBxxxMemType:3 + FBxxxWrDram:1 + FBxxxRdDram:1 + :3 + FCxxxMemType:3 + FCxxxWrDram:1 + FCxxxRdDram:1 + :3 + FDxxxMemType:3 + FDxxxWrDram:1 + FDxxxRdDram:1 + :3 + FExxxMemType:3 + FExxxWrDram:1 + FExxxRdDram:1 + :3 + FFxxxMemType:3 + FFxxxWrDram:1 + FFxxxRdDram:1 + :3 +} + +{PAT=0x0277;page attribute table + PA0MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA1MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA2MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA3MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA4MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA5MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA6MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA7MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 +} + +{MTRRdefType=0x02ff;MTRR default memory type + MemType:8 + :2 + MtrrDefTypeFixEn:1 + MtrrDefTypeEn:1 + :52 +} + +{MC0_CTL=0x0400;data cache MC control + ECCI:1 + ECCM:1 + DECC:1 + DMTP:1 + DSTP:1 + L1TP:1 + L2TP:1 + :57 +} + +{MC0_STATUS=0x0401;data cache MC status + ErrorCode:16 + ErrorCodeExt:4 + :4 + Syndrome:8 + :13 + UECC:1 + CECC:1 + Syndrome:8 + :2 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + OVER:1 + VAL:1 +} + +{MC0_ADDR=0x0402;data cache MC address + ADDR:64 +} + +{MC0_MISC=0x0403;data cache MC miscellaneous + :64 +} + +{MC1_CTL=0x0404;instruction cache MC control + ECCI:1 + ECCM:1 + IDP:1 + IMTP:1 + ISTP:1 + L1TP:1 + L2TP:1 + :2 + RDDE:1 + :54 +} + +{MC1_STATUS=0x0405;instruction cache MC status + ErrorCode:16 + ErrorCodeExt:4 + :4 + Syndrome:8 + :13 + UECC:1 + CECC:1 + Syndrome:8 + :2 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + OVER:1 + VAL:1 +} + +{MC1_ADDR=0x0406;instruction cache MC address + ADDR:64 +} + +{MC1_MISC=0x0407;instruction cache MC miscellaneous + :64 +} + +{MC2_CTL=0x0408;BU MC control + SRDE_HP:1 + SRDE_TLB:1 + SRDE_ALL:1 + L2T_PAR:1 + L2T_CECC:1 + L2T_UECC:1 + L2D_PAR:1 + L2D_CECC:1 + L2D_UECC:1 + :1 + VB_PAR:1 + PDC_PAR:1 + :52 +} + +{MC2_STATUS=0x0409;BU MC status + ErrorCode:16 + ErrorCodeExt:4 + :4 + Syndrome:8 + :13 + UECC:1 + CECC:1 + Syndrome:8 + :2 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + OVER:1 + VAL:1 +} + +{MC2_ADDR=0x040a;BU MC address register + ADDR:64 +} + +{MC2_MISC=0x040b;BU MC miscellaneous + :64 +} + +{MC3_CTL=0x040c;LS MC control + SRDE_L:1 + SRDE_S:1 + :62 +} + +{MC3_STATUS=0x040d;LS MC status + ErrorCode:16 + ErrorCodeExt:4 + :4 + Syndrome:8 + :13 + UECC:1 + CECC:1 + Syndrome:8 + :2 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + OVER:1 + VAL:1 +} + +{MC3_ADDR=0x040e;LS MC address + ADDR:64 +} + +{MC3_MISC=0x040f;LS MC miscellaneous + :64 +} + +{MC4_CTL=0x0410;NB MC control + :5 + SyncFloodEn:1 + :2 + MstrAbrtEn:1 + TgtAbrtEn:1 + :1 + AtomicRMWEn:1 + WDTRptEn:1 + DevErrEn:1 + :2 + ProtEn:1 + DataEn:1 + :7 + McaUsPwDatErrEn:1 + :38 +} + +{MC4_STATUS=0x0411;NB MC status + ErrorCode:16 + ErrorCodeExt:5 + :11 + ErrCpu0:1 + ErrCpu1:1 + ErrCpu2:1 + ErrCpu3:1 + BusErr:1 + :20 + PCC:1 + AddrV:1 + :1 + En:1 + UC:1 + Over:1 + Val:1 +} + +{MC4_ADDR=0x0412;NB MC address + McaNbAddrLow:32 + McaNbAddrHigh:32 +} + +{MC4_MISC0=0x0413;reserved (NB MC misc) + :64 +} + +{MC5_CTL=0x0414;FR MC control + CPUWDT:1 + :63 +} + +{MC5_STATUS=0x0415;FR MC status + ErrorCode:16 + ErrorCodeExt:4 + :4 + Syndrome:8 + :13 + UECC:1 + CECC:1 + Syndrome:8 + :2 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + OVER:1 + VAL:1 +} + +{MC5_ADDR=0x0416;FR MC address + ADDR:64 +} + +{MC5_MISC=0x0417;FR MC miscellaneous + State:12 + :52 +} + +{EFER=0xc0000080;extended feature enable + SYSCALL:1 + :7 + LME:1 + :1 + LMA:1 + NXE:1 + SVME:1 + LMSLE:1 + FFXSE:1 + :49 +} + +{STAR=0xc0000081;SYSCALL target address + Target:32 + SysCallSel:16 + SysRetSel:16 +} + +{STAR64=0xc0000082;long mode SYSCALL target address + LSTAR:64 +} + +{STARCOMPAT=0xc0000083;compat mode SYSCALL target address + CSTAR:64 +} + +{SYSCALL_FLAG_MASK=0xc0000084;SYSCALL flag mask + MASK:32 + :32 +} + +{FS_BASE=0xc0000100;FS base + FS_BASE:64 +} + +{GS_BASE=0xc0000101;GS base + GS_BASE:64 +} + +{KernelGSbase=0xc0000102;kernel GS base + KernelGSBase:64 +} + +{TSC_AUX=0xc0000103;auxiliary time stamp counter data + TscAux:32 + :32 +} + +{PERF_CTL0=0xc0010000;performance event select (0) + EventSelect:8 + UnitMask:8 + User:1 + OS:1 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + GuestOnly:1 + HostOnly:1 + :22 +} + +{PERF_CTL1=0xc0010001;performance event select (1) + EventSelect:8 + UnitMask:8 + User:1 + OS:1 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + GuestOnly:1 + HostOnly:1 + :22 +} + +{PERF_CTL2=0xc0010002;performance event select (2) + EventSelect:8 + UnitMask:8 + User:1 + OS:1 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + GuestOnly:1 + HostOnly:1 + :22 +} + +{PERF_CTL3=0xc0010003;performance event select (3) + EventSelect:8 + UnitMask:8 + User:1 + OS:1 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + GuestOnly:1 + HostOnly:1 + :22 +} + +{PERF_CTR0=0xc0010004;performance event counter (0) + CTR:48 + :16 +} + +{PERF_CTR1=0xc0010005;performance event counter (1) + CTR:48 + :16 +} + +{PERF_CTR2=0xc0010006;performance event counter (2) + CTR:48 + :16 +} + +{PERF_CTR3=0xc0010007;performance event counter (3) + CTR:48 + :16 +} + +{SYS_CFG=0xc0010010;system configuration + :8 + SetDirtyEnE:1 + SetDirtyEnS:1 + SetDirtyEnO:1 + :5 + ChxToDirtyDis:1 + SysUcLockEn:1 + MtrrFixDramEn:1 + MtrrFixDramModeEn:1 + MtrrVarDramEn:1 + MtrrTom2En:1 + Tom2ForceMemTypeWB:1 + :41 +} + +{HWCR=0xc0010015;hardware configuration + SmmLock:1 + SlowFence:1 + :1 + TlbCacheDis:1 + INVD_WBINVD:1 + :3 + IgnneEm:1 + MonMwaitDis:1 + MonMwaitUserEn:1 + :2 + SmiSpCycDis:1 + RsmSpCycDis:1 + SseDis:1 + :1 + Wrap32Dis:1 + McStatusWrEn:1 + :1 + IoCfgGpFault:1 + MisAlignSseDis:1 + :1 + ForceUsRdWrSzPrb:1 + TscFreqSel:1 + CpbDis:1 + EffFreqCntMwait:1 + :37 +} + +{IORR_BASE0=0xc0010016;base of variable I/O range (0) + :3 + WrMem:1 + RdMem:1 + :7 + PhyBase:28 + :24 +} + +{IORR_MASK0=0xc0010017;mask of variable I/O range (0) + :11 + Valid:1 + PhyMask:28 + :24 +} + +{IORR_BASE1=0xc0010018;base of variable I/O range (1) + :3 + WrMem:1 + RdMem:1 + :7 + PhyBase:28 + :24 +} + +{IORR_MASK1=0xc0010019;mask of variable I/O range (1) + :11 + Valid:1 + PhyMask:28 + :24 +} + +{TOP_MEM=0xc001001a;top of memory address + :23 + TOM:17 + :24 +} + +{TOM2=0xc001001d;second top of memory address + :23 + TOM2:17 + :24 +} + +{NB_CFG=0xc001001f;northbridge configuration + :45 + DisUsSysMgtReqToNcHt:1 + EnableCf8ExtCfg:1 + :11 + EnConvertToNonIsoc:1 + :5 +} + +{MCEredirection=0xc0010022;MCE redirection + RedirVector:8 + RedirVecEn:1 + RedirSmiEn:1 + :54 +} + +{ProcessorNameString0=0xc0010030;processor name string (0) + CpuNameString:64 +} + +{ProcessorNameString1=0xc0010031;processor name string (1) + CpuNameString:64 +} + +{ProcessorNameString2=0xc0010032;processor name string (2) + CpuNameString:64 +} + +{ProcessorNameString3=0xc0010033;processor name string (3) + CpuNameString:64 +} + +{ProcessorNameString4=0xc0010034;processor name string (4) + CpuNameString:64 +} + +{ProcessorNameString5=0xc0010035;processor name string (5) + CpuNameString:64 +} + +{MC0_CTL_MASK=0xc0010044;data cache MC control mask + ECCI:1 + ECCM:1 + DECC:1 + DMTP:1 + DSTP:1 + L1TP:1 + L2TP:1 + :57 +} + +{MC1_CTL_MASK=0xc0010045;instruction cache MC control mask + ECCI:1 + ECCM:1 + IDP:1 + IMTP:1 + ISTP:1 + L1TP:1 + L2TP:1 + :2 + RDDE:1 + :54 +} + +{MC2_CTL_MASK=0xc0010046;BU MC control mask + SRDE_HP:1 + SRDE_TLB:1 + SRDE_ALL:1 + L2T_PAR:1 + L2T_CECC:1 + L2T_UECC:1 + L2D_PAR:1 + L2D_CECC:1 + L2D_UECC:1 + :1 + VB_PAR:1 + PDC_PAR:1 + :52 +} + +{MC3_CTL_MASK=0xc0010047;LS MC control mask + SRDE_L:1 + SRDE_S:1 + :62 +} + +{MC4_CTL_MASK=0xc0010048;NB MC control mask + :5 + SyncFloodEn:1 + :2 + MstrAbrtEn:1 + TgtAbrtEn:1 + :1 + AtomicRMWEn:1 + WDTRptEn:1 + DevErrEn:1 + :2 + ProtEn:1 + DataEn:1 + :7 + McaUsPwDatErrEn:1 + :38 +} + +{MC5_CTL_MASK=0xc0010049;FR MC control mask + CPUWDT:1 + :63 +} + +{SMI_ON_IO_TRAP_0=0xc0010050;IO trap address (0) + SmiAddr:32 + SmiMask:24 + :5 + ConfigSmi:1 + SmiOnWrEn:1 + SmiOnRdEn:1 +} + +{SMI_ON_IO_TRAP_1=0xc0010051;IO trap address (1) + SmiAddr:32 + SmiMask:24 + :5 + ConfigSmi:1 + SmiOnWrEn:1 + SmiOnRdEn:1 +} + +{SMI_ON_IO_TRAP_2=0xc0010052;IO trap address (2) + SmiAddr:32 + SmiMask:24 + :5 + ConfigSmi:1 + SmiOnWrEn:1 + SmiOnRdEn:1 +} + +{SMI_ON_IO_TRAP_3=0xc0010053;IO trap address (3) + SmiAddr:32 + SmiMask:24 + :5 + ConfigSmi:1 + SmiOnWrEn:1 + SmiOnRdEn:1 +} + +{SMI_ON_IO_TRAP_CTL_STS=0xc0010054;IO trap control + :1 + SmiEn_0:1 + :1 + SmiEn_1:1 + :1 + SmiEn_2:1 + :1 + SmiEn_3:1 + :7 + IoTrapEn:1 + :48 +} + +{SmiTriggerIoCycle=0xc0010056;SMI trigger IO cycle + IoPortAddress:16 + IoData:8 + :1 + IoCycleEn:1 + IoRd:1 + :37 +} + +{MmioConfigBase=0xc0010058;MMIO configuration base address + Enable:1 + :1 + SegBusRange:4;0=1;1=2;2=4;3=8;4=16;5=32;6=64;7=128;8=256 + :14 + MmiocCfgBaseAddr:20 + :24 +} + +{BistResults=0xc0010060;BIST results + BistResults:32 + :32 +} + +{PstateCurrentLimit=0xc0010061;P-state current limit + CurPstateLimit:3 + :1 + PstateMaxVal:3 + :57 +} + +{PstateControl=0xc0010062;P-state control + PstateCmd:3 + :61 +} + +{PstateStatus=0xc0010063;P-state status + CurPstate:3 + :61 +} + +{Pstate0=0xc0010064;P-state 0 + CpuDid:4 + CpuFid:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate1=0xc0010065;P-state 1 + CpuDid:4 + CpuFid:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate2=0xc0010066;P-state 2 + CpuDid:4 + CpuFid:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate3=0xc0010067;P-state 3 + CpuDid:4 + CpuFid:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate4=0xc0010068;P-state 4 + CpuDid:4 + CpuFid:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate5=0xc0010069;P-state 5 + CpuDid:4 + CpuFid:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate6=0xc001006a;P-state 6 + CpuDid:4 + CpuFid:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate7=0xc001006b;P-state 7 + CpuDid:4 + CpuFid:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{COFVIDcontrol=0xc0010070;COFVID control + CpuDid:4 + CpuFid:5 + CpuVid:7 + PstateId:3 + IgnorVidFidDid:1 + :44 +} + +{COFVIDstatus=0xc0010071;COFVID status + CurCpuDid:4 + CurCpuFid:5 + CurCpuVid:7 + CurPstate:3 + :1 + PstateInProgress:1 + :4 + CurNbVid:7 + StartupPstate:3 + MaxVid:7 + MinVid:7 + MainPllOpFreqIdMax:6 + :1 + CurPstateLimit:3 + :5 +} + +{CstateAddress=0xc0010073;C-state address + CstateAddr:16 + :48 +} + +{CpuWdTmrCfg=0xc0010074;CPU watchdog timer + CpuWdtEn:1 + CpuWdtTimeBase:2 + CpuWdtCountSel:4 + :57 +} + +{SMM_BASE=0xc0010111;SMM base address + SMM_BASE:32 + :32 +} + +{SMMAddr=0xc0010112;SMM TSeg base address + :17 + TSegBase:23 + :24 +} + +{SMMMask=0xc0010113;SMM Tseg mask + AValid:1 + TValid:1 + AClose:1 + TClose:1 + AMTypeIoWc:1 + TMTypeIoWc:1 + :2 + AMTypeDram:3 + :1 + TMTypeDram:3 + :2 + TSegMask:23 + :24 +} + +{VM_CR=0xc0010114;virtual machine control + dpd:1 + r_init:1 + dis_a20m:1 + Lock:1 + Svme_Disable:1 + :59 +} + +{IGNNE=0xc0010115;IGNNE + IGNNE:1 + :63 +} + +# {SMM_CTL=0xc0010116;SMM control +# smm_dismiss:1 +# smm_enter:1 +# smi_cyle:1 +# smm_exit:1 +# rsm_cycle:1 +# :59 +# } # write-only + +{VM_HSAVE_PA=0xc0010117;virtual machine host save physical address + :12 + VM_HSAVE_PA:28 + :24 +} + +# {SVMLock=0xc0010118;SVM lock key +# SvmLockKey:64 +# } # write-only + +# {SMMLock=0xc0010119;SMM lock key +# SmmLockKey:64 +# } # write-only + +{SMIstatus=0xc001011a;local SMI status + IoTrapSts:4 + :4 + MceRedirSts:1 + :7 + SmiSrcLvtLcy:1 + SmiSrcLvtExt:1 + :46 +} + +{OSVW_ID_Length=0xc0010140;OS visible work-around + OSVW_ID_Length:16 + :48 +} + +{OsvwStatus=0xc0010141;OS visible work-around status bits + OsvwStatusBits:64 +} + +{CPUIDFeatures=0xc0011004;CPUID features + FeaturesEdx:32 + FeaturesEcx:32 +} + +{CPUIDExtFeatures=0xc0011005;extended CPUID features + ExtFeaturesEdx:32 + ExtFeaturesEcx:32 +} + +{LS_CFG=0xc0011020;load store configuration + :28 + DIS_SS:1 + :35 +} + +{IC_CFG=0xc0011021;instruction cache configuration + :9 + DIS_SPEC_TLB_RLD:1 + :54 +} + +{DC_CFG=0xc0011022;data cache configuration + :4 + DIS_SPEC_TLB_RLD:1 + :3 + DIS_CLR_WBTOL2_SMC_HIT:1 + :4 + DIS_HW_PF:1 + :50 +} + +{DE_CFG=0xc0011029;decode configuration + :23 + ClflushSerialize:1 + :13 +} + +{BU_CFG2=0xc001102A;bus unit configuration 2 + :35 + IcDisSpecTlbWr:1 + :14 + RdMmExtCfgDwDis:1 + :5 + L2ClkGatingEn:1 + L2HystCnt:2 + :5 +} + +{IbsFetchCtl=0xc0011030;IBS fetch control + IbsFetchMaxCnt:16 + IbsFetchCnt:16 + IbsFetchLat:16 + IbsFetchEn:1 + IbsFetchVal:1 + IbsFetchComp:1 + IbsIcMiss:1 + IbsPhyAddrValid:1 + IbsL1TlbPgSz:2 + IbsL1TlbMiss:1 + IbsL2TlbMiss:1 + IbsRandEn:1 + :6 +} + +{IbsFetchLinAd=0xc0011031;IBS fetch linear address + IbsFetchLinAd:64 +} + +{IbsFetchPhysAd=0xc0011032;IBS fetch physical address + IbsFetchPhysAd:64 +} + +{IbsOpCtl=0xc0011033;IBS execution control + IbsOpMaxCnt:16 + :1 + IbsOpEn:1 + IbsOpVal:1 + IbsOpCntCtl:1 + IbsOpMaxCntExt:7 + :5 + IbsOpCurCnt:20 + IbsOpCurCntExt:7 + :5 +} + +{IbsOpRip=0xc0011034;IBS Op logical address + IbsOpRip:64 +} + +{IbsOpData=0xc0011035;IBS Op data + IbsCompToRetCtr:16 + IbsTagToRetCtr:16 + IbsOpBrnResync:1 + IbsOpMispReturn:1 + IbsOpReturn:1 + IbsOpBrnTaken:1 + IbsOpBrnMisp:1 + IbsOpBrnRet:1 + IbsRipInvalid:1 + :25 +} + +{IbsOpData2=0xc0011036;IBS Op data 2 + NbIbsReqSrc:3 + :61 +} + +{IbsOpData3=0xc0011037;IBS Op data 3 + IbsLdOp:1 + IbsStOp:1 + IbsDcL1tlbMiss:1 + IbsDcL2tlbMiss:1 + IbsDcL1tlbHit2M:1 + IbsDcL1tlbHit1G:1 + IbsDcL2tlbHit2M:1 + IbsDcMiss:1 + IbsDcMisAcc:1 + IbsDcLdBnkCon:1 + IbsDcStBnkCon:1 + IbsDcStToLdFwd:1 + IbsDcStToLdCan:1 + IbsDcWcMemAcc:1 + IbsDcUcMemAcc:1 + IbsDcLockedOp:1 + IbsDcMabHit:1 + IbsDcLinAddrValid:1 + IbsDcPhyAddrValid:1 + IbsDcL2tlbHit1G:1 + :12 + IbsDcMissLat:16 + :16 +} + +{IbsDcLinAd=0xc0011038;IBS DC linear address + IbsDcLinAd:64 +} + +{IbsDcPhysAd=0xc0011039;IBS DC physical address + IbsDcPhysAd:64 +} + +{IbsControl=0xc001103a;IBS control + LvtOffset:4 + :4 + LvtOffsetVal:1 + :55 +} + +{IbsBranchTargetAddress=0xc001103b;IBS branch target address + IbsBrTarget:64 +} + +### Local Variables: ### +### mode:shell-script ### +### End: ###
[-] [+]	Added	x86info-1.30.tar.bz2/AMD/fam14h.regs ^
@@ -0,0 +1,1612 @@ +# Author: Andreas Herrmann <andreas.herrmann3@amd.com> +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. + +# This file contains information from: +# - "43170 Rev 3.09 - May 02, 2011, BIOS and Kernel Developer's Guide (BKDG) +# for AMD Family 14h Models 00h-0Fh Processors" + +# See scripts/createheader.py for the general format of this register +# definitions. + +{LSMCAaddr=0x0000;load-store MCA address + ADDR:48 + :16 +} # alias of MC0_ADDR + +{LSMCAstatus=0x0001;load-store MCE status + ErrorCode:16 + ErrorCodeExt:4 + :37 + PCC:1 + AddrV:1 + :1 + En:1 + UC:1 + OVER:1 + VAL:1 +} # alias of MC0_STATUS + +{TSC=0x0010;time-stamp counter + TSC:64 +} + +{APIC_BASE=0x001b;APIC base address + :8 + BSC:1 + :2 + ApicEn:1 + ApicBar:28 + :24 +} + +{EBL_CR_POWERON=0x002a;cluster ID + :16 + ClusterID:2 + :46 +} + +{PATCH_LEVEL=0x008b;microcode patch level + PATCH_LEVEL:32 + :32 +} + +{MPERF=0x00e7;max performance frequency clock count + MPERF:64 +} + +{APERF=0x00e8;actual performance frequency clock count + APERF:64 +} + +{MTRRcap=0x00fe;MTRR capabilities + MtrrCapVCnt:8 + MtrrCapFix:1 + :1 + MtrrCapWc:1 + :53 +} + +{SYSENTER_CS=0x0174;SYSENTER/SYSEXIT code segment selector + SYSENTER_CS:16 + :48 +} + +{SYSENTER_ESP=0x0175;SYSENTER/SYSEXIT stack pointer + SYSENTER_ESP:32 + :32 +} + +{SYSENTER_EIP=0x0176;SYSENTER/SYSEXIT instruction pointer + SYSENTER_EIP:32 + :32 +} + +{MCG_CAP=0x0179;global MC capabilities + Count:8 + MCG_CTL_P:1 + :55 +} + +{MCG_STAT=0x017a;global MC status + RIPV:1 + EIPV:1 + MCIP:1 + :61 +} + +{MCG_CTL=0x017b;global MC control + MC0En:1 + MC1En:1 + MC2En:1 + MC3En:1 + MC4En:1 + MC5En:1 + :58 +} + +{DBG_CTL_MSR=0x01d9;debug control + LBR:1 + BTF:1 + PB0:1 + PB1:1 + PB2:1 + PB3:1 + :58 +} + +{BR_FROM=0x01db;last branch from IP + LastBranchFromIP:64 +} + +{BR_TO=0x01dc;last branch to IP + LastBranchToIP:64 +} + +{LastExceptionFromIP=0x01dd;last exception from IP + LastIntFromIP:64 +} + +{LastExceptionToIP=0x01de;last exception to IP + LastIntToIP:64 +} + +{MTRRphysBase0=0x0200;base of variable-size MTRR (0) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:24 + :28 +} + +{MTRRphysMask0=0x0201;mask of variable-size MTRR (0) + :11 + Valid:1 + PhysMask:24 + :28 +} + +{MTRRphysBase1=0x0202;base of variable-size MTRR (1) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:24 + :28 +} + +{MTRRphysMask1=0x0203;mask of variable-size MTRR (1) + :11 + Valid:1 + PhysMask:24 + :28 +} + +{MTRRphysBase2=0x0204;base of variable-size MTRR (2) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:24 + :28 +} + +{MTRRphysMask2=0x0205;mask of variable-size MTRR (2) + :11 + Valid:1 + PhysMask:24 + :28 +} + +{MTRRphysBase3=0x0206;base of variable-size MTRR (3) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:24 + :28 +} + +{MTRRphysMask3=0x0207;mask of variable-size MTRR (3) + :11 + Valid:1 + PhysMask:24 + :28 +} + +{MTRRphysBase4=0x0208;base of variable-size MTRR (4) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:24 + :28 +} + +{MTRRphysMask4=0x0209;mask of variable-size MTRR (4) + :11 + Valid:1 + PhysMask:24 + :28 +} + +{MTRRphysBase5=0x020a;base of variable-size MTRR (5) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:24 + :28 +} + +{MTRRphysMask5=0x020b;mask of variable-size MTRR (5) + :11 + Valid:1 + PhysMask:24 + :28 +} + +{MTRRphysBase6=0x020c;base of variable-size MTRR (6) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:24 + :28 +} + +{MTRRphysMask6=0x020d;mask of variable-size MTRR (6) + :11 + Valid:1 + PhysMask:24 + :28 +} + +{MTRRphysBase7=0x020e;base of variable-size MTRR (7) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:24 + :28 +} + +{MTRRphysMask7=0x020f;mask of variable-size MTRR (7) + :11 + Valid:1 + PhysMask:24 + :28 +} + +{MTRRfix64K_00000=0x0250;fixed range MTRR + 0xxxxMemType:3 + 0xxxxWrDram:1 + 0xxxxRdDram:1 + :3 + 1xxxxMemType:3 + 1xxxxWrDram:1 + 1xxxxRdDram:1 + :3 + 2xxxxMemType:3 + 2xxxxWrDram:1 + 2xxxxRdDram:1 + :3 + 3xxxxMemType:3 + 3xxxxWrDram:1 + 3xxxxRdDram:1 + :3 + 4xxxxMemType:3 + 4xxxxWrDram:1 + 4xxxxRdDram:1 + :3 + 5xxxxMemType:3 + 5xxxxWrDram:1 + 5xxxxRdDram:1 + :3 + 6xxxxMemType:3 + 6xxxxWrDram:1 + 6xxxxRdDram:1 + :3 + 7xxxxMemType:3 + 7xxxxWrDram:1 + 7xxxxRdDram:1 + :3 +} + +{MTRRfix16K_80000=0x0258;fixed range MTRR + 80xxxMemType:3 + 80xxxWrDram:1 + 80xxxRdDram:1 + :3 + 84xxxMemType:3 + 84xxxWrDram:1 + 84xxxRdDram:1 + :3 + 88xxxMemType:3 + 88xxxWrDram:1 + 88xxxRdDram:1 + :3 + 8CxxxMemType:3 + 8CxxxWrDram:1 + 8CxxxRdDram:1 + :3 + 90xxxMemType:3 + 90xxxWrDram:1 + 90xxxRdDram:1 + :3 + 94xxxMemType:3 + 94xxxWrDram:1 + 94xxxRdDram:1 + :3 + 98xxxMemType:3 + 98xxxWrDram:1 + 98xxxRdDram:1 + :3 + 9CxxxMemType:3 + 9CxxxWrDram:1 + 9CxxxRdDram:1 + :3 +} + +{MTRRfix16K_A0000=0x0259;fixed range MTRR + A0xxxMemType:3 + A0xxxWrDram:1 + A0xxxRdDram:1 + :3 + A4xxxMemType:3 + A4xxxWrDram:1 + A4xxxRdDram:1 + :3 + A8xxxMemType:3 + A8xxxWrDram:1 + A8xxxRdDram:1 + :3 + ACxxxMemType:3 + ACxxxWrDram:1 + ACxxxRdDram:1 + :3 + B0xxxMemType:3 + B0xxxWrDram:1 + B0xxxRdDram:1 + :3 + B4xxxMemType:3 + B4xxxWrDram:1 + B4xxxRdDram:1 + :3 + B8xxxMemType:3 + B8xxxWrDram:1 + B8xxxRdDram:1 + :3 + BCxxxMemType:3 + BCxxxWrDram:1 + BCxxxRdDram:1 + :3 +} + +{MTRRfix4K_C0000=0x0268;fixed range MTRR + C0xxxMemType:3 + C0xxxWrDram:1 + C0xxxRdDram:1 + :3 + C1xxxMemType:3 + C1xxxWrDram:1 + C1xxxRdDram:1 + :3 + C2xxxMemType:3 + C2xxxWrDram:1 + C2xxxRdDram:1 + :3 + C3xxxMemType:3 + C3xxxWrDram:1 + C3xxxRdDram:1 + :3 + C4xxxMemType:3 + C4xxxWrDram:1 + C4xxxRdDram:1 + :3 + C5xxxMemType:3 + C5xxxWrDram:1 + C5xxxRdDram:1 + :3 + C6xxxMemType:3 + C6xxxWrDram:1 + C6xxxRdDram:1 + :3 + C7xxxMemType:3 + C7xxxWrDram:1 + C7xxxRdDram:1 + :3 +} + +{MTRRfix4K_C8000=0x0269;fixed range MTRR + C8xxxMemType:3 + C8xxxWrDram:1 + C8xxxRdDram:1 + :3 + C9xxxMemType:3 + C9xxxWrDram:1 + C9xxxRdDram:1 + :3 + CAxxxMemType:3 + CAxxxWrDram:1 + CAxxxRdDram:1 + :3 + CBxxxMemType:3 + CBxxxWrDram:1 + CBxxxRdDram:1 + :3 + CCxxxMemType:3 + CCxxxWrDram:1 + CCxxxRdDram:1 + :3 + CDxxxMemType:3 + CDxxxWrDram:1 + CDxxxRdDram:1 + :3 + CExxxMemType:3 + CExxxWrDram:1 + CExxxRdDram:1 + :3 + CFxxxMemType:3 + CFxxxWrDram:1 + CFxxxRdDram:1 + :3 +} + +{MTRRfix4K_D0000=0x026a;fixed range MTRR + D0xxxMemType:3 + D0xxxWrDram:1 + D0xxxRdDram:1 + :3 + D1xxxMemType:3 + D1xxxWrDram:1 + D1xxxRdDram:1 + :3 + D2xxxMemType:3 + D2xxxWrDram:1 + D2xxxRdDram:1 + :3 + D3xxxMemType:3 + D3xxxWrDram:1 + D3xxxRdDram:1 + :3 + D4xxxMemType:3 + D4xxxWrDram:1 + D4xxxRdDram:1 + :3 + D5xxxMemType:3 + D5xxxWrDram:1 + D5xxxRdDram:1 + :3 + D6xxxMemType:3 + D6xxxWrDram:1 + D6xxxRdDram:1 + :3 + D7xxxMemType:3 + D7xxxWrDram:1 + D7xxxRdDram:1 + :3 +} + +{MTRRfix4K_D8000=0x026b;fixed range MTRR + D8xxxMemType:3 + D8xxxWrDram:1 + D8xxxRdDram:1 + :3 + D9xxxMemType:3 + D9xxxWrDram:1 + D9xxxRdDram:1 + :3 + DAxxxMemType:3 + DAxxxWrDram:1 + DAxxxRdDram:1 + :3 + DBxxxMemType:3 + DBxxxWrDram:1 + DBxxxRdDram:1 + :3 + DCxxxMemType:3 + DCxxxWrDram:1 + DCxxxRdDram:1 + :3 + DDxxxMemType:3 + DDxxxWrDram:1 + DDxxxRdDram:1 + :3 + DExxxMemType:3 + DExxxWrDram:1 + DExxxRdDram:1 + :3 + DFxxxMemType:3 + DFxxxWrDram:1 + DFxxxRdDram:1 + :3 +} + +{MTRRfix4K_E0000=0x026c;fixed range MTRR + E0xxxMemType:3 + E0xxxWrDram:1 + E0xxxRdDram:1 + :3 + E1xxxMemType:3 + E1xxxWrDram:1 + E1xxxRdDram:1 + :3 + E2xxxMemType:3 + E2xxxWrDram:1 + E2xxxRdDram:1 + :3 + E3xxxMemType:3 + E3xxxWrDram:1 + E3xxxRdDram:1 + :3 + E4xxxMemType:3 + E4xxxWrDram:1 + E4xxxRdDram:1 + :3 + E5xxxMemType:3 + E5xxxWrDram:1 + E5xxxRdDram:1 + :3 + E6xxxMemType:3 + E6xxxWrDram:1 + E6xxxRdDram:1 + :3 + E7xxxMemType:3 + E7xxxWrDram:1 + E7xxxRdDram:1 + :3 +} + +{MTRRfix4K_E8000=0x026d;fixed range MTRR + E8xxxMemType:3 + E8xxxWrDram:1 + E8xxxRdDram:1 + :3 + E9xxxMemType:3 + E9xxxWrDram:1 + E9xxxRdDram:1 + :3 + EAxxxMemType:3 + EAxxxWrDram:1 + EAxxxRdDram:1 + :3 + EBxxxMemType:3 + EBxxxWrDram:1 + EBxxxRdDram:1 + :3 + ECxxxMemType:3 + ECxxxWrDram:1 + ECxxxRdDram:1 + :3 + EDxxxMemType:3 + EDxxxWrDram:1 + EDxxxRdDram:1 + :3 + EExxxMemType:3 + EExxxWrDram:1 + EExxxRdDram:1 + :3 + EFxxxMemType:3 + EFxxxWrDram:1 + EFxxxRdDram:1 + :3 +} + +{MTRRfix4K_F0000=0x026e;fixed range MTRR + F0xxxMemType:3 + F0xxxWrDram:1 + F0xxxRdDram:1 + :3 + F1xxxMemType:3 + F1xxxWrDram:1 + F1xxxRdDram:1 + :3 + F2xxxMemType:3 + F2xxxWrDram:1 + F2xxxRdDram:1 + :3 + F3xxxMemType:3 + F3xxxWrDram:1 + F3xxxRdDram:1 + :3 + F4xxxMemType:3 + F4xxxWrDram:1 + F4xxxRdDram:1 + :3 + F5xxxMemType:3 + F5xxxWrDram:1 + F5xxxRdDram:1 + :3 + F6xxxMemType:3 + F6xxxWrDram:1 + F6xxxRdDram:1 + :3 + F7xxxMemType:3 + F7xxxWrDram:1 + F7xxxRdDram:1 + :3 +} + +{MTRRfix4K_F8000=0x026f;fixed range MTRR + F8xxxMemType:3 + F8xxxWrDram:1 + F8xxxRdDram:1 + :3 + F9xxxMemType:3 + F9xxxWrDram:1 + F9xxxRdDram:1 + :3 + FAxxxMemType:3 + FAxxxWrDram:1 + FAxxxRdDram:1 + :3 + FBxxxMemType:3 + FBxxxWrDram:1 + FBxxxRdDram:1 + :3 + FCxxxMemType:3 + FCxxxWrDram:1 + FCxxxRdDram:1 + :3 + FDxxxMemType:3 + FDxxxWrDram:1 + FDxxxRdDram:1 + :3 + FExxxMemType:3 + FExxxWrDram:1 + FExxxRdDram:1 + :3 + FFxxxMemType:3 + FFxxxWrDram:1 + FFxxxRdDram:1 + :3 +} + +{PAT=0x0277;page attribute table + PA0MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA1MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA2MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA3MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA4MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA5MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA6MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA7MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 +} + +{MTRRdefType=0x02ff;MTRR default memory type + MemType:8 + :2 + MtrrDefTypeFixEn:1 + MtrrDefTypeEn:1 + :52 +} + +{MC0_CTL=0x0400;data cache MC control + :2 + DDP:1 + DTP:1 + :2 + TLBP:1 + :1 + SRDEL:1 + SRDES:1 + SRDET:1 + SRDE_ALL:1 + :52 +} + +{MC0_STATUS=0x0401;data cache MC status + ErrorCode:16 + ErrorCodeExt:4 + :37 + PCC:1 + AddrV:1 + :1 + En:1 + UC:1 + OVER:1 + VAL:1 +} + +{MC0_ADDR=0x0402;data cache MC address + ADDR:48 + :16 +} + +{MC0_MISC=0x0403;data cache MC miscellaneous + :64 +} + +{MC1_CTL=0x0404;instruction cache MC control + :2 + IDP:1 + ITP:1 + ISTP:1 + :1 + TLBP:1 + :2 + SRDE:1 + :54 +} + +{MC1_STATUS=0x0405;instruction cache MC status + ErrorCode:16 + ErrorCodeExt:4 + :37 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + OVER:1 + VAL:1 +} + +{MC1_ADDR=0x0406;instruction cache MC address + ADDR:48 + :16 +} + +{MC1_MISC=0x0407;instruction cache MC miscellaneous + :64 +} + +{MC2_CTL=0x0408;bus unit MC control + :4 + TagCor:1 + TagUncor:1 + DataParity:1 + DataCor:1 + DataUncor:1 + :3 + TagMultiHit:1 + AttrParity:1 + :50 +} + +{MC2_STATUS=0x0409;bus unit MC status + ErrorCode:16 + ErrorCodeExt:5 + :24 + UECC:1 + CECC:1 + :10 + PCC:1 + AddrV:1 + :1 + En:1 + UC:1 + OVER:1 + VAL:1 +} + +{MC2_ADDR=0x040a;bus unit MC address register + ADDR:36 + :28 +} + +{MC2_MISC=0x040b;bus unit MC miscellaneous + :64 +} + +{MC3_CTL=0x040c;reserved + :64 +} + +{MC3_STATUS=0x040d;reserved + :64 +} + +{MC3_ADDR=0x040e;reserved + :64 +} + +{MC3_MISC=0x040f;reserved + :64 +} + +{MC4_CTL=0x0410;northbridge MC control + :5 + SyncFloodEn:1 + :2 + MstrAbrtEn:1 + TgtAbrtEn:1 + :1 + AtomicRMWEn:1 + WDTRptEn:1 + DevErrEn:1 + :2 + NbIntProtEn:1 + CpPktDatEn:1 + :7 + UsPwDatErrEn:1 + :38 +} + +{MC4_STATUS=0x0411;northbridge MC status + ErrorCode:16 + ErrorCodeExt:5 + :11 + ErrCpu0:1 + ErrCpu1:1 + :2 + BusErr:1 + :20 + PCC:1 + AddrV:1 + :1 + En:1 + UC:1 + Over:1 + Val:1 +} + +{MC4_ADDR=0x0412;northbridge MC address + McaNbAddrLow:32 + McaNbAddrHigh:32 +} + +{MC4_MISC0=0x0413;reserved (northbridge MC misc) + :64 +} + +{MC5_CTL=0x0414;reorder buffer MC control + CPUWDT:1 + :63 +} + +{MC5_STATUS=0x0415;reorder buffer MC status + ErrorCode:16 + :41 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + OVER:1 + VAL:1 +} + +{MC5_ADDR=0x0416;reorder buffer MC address + ADDR:48 + :16 +} + +{MC5_MISC=0x0417;reorder buffer MC miscellaneous + FrCompl:8 + :56 +} + +{EFER=0xc0000080;extended feature enable + SYSCALL:1 + :7 + LME:1 + :1 + LMA:1 + NXE:1 + SVME:1 + LMSLE:1 + FFXSE:1 + :49 +} + +{STAR=0xc0000081;SYSCALL target address + Target:32 + SysCallSel:16 + SysRetSel:16 +} + +{STAR64=0xc0000082;long mode SYSCALL target address + LSTAR:64 +} + +{STARCOMPAT=0xc0000083;compat mode SYSCALL target address + CSTAR:64 +} + +{SYSCALL_FLAG_MASK=0xc0000084;SYSCALL flag mask + MASK:32 + :32 +} + +{FS_BASE=0xc0000100;FS base + FS_BASE:64 +} + +{GS_BASE=0xc0000101;GS base + GS_BASE:64 +} + +{KernelGSbase=0xc0000102;kernel GS base + KernelGSBase:64 +} + +{TSC_AUX=0xc0000103;auxiliary time stamp counter data + TscAux:32 + :32 +} + +{PERF_CTL0=0xc0010000;performance event select (0) + EventSelect:8 + UnitMask:8 + User:1 + OS:1 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + GuestOnly:1 + HostOnly:1 + :22 +} + +{PERF_CTL1=0xc0010001;performance event select (1) + EventSelect:8 + UnitMask:8 + User:1 + OS:1 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + GuestOnly:1 + HostOnly:1 + :22 +} + +{PERF_CTL2=0xc0010002;performance event select (2) + EventSelect:8 + UnitMask:8 + User:1 + OS:1 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + GuestOnly:1 + HostOnly:1 + :22 +} + +{PERF_CTL3=0xc0010003;performance event select (3) + EventSelect:8 + UnitMask:8 + User:1 + OS:1 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + GuestOnly:1 + HostOnly:1 + :22 +} + +{PERF_CTR0=0xc0010004;performance event counter (0) + CTR:48 + :16 +} + +{PERF_CTR1=0xc0010005;performance event counter (1) + CTR:48 + :16 +} + +{PERF_CTR2=0xc0010006;performance event counter (2) + CTR:48 + :16 +} + +{PERF_CTR3=0xc0010007;performance event counter (3) + CTR:48 + :16 +} + +{SYS_CFG=0xc0010010;system configuration + :17 + SysUcLockEn:1 + MtrrFixDramEn:1 + MtrrFixDramModeEn:1 + MtrrVarDramEn:1 + MtrrTom2En:1 + Tom2ForceMemTypeWB:1 + :41 +} + +{HWCR=0xc0010015;hardware configuration + SmmLock:1 + :2 + TlbCacheDis:1 + INVD_WBINVD:1 + :3 + IgnneEm:1 + MonMwaitDis:1 + MonMwaitUserEn:1 + :2 + SmiSpCycDis:1 + RsmSpCycDis:1 + SseDis:1 + :1 + Wrap32Dis:1 + McStatusWrEn:1 + :1 + IoCfgGpFault:1 + MisAlignSseDis:1 + :1 + ForceUsRdWrSzPrb:1 + TscFreqSel:1 + :1 + EffFreqCntMwait:1 + :37 +} + +{IORR_BASE0=0xc0010016;base of variable I/O range (0) + :3 + WrMem:1 + RdMem:1 + :7 + PhyBase:24 + :28 +} + +{IORR_MASK0=0xc0010017;mask of variable I/O range (0) + :11 + Valid:1 + PhyMask:24 + :28 +} + +{IORR_BASE1=0xc0010018;base of variable I/O range (1) + :3 + WrMem:1 + RdMem:1 + :7 + PhyBase:24 + :28 +} + +{IORR_MASK1=0xc0010019;mask of variable I/O range (1) + :11 + Valid:1 + PhyMask:24 + :28 +} + +{TOP_MEM=0xc001001a;top of memory address + :23 + TOM:13 + :28 +} + +{TOM2=0xc001001d;second top of memory address + :23 + TOM2:13 + :28 +} + +{NB_CFG=0xc001001f;northbridge configuration + :45 + DisUsSysMgtReqToNcHt:1 + EnableCf8ExtCfg:1 + :11 + EnConvertToNonIsoc:1 + :5 +} + +{MCEredirection=0xc0010022;MCE redirection + RedirVector:8 + RedirVecEn:1 + RedirSmiEn:1 + :54 +} + +{ProcessorNameString0=0xc0010030;processor name string (0) + CpuNameString:64 +} + +{ProcessorNameString1=0xc0010031;processor name string (1) + CpuNameString:64 +} + +{ProcessorNameString2=0xc0010032;processor name string (2) + CpuNameString:64 +} + +{ProcessorNameString3=0xc0010033;processor name string (3) + CpuNameString:64 +} + +{ProcessorNameString4=0xc0010034;processor name string (4) + CpuNameString:64 +} + +{ProcessorNameString5=0xc0010035;processor name string (5) + CpuNameString:64 +} + +{MC0_CTL_MASK=0xc0010044;data cache MC control mask + :2 + DDP:1 + DTP:1 + :2 + TLBP:1 + :1 + SRDEL:1 + SRDES:1 + SRDET:1 + SRDE_ALL:1 + :52 +} + +{MC1_CTL_MASK=0xc0010045;instruction cache MC control mask + :2 + IDP:1 + ITP:1 + ISTP:1 + :1 + TLBP:1 + :2 + SRDE:1 + :54 +} + +{MC2_CTL_MASK=0xc0010046;bus unit MC control mask + :4 + TagCor:1 + TagUncor:1 + DataParity:1 + DataCor:1 + DataUncor:1 + :3 + TagMultiHit:1 + AttrParity:1 + :50 +} + +{MC3_CTL_MASK=0xc0010047;reserved + :64 +} + +{MC4_CTL_MASK=0xc0010048;northbridge MC control mask + :5 + SyncFloodEn:1 + :2 + MstrAbrtEn:1 + TgtAbrtEn:1 + :1 + AtomicRMWEn:1 + WDTRptEn:1 + DevErrEn:1 + :2 + NbIntProtEn:1 + CpPktDatEn:1 + :7 + UsPwDatErrEn:1 + :38 +} + +{MC5_CTL_MASK=0xc0010049;reorder buffer MC control mask + CPUWDT:1 + :63 +} + +{SMI_ON_IO_TRAP_0=0xc0010050;IO trap address (0) + SmiAddr:32 + SmiMask:24 + :5 + ConfigSmi:1 + SmiOnWrEn:1 + SmiOnRdEn:1 +} + +{SMI_ON_IO_TRAP_1=0xc0010051;IO trap address (1) + SmiAddr:32 + SmiMask:24 + :5 + ConfigSmi:1 + SmiOnWrEn:1 + SmiOnRdEn:1 +} + +{SMI_ON_IO_TRAP_2=0xc0010052;IO trap address (2) + SmiAddr:32 + SmiMask:24 + :5 + ConfigSmi:1 + SmiOnWrEn:1 + SmiOnRdEn:1 +} + +{SMI_ON_IO_TRAP_3=0xc0010053;IO trap address (3) + SmiAddr:32 + SmiMask:24 + :5 + ConfigSmi:1 + SmiOnWrEn:1 + SmiOnRdEn:1 +} + +{SMI_ON_IO_TRAP_CTL_STS=0xc0010054;IO trap control + :1 + SmiEn_0:1 + :1 + SmiEn_1:1 + :1 + SmiEn_2:1 + :1 + SmiEn_3:1 + :7 + IoTrapEn:1 + :48 +} + +{IntPendingMessage=0xc0010055;reserved + :64 +} + +{SmiTriggerIoCycle=0xc0010056;SMI trigger IO cycle + IoPortAddress:16 + IoData:8 + :1 + IoCycleEn:1 + IoRd:1 + :37 +} + +{MmioConfigBase=0xc0010058;MMIO configuration base address + Enable:1 + :1 + SegBusRange:4;0=1;1=2;2=4;3=8;4=16;5=32;6=64;7=128;8=256 + :14 + MmiocCfgBaseAddr:16 + :28 +} + +{BISTResults=0xc0010060;BIST Results + BistResults:30 + :34 +} + +{PstateCurrentLimit=0xc0010061;P-state current limit + CurPstateLimit:3 + :1 + PstateMaxVal:3 + :57 +} + +{PstateControl=0xc0010062;P-state control + PstateCmd:3 + :61 +} + +{PstateStatus=0xc0010063;P-state status + CurPstate:3 + :61 +} + +{Pstate0=0xc0010064;P-state 0 + CpuDidLSD:4 + CpuDidMSD:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate1=0xc0010065;P-state 1 + CpuDidLSD:4 + CpuDidMSD:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate2=0xc0010066;P-state 2 + CpuDidLSD:4 + CpuDidMSD:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate3=0xc0010067;P-state 3 + CpuDidLSD:4 + CpuDidMSD:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate4=0xc0010068;P-state 4 + CpuDidLSD:4 + CpuDidMSD:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate5=0xc0010069;P-state 5 + CpuDidLSD:4 + CpuDidMSD:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate6=0xc001006a;P-state 6 + CpuDidLSD:4 + CpuDidMSD:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate7=0xc001006b;P-state 7 + CpuDidLSD:4 + CpuDidMSD:5 + CpuVid:7 + :16 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{COFVIDstatus=0xc0010071;COFVID status + CurCpuDidLSD:4 + CurCpuDidMSD:5 + CurCpuVid:7 + CurPstate:3 + :1 + PstateInProgress:1 + :4 + CurNbVid:7 + StartupPstate:3 + MaxVid:7 + MinVid:7 + MainPllOpFreqIdMax:6 + :1 + CurPstateLimit:3 + :5 +} + +{CstateAddress=0xc0010073;C-state address + CstateAddr:16 + :48 +} + +{CpuWdTmrCfg=0xc0010074;CPU watchdog timer + CpuWdtEn:1 + CpuWdtTimeBase:2 + CpuWdtCountSel:4 + :57 +} + +{SMM_BASE=0xc0010111;SMM base address + SMM_BASE:32 + :32 +} + +{SMMAddr=0xc0010112;SMM TSeg base address + :17 + TSegBase:19 + :28 +} + +{SMMMask=0xc0010113;SMM Tseg mask + AValid:1 + TValid:1 + AClose:1 + TClose:1 + AMTypeIoWc:1 + TMTypeIoWc:1 + :2 + AMTypeDram:3 + :1 + TMTypeDram:3 + :2 + TSegMask:19 + :28 +} + +{VM_CR=0xc0010114;virtual machine control + dpd:1 + r_init:1 + dis_a20m:1 + Lock:1 + Svme_Disable:1 + :59 +} + +{IGNNE=0xc0010115;IGNNE + IGNNE:1 + :63 +} + +# {SMM_CTL=0xc0010116;SMM control +# smm_dismiss:1 +# smm_enter:1 +# smi_cyle:1 +# smm_exit:1 +# rsm_cycle:1 +# :59 +# } # write-only + +{VM_HSAVE_PA=0xc0010117;virtual machine host save physical address + :12 + VM_HSAVE_PA:24 + :28 +} + +# {SVMLock=0xc0010118;SVM lock key +# SvmLockKey:64 +# } # write-only + +{SMIstatus=0xc001011a;local SMI status + IoTrapSts:4 + :4 + MceRedirSts:1 + :7 + SmiSrcLvtLcy:1 + SmiSrcLvtExt:1 + :46 +} + +{OSVW_ID_Length=0xc0010140;OS visible work-around + OSVW_ID_Length:16 + :48 +} + +{OsvwStatus=0xc0010141;OS visible work-around status bits + OsvwStatusBits:64 +} + +{CPUIDFeatures=0xc0011004;CPUID features + FeaturesEdx:32 + FeaturesEcx:32 +} + +{CPUIDExtFeatures=0xc0011005;extended CPUID features + ExtFeaturesEdx:32 + ExtFeaturesEcx:32 +} + +{LS_CFG=0xc0011020;load store configuration + :28 + DisStreamSt:1 + :35 +} + +{IC_CFG=0xc0011021;instruction cache configuration + :9 + DIS_SPEC_TLB_RLD:1 + :54 +} + +{DC_CFG=0xc0011022;data cache configuration + :13 + DIS_HW_PF:1 + :50 +} + +{IbsFetchCtl=0xc0011030;IBS fetch control + IbsFetchMaxCnt:16 + IbsFetchCnt:16 + IbsFetchLat:16 + IbsFetchEn:1 + IbsFetchVal:1 + IbsFetchComp:1 + IbsIcMiss:1 + IbsPhyAddrValid:1 + IbsL1TlbPgSz:2 + IbsL1TlbMiss:1 + IbsL2TlbMiss:1 + IbsRandEn:1 + :6 +} + +{IbsFetchLinAd=0xc0011031;IBS fetch linear address + IbsFetchLinAd:64 +} + +{IbsFetchPhysAd=0xc0011032;IBS fetch physical address + IbsFetchPhysAd:36 + :28 +} + +{IbsOpCtl=0xc0011033;IBS execution control + IbsOpMaxCnt:16 + :1 + IbsOpEn:1 + IbsOpVal:1 + IbsOpCntCtl:1 + IbsOpMaxCntExt:7 + :5 + IbsOpCurCnt:20 + IbsOpCurCntExt:7 + :5 +} + +{IbsOpRip=0xc0011034;IBS Op logical address + IbsOpRip:64 +} + +{IbsOpData=0xc0011035;IBS Op data + IbsCompToRetCtr:16 + IbsTagToRetCtr:16 + IbsOpBrnResync:1 + IbsOpMispReturn:1 + IbsOpReturn:1 + IbsOpBrnTaken:1 + IbsOpBrnMisp:1 + IbsOpBrnRet:1 + IbsRipInvalid:1 + :25 +} + +{IbsOpData2=0xc0011036;IBS Op data 2 + NbIbsReqSrc:3 + :61 +} + +{IbsOpData3=0xc0011037;IBS Op data 3 + IbsLdOp:1 + IbsStOp:1 + IbsDcL1tlbMiss:1 + IbsDcL2tlbMiss:1 + IbsDcL1tlbHit2M:1 + :1 + IbsDcL2tlbHit2M:1 + IbsDcMiss:1 + IbsDcMisAcc:1 + :2 + IbsDcStToLdFwd:1 + :1 + IbsDcWcMemAcc:1 + IbsDcUcMemAcc:1 + IbsDcLockedOp:1 + IbsDcMabHit:1 + IbsDcLinAddrValid:1 + IbsDcPhyAddrValid:1 + :13 + IbsDcMissLat:16 + :16 +} + +{IbsDcLinAd=0xc0011038;IBS DC linear address + IbsDcLinAd:64 +} + +{IbsDcPhysAd=0xc0011039;IBS DC physical address + IbsDcPhysAd:36 + :28 +} + +{IbsControl=0xc001103a;IBS control + LvtOffset:4 + :4 + LvtOffsetVal:1 + :55 +} + +{IbsBranchTargetAddress=0xc001103b;IBS branch target address + IbsBrTarget:64 +} + +### Local Variables: ### +### mode:shell-script ### +### End: ###
[-] [+]	Added	x86info-1.30.tar.bz2/AMD/fam15h.regs ^
@@ -0,0 +1,2167 @@ +# Author: Andreas Herrmann <andreas.herrmann3@amd.com> +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This file contains information from: +# - "42301 Rev 3.02 - October 18, 2011, BIOS and Kernel Developer's +# Guide (BKDG) for AMD Family 15h Models 00h-0Fh Processors" + +# See scripts/createheader.py for the general format of this register +# definitions. + +{LSMCAaddr=0x0000;load-store MCA address + ADDR:64 +} # alias of MC0_ADDR + +{LSMCAstatus=0x0001;load-store MCE status + ErrorCode:16 + ErrorCodeExt:5 + :15 + Way:4 + :3 + Poison:1 + Deferred:1 + :12 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + Overflow:1 + Val:1 +} # alias of MC0_STATUS + +{TSC=0x0010;time-stamp counter + TSC:64 +} + +{APIC_BASE=0x001b;APIC base address + :8 + BSC:1 + :1 + Apicx2En:1 + ApicEn:1 + ApicBar:28 + :24 +} + +{EBL_CR_POWERON=0x002a;cluster ID + :16 + ClusterID:2 + :46 +} + +{PATCH_LEVEL=0x008b;microcode patch level (sharedC) + PATCH_LEVEL:32 + :32 +} + +{MPERF=0x00e7;max performance frequency clock count + MPERF:64 +} + +{APERF=0x00e8;actual performance frequency clock count + APERF:64 +} + +{MTRRcap=0x00fe;MTRR capabilities + MtrrCapVCnt:8 + MtrrCapFix:1 + :1 + MtrrCapWc:1 + :53 +} + +{SYSENTER_CS=0x0174;SYSENTER/SYSEXIT code segment selector + SYSENTER_CS:16 + :48 +} + +{SYSENTER_ESP=0x0175;SYSENTER/SYSEXIT stack pointer + SYSENTER_ESP:32 + :32 +} + +{SYSENTER_EIP=0x0176;SYSENTER/SYSEXIT instruction pointer + SYSENTER_EIP:32 + :32 +} + +{MCG_CAP=0x0179;global MC capabilities + Count:8 + MCG_CTL_P:1 + :55 +} + +{MCG_STAT=0x017a;global MC status + RIPV:1 + EIPV:1 + MCIP:1 + :61 +} + +{MCG_CTL=0x017b;global MC control + LS:1 + IF:1 + CU:1 + :1 + NB:1 + EX:1 + FP:1 + :57 +} + +{DBG_CTL_MSR=0x01d9;debug control + LBR:1 + BTF:1 + PB0:1 + PB1:1 + PB2:1 + PB3:1 + :58 +} + +{BR_FROM=0x01db;last branch from IP + LastBranchFromIP:64 +} + +{BR_TO=0x01dc;last branch to IP + LastBranchToIP:64 +} + +{LastExceptionFromIP=0x01dd;last exception from IP + LastIntFromIP:64 +} + +{LastExceptionToIP=0x01de;last exception to IP + LastIntToIP:64 +} + +{MTRRphysBase0=0x0200;base of variable-size MTRR (0) (sharedC) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:36 + :16 +} + +{MTRRphysMask0=0x0201;mask of variable-size MTRR (0) (sharedC) + :11 + Valid:1 + PhysMask:36 + :16 +} + +{MTRRphysBase1=0x0202;base of variable-size MTRR (1) (sharedC) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:36 + :16 +} + +{MTRRphysMask1=0x0203;mask of variable-size MTRR (1) (sharedC) + :11 + Valid:1 + PhysMask:36 + :16 +} + +{MTRRphysBase2=0x0204;base of variable-size MTRR (2) (sharedC) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:36 + :16 +} + +{MTRRphysMask2=0x0205;mask of variable-size MTRR (2) (sharedC) + :11 + Valid:1 + PhysMask:36 + :16 +} + +{MTRRphysBase3=0x0206;base of variable-size MTRR (3) (sharedC) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:36 + :16 +} + +{MTRRphysMask3=0x0207;mask of variable-size MTRR (3) (sharedC) + :11 + Valid:1 + PhysMask:36 + :16 +} + +{MTRRphysBase4=0x0208;base of variable-size MTRR (4) (sharedC) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:36 + :16 +} + +{MTRRphysMask4=0x0209;mask of variable-size MTRR (4) (sharedC) + :11 + Valid:1 + PhysMask:36 + :16 +} + +{MTRRphysBase5=0x020a;base of variable-size MTRR (5) (sharedC) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:36 + :16 +} + +{MTRRphysMask5=0x020b;mask of variable-size MTRR (5) (sharedC) + :11 + Valid:1 + PhysMask:36 + :16 +} + +{MTRRphysBase6=0x020c;base of variable-size MTRR (6) (sharedC) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:36 + :16 +} + +{MTRRphysMask6=0x020d;mask of variable-size MTRR (6) (sharedC) + :11 + Valid:1 + PhysMask:36 + :16 +} + +{MTRRphysBase7=0x020e;base of variable-size MTRR (7) (sharedC) + MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB + :9 + PhyBase:36 + :16 +} + +{MTRRphysMask7=0x020f;mask of variable-size MTRR (7) (sharedC) + :11 + Valid:1 + PhysMask:36 + :16 +} + +{MTRRfix64K_00000=0x0250;fixed range MTRR (sharedC) + 0xxxxMemType:3 + 0xxxxWrDram:1 + 0xxxxRdDram:1 + :3 + 1xxxxMemType:3 + 1xxxxWrDram:1 + 1xxxxRdDram:1 + :3 + 2xxxxMemType:3 + 2xxxxWrDram:1 + 2xxxxRdDram:1 + :3 + 3xxxxMemType:3 + 3xxxxWrDram:1 + 3xxxxRdDram:1 + :3 + 4xxxxMemType:3 + 4xxxxWrDram:1 + 4xxxxRdDram:1 + :3 + 5xxxxMemType:3 + 5xxxxWrDram:1 + 5xxxxRdDram:1 + :3 + 6xxxxMemType:3 + 6xxxxWrDram:1 + 6xxxxRdDram:1 + :3 + 7xxxxMemType:3 + 7xxxxWrDram:1 + 7xxxxRdDram:1 + :3 +} + +{MTRRfix16K_80000=0x0258;fixed range MTRR (sharedC) + 80xxxMemType:3 + 80xxxWrDram:1 + 80xxxRdDram:1 + :3 + 84xxxMemType:3 + 84xxxWrDram:1 + 84xxxRdDram:1 + :3 + 88xxxMemType:3 + 88xxxWrDram:1 + 88xxxRdDram:1 + :3 + 8CxxxMemType:3 + 8CxxxWrDram:1 + 8CxxxRdDram:1 + :3 + 90xxxMemType:3 + 90xxxWrDram:1 + 90xxxRdDram:1 + :3 + 94xxxMemType:3 + 94xxxWrDram:1 + 94xxxRdDram:1 + :3 + 98xxxMemType:3 + 98xxxWrDram:1 + 98xxxRdDram:1 + :3 + 9CxxxMemType:3 + 9CxxxWrDram:1 + 9CxxxRdDram:1 + :3 +} + +{MTRRfix16K_A0000=0x0259;fixed range MTRR (sharedC) + A0xxxMemType:3 + A0xxxWrDram:1 + A0xxxRdDram:1 + :3 + A4xxxMemType:3 + A4xxxWrDram:1 + A4xxxRdDram:1 + :3 + A8xxxMemType:3 + A8xxxWrDram:1 + A8xxxRdDram:1 + :3 + ACxxxMemType:3 + ACxxxWrDram:1 + ACxxxRdDram:1 + :3 + B0xxxMemType:3 + B0xxxWrDram:1 + B0xxxRdDram:1 + :3 + B4xxxMemType:3 + B4xxxWrDram:1 + B4xxxRdDram:1 + :3 + B8xxxMemType:3 + B8xxxWrDram:1 + B8xxxRdDram:1 + :3 + BCxxxMemType:3 + BCxxxWrDram:1 + BCxxxRdDram:1 + :3 +} + +{MTRRfix4K_C0000=0x0268;fixed range MTRR (sharedC) + C0xxxMemType:3 + C0xxxWrDram:1 + C0xxxRdDram:1 + :3 + C1xxxMemType:3 + C1xxxWrDram:1 + C1xxxRdDram:1 + :3 + C2xxxMemType:3 + C2xxxWrDram:1 + C2xxxRdDram:1 + :3 + C3xxxMemType:3 + C3xxxWrDram:1 + C3xxxRdDram:1 + :3 + C4xxxMemType:3 + C4xxxWrDram:1 + C4xxxRdDram:1 + :3 + C5xxxMemType:3 + C5xxxWrDram:1 + C5xxxRdDram:1 + :3 + C6xxxMemType:3 + C6xxxWrDram:1 + C6xxxRdDram:1 + :3 + C7xxxMemType:3 + C7xxxWrDram:1 + C7xxxRdDram:1 + :3 +} + +{MTRRfix4K_C8000=0x0269;fixed range MTRR (sharedC) + C8xxxMemType:3 + C8xxxWrDram:1 + C8xxxRdDram:1 + :3 + C9xxxMemType:3 + C9xxxWrDram:1 + C9xxxRdDram:1 + :3 + CAxxxMemType:3 + CAxxxWrDram:1 + CAxxxRdDram:1 + :3 + CBxxxMemType:3 + CBxxxWrDram:1 + CBxxxRdDram:1 + :3 + CCxxxMemType:3 + CCxxxWrDram:1 + CCxxxRdDram:1 + :3 + CDxxxMemType:3 + CDxxxWrDram:1 + CDxxxRdDram:1 + :3 + CExxxMemType:3 + CExxxWrDram:1 + CExxxRdDram:1 + :3 + CFxxxMemType:3 + CFxxxWrDram:1 + CFxxxRdDram:1 + :3 +} + +{MTRRfix4K_D0000=0x026a;fixed range MTRR (sharedC) + D0xxxMemType:3 + D0xxxWrDram:1 + D0xxxRdDram:1 + :3 + D1xxxMemType:3 + D1xxxWrDram:1 + D1xxxRdDram:1 + :3 + D2xxxMemType:3 + D2xxxWrDram:1 + D2xxxRdDram:1 + :3 + D3xxxMemType:3 + D3xxxWrDram:1 + D3xxxRdDram:1 + :3 + D4xxxMemType:3 + D4xxxWrDram:1 + D4xxxRdDram:1 + :3 + D5xxxMemType:3 + D5xxxWrDram:1 + D5xxxRdDram:1 + :3 + D6xxxMemType:3 + D6xxxWrDram:1 + D6xxxRdDram:1 + :3 + D7xxxMemType:3 + D7xxxWrDram:1 + D7xxxRdDram:1 + :3 +} + +{MTRRfix4K_D8000=0x026b;fixed range MTRR (sharedC) + D8xxxMemType:3 + D8xxxWrDram:1 + D8xxxRdDram:1 + :3 + D9xxxMemType:3 + D9xxxWrDram:1 + D9xxxRdDram:1 + :3 + DAxxxMemType:3 + DAxxxWrDram:1 + DAxxxRdDram:1 + :3 + DBxxxMemType:3 + DBxxxWrDram:1 + DBxxxRdDram:1 + :3 + DCxxxMemType:3 + DCxxxWrDram:1 + DCxxxRdDram:1 + :3 + DDxxxMemType:3 + DDxxxWrDram:1 + DDxxxRdDram:1 + :3 + DExxxMemType:3 + DExxxWrDram:1 + DExxxRdDram:1 + :3 + DFxxxMemType:3 + DFxxxWrDram:1 + DFxxxRdDram:1 + :3 +} + +{MTRRfix4K_E0000=0x026c;fixed range MTRR (sharedC) + E0xxxMemType:3 + E0xxxWrDram:1 + E0xxxRdDram:1 + :3 + E1xxxMemType:3 + E1xxxWrDram:1 + E1xxxRdDram:1 + :3 + E2xxxMemType:3 + E2xxxWrDram:1 + E2xxxRdDram:1 + :3 + E3xxxMemType:3 + E3xxxWrDram:1 + E3xxxRdDram:1 + :3 + E4xxxMemType:3 + E4xxxWrDram:1 + E4xxxRdDram:1 + :3 + E5xxxMemType:3 + E5xxxWrDram:1 + E5xxxRdDram:1 + :3 + E6xxxMemType:3 + E6xxxWrDram:1 + E6xxxRdDram:1 + :3 + E7xxxMemType:3 + E7xxxWrDram:1 + E7xxxRdDram:1 + :3 +} + +{MTRRfix4K_E8000=0x026d;fixed range MTRR (sharedC) + E8xxxMemType:3 + E8xxxWrDram:1 + E8xxxRdDram:1 + :3 + E9xxxMemType:3 + E9xxxWrDram:1 + E9xxxRdDram:1 + :3 + EAxxxMemType:3 + EAxxxWrDram:1 + EAxxxRdDram:1 + :3 + EBxxxMemType:3 + EBxxxWrDram:1 + EBxxxRdDram:1 + :3 + ECxxxMemType:3 + ECxxxWrDram:1 + ECxxxRdDram:1 + :3 + EDxxxMemType:3 + EDxxxWrDram:1 + EDxxxRdDram:1 + :3 + EExxxMemType:3 + EExxxWrDram:1 + EExxxRdDram:1 + :3 + EFxxxMemType:3 + EFxxxWrDram:1 + EFxxxRdDram:1 + :3 +} + +{MTRRfix4K_F0000=0x026e;fixed range MTRR (sharedC) + F0xxxMemType:3 + F0xxxWrDram:1 + F0xxxRdDram:1 + :3 + F1xxxMemType:3 + F1xxxWrDram:1 + F1xxxRdDram:1 + :3 + F2xxxMemType:3 + F2xxxWrDram:1 + F2xxxRdDram:1 + :3 + F3xxxMemType:3 + F3xxxWrDram:1 + F3xxxRdDram:1 + :3 + F4xxxMemType:3 + F4xxxWrDram:1 + F4xxxRdDram:1 + :3 + F5xxxMemType:3 + F5xxxWrDram:1 + F5xxxRdDram:1 + :3 + F6xxxMemType:3 + F6xxxWrDram:1 + F6xxxRdDram:1 + :3 + F7xxxMemType:3 + F7xxxWrDram:1 + F7xxxRdDram:1 + :3 +} + +{MTRRfix4K_F8000=0x026f;fixed range MTRR (sharedC) + F8xxxMemType:3 + F8xxxWrDram:1 + F8xxxRdDram:1 + :3 + F9xxxMemType:3 + F9xxxWrDram:1 + F9xxxRdDram:1 + :3 + FAxxxMemType:3 + FAxxxWrDram:1 + FAxxxRdDram:1 + :3 + FBxxxMemType:3 + FBxxxWrDram:1 + FBxxxRdDram:1 + :3 + FCxxxMemType:3 + FCxxxWrDram:1 + FCxxxRdDram:1 + :3 + FDxxxMemType:3 + FDxxxWrDram:1 + FDxxxRdDram:1 + :3 + FExxxMemType:3 + FExxxWrDram:1 + FExxxRdDram:1 + :3 + FFxxxMemType:3 + FFxxxWrDram:1 + FFxxxRdDram:1 + :3 +} + +{PAT=0x0277;page attribute table + PA0MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA1MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA2MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA3MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA4MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA5MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA6MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 + PA7MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- + :5 +} + +{MTRRdefType=0x02ff;MTRR default memory type (sharedC) + MemType:8 + :2 + MtrrDefTypeFixEn:1 + MtrrDefTypeEn:1 + :52 +} + +{MC0_CTL=0x0400;load store MC control + TagP:1 + TLBP:1 + DatP:1 + LQP:1 + SQP:1 + SCBP:1 + LineFillPoison:1 + SRDE:1 + IntErrType2:1 + IntErrType1:1 + :54 +} + +{MC0_STATUS=0x0401;load store MC status + ErrorCode:16 + ErrorCodeExt:5 + :15 + Way:4 + :3 + Poison:1 + Deferred:1 + :12 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + Overflow:1 + Val:1 +} + +{MC0_ADDR=0x0402;load store MC address + ADDR:64 +} + +{MC0_MISC=0x0403;load store MC miscellaneous + :24 + BlkPtr:8 + ErrCnt:12 + :4 + Ovrflw:1 + :2 + CntEn:1 + :10 + CntP:1 + Valid:1 +} + +{MC1_CTL=0x0404;instruction fetch MC control (sharedC) + :2 + IDP:1 + IMTP:1 + ISTP:1 + L2TP:1 + L1TP:1 + LineFillPoison:1 + :1 + SRDE:1 + :2 + PFBP:1 + PQP:1 + :1 + BSRP:1 + DEPRP:1 + DEUOPQP:1 + DEIBP:1 + DPDBE:1 + DFIFOE:1 + L2TLBM:1 + L1TLBM:1 + IVP:1 + :40 +} + +{MC1_STATUS=0x0405;instruction fetch MC status + ErrorCode:16 + ErrorCodeExt:5 + :15 + Way:4 + :3 + Poison:1 + Deferred:1 + :12 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + Overflow:1 + Val:1 +} + +{MC1_ADDR=0x0406;instruction fetch MC address + ADDR:64 +} + +{MC1_MISC=0x0407;instruction fetch MC miscellaneous + :24 + BlkPtr:8 + ErrCnt:12 + :4 + Ovrflw:1 + :2 + CntEn:1 + :10 + CntP:1 + Valid:1 +} + +{MC2_CTL=0x0408;combined unit MC control (sharedC) + L2TagMultiHit:1 + VbData:1 + WcbData:1 + WccData:1 + WccAddr:1 + PrqData:1 + PrqAddr:1 + FillData:1 + PrbAddr:1 + XabAddr:1 + L2Prefetch:1 + L2TlbData:1 + L2Tag:1 + RdData:1 + L2TlbPoison:1 + :49 +} + +{MC2_STATUS=0x0409;combined unit MC status + ErrorCode:16 + ErrorCodeExt:5 + :3 + Syndrome:4 + :8 + Way:4 + :3 + Poison:1 + Deferred:1 + UECC:1 + CECC:1 + Syndrome:8 + :2 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + Overflow:1 + Val:1 +} + +{MC2_ADDR=0x040a;combined unit MC address register + ADDR:64 +} + +{MC2_MISC=0x040b;combined unit MC miscellaneous + :24 + BlkPtr:8 + ErrCnt:12 + :4 + Ovrflw:1 + :2 + CntEn:1 + :10 + CntP:1 + Valid:1 +} + +{MC3_CTL=0x040c;reserved + :64 +} + +{MC3_STATUS=0x040d;reserved + :64 +} + +{MC3_ADDR=0x040e;reserved + :64 +} + +{MC3_MISC=0x040f;reserved + :64 +} + +{MC4_CTL=0x0410;northbridge MC control + CECCEn:1 + UECCEn:1 + CrcErrEn:3 + SyncPktEn:3 + MstrAbrtEn:1 + TgtAbrtEn:1 + GartTblWkEn:1 + AtomicRMWEn:1 + WDTRptEn:1 + :1 + L3ArrayCorEn:1 + L3ArrayUCEn:1 + ProtEn:1 + HtDataEn:1 + DramParEn:1 + RtryHtEn:4 + CrcErrEn:1 + SyncPktEn:1 + McaUsPwDatErrEn:1 + NbArrayParEn:1 + TblWlkDatErrEn:1 + :3 + McaCpuDatErrEn:1 + :32 +} + +{MC4_STATUS=0x0411;northbridge MC status + ErrorCode:16 + ErrorCodeExt:5 + :3 + Syndrome:8 + ErrCoreId:4 + Link:4 + Scrub:1 + SubLink:1 + McaStatSubCache:2 + :1 + UECC:1 + CECC:1 + Syndrome:8 + :1 + ErrCoreIdVal:1 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + Overflow:1 + Val:1 +} + +{MC4_ADDR=0x0412;northbridge MC address + :1 + ErrAddr:47 + :16 +} + +{MC4_MISC0=0x0413;northbridge MC misc (DRAM Thresholding) (0) + :24 + BlkPtr:8 + ErrCnt:12 + :4 + Ovrflw:1 + IntType:2 + CntEn:1 + LvtOffset:4 + :5 + Locked:1 + CntP:1 + Valid:1 +} + +{MC5_CTL=0x0414;execution unit MC control + :1 + PICWAK:1 + PLDAG:1 + PLDEX:1 + IDF:1 + RETDISP:1 + MAP:1 + EX0PRF:1 + EX1PRF:1 + AG0PRF:1 + AG1PRF:1 + FRF:1 + DE:1 + :51 +} + +{MC5_STATUS=0x0415;execution unit MC status + ErrorCode:16 + ErrorCodeExt:5 + :36 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + Overflow:1 + Val:1 +} + +{MC5_ADDR=0x0416;execution unit MC address + ADDR:64 +} + +{MC5_MISC=0x0417;execution unit MC miscellaneous + :24 + BlkPtr:8 + ErrCnt:12 + :4 + Ovrflw:1 + :2 + CntEn:1 + :10 + CntP:1 + Valid:1 +} + +{MC6_CTL=0x0418;floating point unit MC control (sharedC) + PRF:1 + FreeList:1 + Sched:1 + :1 + RetireQ:1 + SRF:1 + :58 +} + +{MC6_STATUS=0x0419;floating point unit MC status + ErrorCode:16 + ErrorCodeExt:5 + :36 + PCC:1 + AddrV:1 + MiscV:1 + En:1 + UC:1 + Overflow:1 + Val:1 +} + +{MC6_ADDR=0x041a;floating point unit MC address + :64 +} + +{MC6_MISC=0x041b;floating point unit MC miscellaneous + :64 +} + +{EFER=0xc0000080;extended feature enable + SYSCALL:1 + :7 + LME:1 + :1 + LMA:1 + NXE:1 + SVME:1 + LMSLE:1 + FFXSE:1 + :49 +} + +{STAR=0xc0000081;SYSCALL target address + Target:32 + SysCallSel:16 + SysRetSel:16 +} + +{STAR64=0xc0000082;long mode SYSCALL target address + LSTAR:64 +} + +{STARCOMPAT=0xc0000083;compat mode SYSCALL target address + CSTAR:64 +} + +{SYSCALL_FLAG_MASK=0xc0000084;SYSCALL flag mask + MASK:32 + :32 +} + +{FS_BASE=0xc0000100;FS base + FS_BASE:64 +} + +{GS_BASE=0xc0000101;GS base + GS_BASE:64 +} + +{KernelGSbase=0xc0000102;kernel GS base + KernelGSBase:64 +} + +{TSC_AUX=0xc0000103;auxiliary time stamp counter data + TscAux:32 + :32 +} + +{TscRateMsr=0xc0000104;time stamp counter ratio + TscRateMsrFrac:32 + TscRateMsrInt:32 +} + +{LWP_CFG=0xc0000105;lightweight profile configuration + :1 + LwpVAL:1 + LwpIRE:1 + LwpBRE:1 + LwpDME:1 + LwpCNH:1 + LwpRNH:1 + :24 + LwpInt:1 + LwpCoreId:8 + LwpVector:8 + :16 +} + +{LWP_CBADDR=0xc0000106;leightweight profile control block address + :6 + LwpCbAddr:58 +} + +{MC4_MISC1=0xc0000408;northbridge MC misc (Link Thresholding) (1) + :24 + BlkPtr:8 + ErrCnt:12 + :4 + Ovrflw:1 + IntType:2 + CntEn:1 + LvtOffset:4 + :5 + Locked:1 + CntP:1 + Valid:1 +} + +{MC4_MISC2=0xc0000409;northbridge MC misc (L3 Thresholding) (2) + :24 + BlkPtr:8 + ErrCnt:12 + :4 + Ovrflw:1 + IntType:2 + CntEn:1 + LvtOffset:4 + :5 + Locked:1 + CntP:1 + Valid:1 +} + +{MC4_MISC3=0xc000040a;reserved + :64 +} + +{LEG_PERF_CTL0=0xc0010000;performance event select (0) + EventSelect:8 + UnitMask:8 + OsUserMode:2 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + HostGuestOnly:2 + :22 +} # alias of PERF_CTL0 + +{LEG_PERF_CTL1=0xc0010001;performance event select (1) + EventSelect:8 + UnitMask:8 + OsUserMode:2 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + HostGuestOnly:2 + :22 +} # alias of PERF_CTL1 + +{LEG_PERF_CTL2=0xc0010002;performance event select (2) + EventSelect:8 + UnitMask:8 + OsUserMode:2 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + HostGuestOnly:2 + :22 +} # alias of PERF_CTL2 + +{LEG_PERF_CTL3=0xc0010003;performance event select (3) + EventSelect:8 + UnitMask:8 + OsUserMode:2 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + HostGuestOnly:2 + :22 +} # alias of PERF_CTL3 + +{LEG_PERF_CTR0=0xc0010004;performance event counter (0) + CTR:48 + :16 +} # alias of PERF_CTR0 + +{LEG_PERF_CTR1=0xc0010005;performance event counter (1) + CTR:48 + :16 +} # alias of PERF_CTR1 + +{LEG_PERF_CTR2=0xc0010006;performance event counter (2) + CTR:48 + :16 +} # alias of PERF_CTR2 + +{LEG_PERF_CTR3=0xc0010007;performance event counter (3) + CTR:48 + :16 +} # alias of PERF_CTR3 + +{SYS_CFG=0xc0010010;system configuration (sharedC) + :16 + ChxToDirtyDis:1 + :1 + MtrrFixDramEn:1 + MtrrFixDramModeEn:1 + MtrrVarDramEn:1 + MtrrTom2En:1 + Tom2ForceMemTypeWB:1 + :41 +} + +{HWCR=0xc0010015;hardware configuration + SmmLock:1 + :2 + TlbCacheDis:1 + INVDWBINVD:1 + :3 + IgnneEm:1 + MonMwaitDis:1 + MonMwaitUserEn:1 + :1 + HltXSpCycEn:1 + SmiSpCycDis:1 + RsmSpCycDis:1 + :2 + Wrap32Dis:1 + McStatusWrEn:1 + :1 + IoCfgGpFault:1 + :2 + ForceRdWrSzPrb:1 + TscFreqSel:1 + CpbDis:1 + EffFreqCntMwait:1 + :37 +} + +{IORR_BASE0=0xc0010016;base of variable I/O range (0) (sharedC) + :3 + WrMem:1 + RdMem:1 + :7 + PhyBase:36 + :16 +} + +{IORR_MASK0=0xc0010017;mask of variable I/O range (0) (sharedC) + :11 + Valid:1 + PhyMask:36 + :16 +} + +{IORR_BASE1=0xc0010018;base of variable I/O range (1) (sharedC) + :3 + WrMem:1 + RdMem:1 + :7 + PhyBase:36 + :16 +} + +{IORR_MASK1=0xc0010019;mask of variable I/O range (1) (sharedC) + :11 + Valid:1 + PhyMask:36 + :16 +} + +{TOP_MEM=0xc001001a;top of memory address (sharedC) + :23 + TOM:25 + :16 +} + +{TOM2=0xc001001d;second top of memory address (sharedC) + :23 + TOM2:25 + :16 +} + +{NB_CFG=0xc001001f;northbridge configuration + :9 + DisRefUseFreeBuf:1 + DisXdsBypass:1 + :20 + DisCohLdtCfg:1 + :4 + DisDatMsk:1 + :8 + DisUsSysMgtReqToNcHt:1 + EnableCf8ExtCfg:1 + :3 + DisOrderRdRsp:1 + :3 + InitApicIdCpuIdLo:1 + :9 +} + +{MCEredirection=0xc0010022;MCE redirection + RedirVector:8 + RedirVecEn:1 + RedirSmiEn:1 + :54 +} + +{ProcessorNameString0=0xc0010030;processor name string (0) (sharedNC) + CpuNameString:64 +} + +{ProcessorNameString1=0xc0010031;processor name string (1) (sharedNC) + CpuNameString:64 +} + +{ProcessorNameString2=0xc0010032;processor name string (2) (sharedNC) + CpuNameString:64 +} + +{ProcessorNameString3=0xc0010033;processor name string (3) (sharedNC) + CpuNameString:64 +} + +{ProcessorNameString4=0xc0010034;processor name string (4) (sharedNC) + CpuNameString:64 +} + +{ProcessorNameString5=0xc0010035;processor name string (5) (sharedNC) + CpuNameString:64 +} + +{HTC=0xc001003e;hardware thermal control + HtcEn:1 + :3 + HtcAct:1 + HtcActSts:1 + PslApicHiEn:1 + PslApicLoEn:1 + :8 + HtcTmpLmt:7 + HtcSlewSel:1 + HtcHystLmt:4 + HtcPstateLimit:3 + :33 +} + +{MC0_CTL_MASK=0xc0010044;load store MC control mask + TagP:1 + TLBP:1 + DatP:1 + LQP:1 + SQP:1 + SCBP:1 + LineFillPoison:1 + SRDE:1 + IntErrType2:1 + :55 +} + +{MC1_CTL_MASK=0xc0010045;instruction fetch MC control mask (sharedC) + :2 + IDP:1 + IMTP:1 + ISTP:1 + L2TP:1 + L1TP:1 + LineFillPoison:1 + :1 + SRDE:1 + :2 + PFBP:1 + PQP:1 + :1 + BSRP:1 + DEPRP:1 + DEUOPQP:1 + DEIBP:1 + DPDBE:1 + DFIFOE:1 + L2TLBM:1 + L1TLBM:1 + IVP:1 + :40 +} + +{MC2_CTL_MASK=0xc0010046;bus unit MC control mask (sharedC) + L2TagMultiHit:1 + VbData:1 + WcbData:1 + WccData:1 + WccAddr:1 + PrqData:1 + PrqAddr:1 + FillData:1 + PrbAddr:1 + XabAddr:1 + L2Prefetch:1 + L2TlbData:1 + L2Tag:1 + RdData:1 + L2TlbPoison:1 + :49 +} + +{MC3_CTL_MASK=0xc0010047;reserved + :64 +} + +{MC4_CTL_MASK=0xc0010048;northbridge MC control mask + CECCEn:1 + UECCEn:1 + CrcErrEn:3 + SyncPktEn:3 + MstrAbrtEn:1 + TgtAbrtEn:1 + GartTblWkEn:1 + AtomicRMWEn:1 + WDTRptEn:1 + :1 + L3ArrayCorEn:1 + L3ArrayUCEn:1 + ProtEn:1 + HtDataEn:1 + DramParEn:1 + RtryHtEn:4 + CrcErrEn:1 + SyncPktEn:1 + McaUsPwDatErrEn:1 + NbArrayParEn:1 + TblWlkDatErrEn:1 + :3 + McaCpuDatErrEn:1 + :32 +} + +{MC5_CTL_MASK=0xc0010049;execution unit MC control mask + :1 + PICWAK:1 + PLDAG:1 + PLDEX:1 + IDF:1 + RETDISP:1 + MAP:1 + EX0PRF:1 + EX1PRF:1 + AG0PRF:1 + AG1PRF:1 + FRF:1 + DE:1 + :51 +} + +{MC6_CTL_MASK=0xc001004a;floating point unit MC control mask (sharedC) + PRF:1 + FreeList:1 + Sched:1 + :1 + RetireQ:1 + SRF:1 + :58 +} + +{SMI_ON_IO_TRAP_0=0xc0010050;IO trap address (0) (sharedNC) + SmiAddr:32 + SmiMask:24 + :5 + ConfigSmi:1 + SmiOnWrEn:1 + SmiOnRdEn:1 +} + +{SMI_ON_IO_TRAP_1=0xc0010051;IO trap address (1) (sharedNC) + SmiAddr:32 + SmiMask:24 + :5 + ConfigSmi:1 + SmiOnWrEn:1 + SmiOnRdEn:1 +} + +{SMI_ON_IO_TRAP_2=0xc0010052;IO trap address (2) (sharedNC) + SmiAddr:32 + SmiMask:24 + :5 + ConfigSmi:1 + SmiOnWrEn:1 + SmiOnRdEn:1 +} + +{SMI_ON_IO_TRAP_3=0xc0010053;IO trap address (3) (sharedNC) + SmiAddr:32 + SmiMask:24 + :5 + ConfigSmi:1 + SmiOnWrEn:1 + SmiOnRdEn:1 +} + +{SMI_ON_IO_TRAP_CTL_STS=0xc0010054;IO trap control (sharedNC) + :1 + SmiEn_0:1 + :1 + SmiEn_1:1 + :1 + SmiEn_2:1 + :1 + SmiEn_3:1 + :7 + IoTrapEn:1 + :48 +} + +{IntPendingMessage=0xc0010055;interrupt pending (sharedNC) + IOMsgAddr:16 + IOMsgData:8 + IntrPndMsgDis:1 + IntrPndMsg:1 + IORd:1 + :2 + BmStsClrOnHaltEn:1 + :34 +} + +{SmiTriggerIoCycle=0xc0010056;SMI trigger IO cycle + IoPortAddress:16 + IoData:8 + :1 + IoCycleEn:1 + IoRd:1 + :37 +} + +{MmioConfigBase=0xc0010058;MMIO configuration base address + Enable:1 + :1 + SegBusRange:4;0=1;1=2;2=4;3=8;4=16;5=32;6=64;7=128;8=256 + :14 + MmiocCfgBaseAddr:28 + :16 +} + +{BistResults=0xc0010060;BIST results + :64 +} + +{PstateCurrentLimit=0xc0010061;P-state current limit (sharedC) + CurPstateLimit:3 + :1 + PstateMaxVal:3 + :57 +} + +{PstateControl=0xc0010062;P-state control + PstateCmd:3 + :61 +} + +{PstateStatus=0xc0010063;P-state status (sharedC) + CurPstate:3 + :61 +} + +{Pstate0=0xc0010064;P-state 0 (sharedC) + CpuFid:6 + CpuDid:3 + CpuVid:7 + :6 + NbPstate:1 + :9 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate1=0xc0010065;P-state 1 (sharedC) + CpuFid:6 + CpuDid:3 + CpuVid:7 + :6 + NbPstate:1 + :9 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate2=0xc0010066;P-state 2 (sharedC) + CpuFid:6 + CpuDid:3 + CpuVid:7 + :6 + NbPstate:1 + :9 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate3=0xc0010067;P-state 3 (sharedC) + CpuFid:6 + CpuDid:3 + CpuVid:7 + :6 + NbPstate:1 + :9 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate4=0xc0010068;P-state 4 (sharedC) + CpuFid:6 + CpuDid:3 + CpuVid:7 + :6 + NbPstate:1 + :9 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate5=0xc0010069;P-state 5 (sharedC) + CpuFid:6 + CpuDid:3 + CpuVid:7 + :6 + NbPstate:1 + :9 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate6=0xc001006a;P-state 6 (sharedC) + CpuFid:6 + CpuDid:3 + CpuVid:7 + :6 + NbPstate:1 + :9 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{Pstate7=0xc001006b;P-state 7 (sharedC) + CpuFid:6 + CpuDid:3 + CpuVid:7 + :6 + NbPstate:1 + :9 + IddValue:8 + IddDiv:2 + :21 + PstateEn:1 +} + +{COFVIDcontrol=0xc0010070;COFVID control + CpuFid:6 + CpuDid:3 + CpuVid:7 + PstateId:3 + :3 + NbPstate:1 + :1 + NbVid:8 + :32 +} + +{COFVIDstatus=0xc0010071;COFVID status + CurCpuFid:6 + CurCpuDid:3 + CurCpuVid:7 + CurPstate:3 + :4 + NbPstateDis:1 + :1 + CurNbVid:7 + StartupPstate:3 + MaxVid:7 + MinVid:7 + MaxCpuCof:6 + :1 + CurPstateLimit:3 + MaxNbCof:5 +} + +{CstateAddress=0xc0010073;C-state address + CstateAddr:16 + :48 +} + +{SMM_BASE=0xc0010111;SMM base address + SMM_BASE:32 + :32 +} + +{SMMAddr=0xc0010112;SMM TSeg base address + :17 + TSegBase:31 + :16 +} + +{SMMMask=0xc0010113;SMM Tseg mask + AValid:1 + TValid:1 + AClose:1 + TClose:1 + AMTypeIoWc:1 + TMTypeIoWc:1 + :2 + AMTypeDram:3 + :1 + TMTypeDram:3 + :2 + TSegMask:31 + :16 +} + +{VM_CR=0xc0010114;virtual machine control + dpd:1 + InterceptInit:1 + DisA20m:1 + Lock:1 + SvmeDisable:1 + :59 +} + +{IGNNE=0xc0010115;IGNNE + IGNNE:1 + :63 +} + +{VM_HSAVE_PA=0xc0010117;virtual machine host save physical address + :12 + VM_HSAVE_PA:36 + :16 +} + +{SMIstatus=0xc001011a;local SMI status + IoTrapSts:4 + :4 + MceRedirSts:1 + :1 + IntPendSmiSts:1 + :5 + SmiSrcLvtLcy:1 + SmiSrcLvtExt:1 + SmiSrcThrCntDram:1 + SmiSrcThrCntHt:1 + SmiSrcThrCntL3:1 + :1 + SmiSrcOnLineSpare:1 + :41 +} + +{OSVW_ID_Length=0xc0010140;OS visible work-around + OSVW_ID_Length:16 + :48 +} + +{OsvwStatus=0xc0010141;OS visible work-around status bits + OsvwStatusBits:64 +} + +{PERF_CTL0=0xc0010200;performance event select (0) + EventSelect:8 + UnitMask:8 + OsUserMode:2 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + HostGuestOnly:2 + :22 +} + +{PERF_CTR0=0xc0010201;performance event counter (0) + CTR:48 + :16 +} + +{PERF_CTL1=0xc0010202;performance event select (1) + EventSelect:8 + UnitMask:8 + OsUserMode:2 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + HostGuestOnly:2 + :22 +} + +{PERF_CTR1=0xc0010203;performance event counter (1) + CTR:48 + :16 +} + +{PERF_CTL2=0xc0010204;performance event select (2) + EventSelect:8 + UnitMask:8 + OsUserMode:2 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + HostGuestOnly:2 + :22 +} + +{PERF_CTR2=0xc0010205;performance event counter (2) + CTR:48 + :16 +} + +{PERF_CTL3=0xc0010206;performance event select (3) + EventSelect:8 + UnitMask:8 + OsUserMode:2 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + HostGuestOnly:2 + :22 +} + +{PERF_CTR3=0xc0010207;performance event counter (3) + CTR:48 + :16 +} + +{PERF_CTL4=0xc0010208;performance event select (4) + EventSelect:8 + UnitMask:8 + OsUserMode:2 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + HostGuestOnly:2 + :22 +} + +{PERF_CTR4=0xc0010209;performance event counter (4) + CTR:48 + :16 +} + +{PERF_CTL5=0xc001020a;performance event select (5) + EventSelect:8 + UnitMask:8 + OsUserMode:2 + Edge:1 + :1 + Int:1 + :1 + En:1 + Inv:1 + CntMask:8 + EventSelect:4 + :4 + HostGuestOnly:2 + :22 +} + +{PERF_CTR5=0xc001020b;performance event counter (5) + CTR:48 + :16 +} + +{NB_PERF_CTL0=0xc0010240;northbridge performance event select (0) + EventSelect:8 + UnitMask:8 + :4 + Int:1 + :1 + En:1 + :9 + EventSelect:4 + :28 +} + +{NB_PERF_CTR0=0xc0010241;northbridge performance event counter (0) + CTR:48 + :16 +} + +{NB_PERF_CTL1=0xc0010242;northbridge performance event select (1) + EventSelect:8 + UnitMask:8 + :4 + Int:1 + :1 + En:1 + :9 + EventSelect:4 + :28 +} + +{NB_PERF_CTR1=0xc0010243;northbridge performance event counter (1) + CTR:48 + :16 +} + +{NB_PERF_CTL2=0xc0010244;northbridge performance event select (2) + EventSelect:8 + UnitMask:8 + :4 + Int:1 + :1 + En:1 + :9 + EventSelect:4 + :28 +} + +{NB_PERF_CTR2=0xc0010245;northbridge performance event counter (2) + CTR:48 + :16 +} + +{NB_PERF_CTL3=0xc0010246;northbridge performance event select (3) + EventSelect:8 + UnitMask:8 + :4 + Int:1 + :1 + En:1 + :9 + EventSelect:4 + :28 +} + +{NB_PERF_CTR3=0xc0010247;northbridge performance event counter (3) + CTR:48 + :16 +} + +{CPUIDPmFeatures=0xc0011003;thermal and power management CPUID features + FeaturesEcx:32 + :32 +} + +{CPUIDFeatures=0xc0011004;CPUID features + FeaturesEdx:32 + FeaturesEcx:32 +} + +{CPUIDExtFeatures=0xc0011005;extended CPUID features + ExtFeaturesEdx:32 + ExtFeaturesEcx:32 +} + +{LS_CFG=0xc0011020;load store configuration + :28 + DIS_SS:1 + :35 +} + +{IC_CFG=0xc0011021;instruction cache configuration (sharedC) + :9 + DIS_SPEC_TLB_RLD:1 + :54 +} + +{DC_CFG=0xc0011022;data cache configuration + :4 + DIS_SPEC_TLB_RLD:1 + :8 + DIS_HW_PF:1 + :50 +} + +{CU_CFG=0xc0011023;combined unit configuration (sharedC) + :10 + DcacheAgressivePriority:1 + :8 + L2FirstLockedWay:4 + L2WayLock:1 + :40 +} + +{FP_CFG=0xc0011028;floating point configuration (sharedC) + :16 + DiDtMode:1 + :1 + DiDtCfg0:5 + :2 + DiDtCfg2:2 + DiDtCfg1:8 + :29 +} + +{DE_CFG=0xc0011029;decode configuration (sharedC) + :10 + ResyncPredSingleDispDis:1 + :53 +} + +{CU_CFG2=0xc001102A;combined unit configuration 2 (sharedC) + :6 + ThrottleNbInterface:2 + :2 + VicResyncChkEn:1 + :25 + ThrottleNbInterface:2 + :4 + ProbeFilterSupEn:1 + :7 + RdMmExtCfgQwEn:1 + :13 +} + +{CU_CFG3=0xc001102B;combined unit configuration 3 (sharedC) + :42 + PwcDisableWalkerSharing:1 + :6 + CombineCr0Cd:1 + AsidIncrScaleFactor:1 + AsidDecrScaleFactor:2 + :11 +} + +{EX_CFG=0xc001102C;execution unit configuration + :64 +} + +{IbsFetchCtl=0xc0011030;IBS fetch control + IbsFetchMaxCnt:16 + IbsFetchCnt:16 + IbsFetchLat:16 + IbsFetchEn:1 + IbsFetchVal:1 + IbsFetchComp:1 + IbsIcMiss:1 + IbsPhyAddrValid:1 + IbsL1TlbPgSz:2 + IbsL1TlbMiss:1 + IbsL2TlbMiss:1 + IbsRandEn:1 + :6 +} + +{IbsFetchLinAd=0xc0011031;IBS fetch linear address + IbsFetchLinAd:64 +} + +{IbsFetchPhysAd=0xc0011032;IBS fetch physical address + IbsFetchPhysAd:64 +} + +{IbsOpCtl=0xc0011033;IBS execution control + IbsOpMaxCnt:16 + :1 + IbsOpEn:1 + IbsOpVal:1 + IbsOpCntCtl:1 + IbsOpMaxCnt:7 + :5 + IbsOpCurCnt:27 + :5 +} + +{IbsOpRip=0xc0011034;IBS Op logical address + IbsOpRip:64 +} + +{IbsOpData=0xc0011035;IBS Op data + IbsCompToRetCtr:16 + IbsTagToRetCtr:16 + IbsOpBrnResync:1 + IbsOpMispReturn:1 + IbsOpReturn:1 + IbsOpBrnTaken:1 + IbsOpBrnMisp:1 + IbsOpBrnRet:1 + IbsRipInvalid:1 + :25 +} + +{IbsOpData2=0xc0011036;IBS Op data 2 + NbIbsReqSrc:3 + :1 + NbIbsReqDstNode:1 + NbIbsReqCacheHitSt:1 + :58 +} + +{IbsOpData3=0xc0011037;IBS Op data 3 + IbsLdOp:1 + IbsStOp:1 + IbsDcL1tlbMiss:1 + IbsDcL2tlbMiss:1 + IbsDcL1tlbHit2M:1 + IbsDcL1tlbHit1G:1 + IbsDcL2tlbHit2M:1 + IbsDcMiss:1 + IbsDcMisAcc:1 + IbsDcLdBnkCon:1 + :1 + IbsDcStToLdFwd:1 + IbsDcStToLdCan:1 + IbsDcWcMemAcc:1 + IbsDcUcMemAcc:1 + IbsDcLockedOp:1 + IbsDcMabHit:1 + IbsDcLinAddrValid:1 + IbsDcPhyAddrValid:1 + IbsDcL2tlbHit1G:1 + :12 + IbsDcMissLat:16 + :16 +} + +{IbsDcLinAd=0xc0011038;IBS DC linear address + IbsDcLinAd:64 +} + +{IbsDcPhysAd=0xc0011039;IBS DC physical address + IbsDcPhysAd:64 +} + +{IbsControl=0xc001103a;IBS control + LvtOffset:4 + :4 + LvtOffsetVal:1 + :55 +} + +{IbsBranchTargetAddress=0xc001103b;IBS branch target address + IbsBrTarget:64 +} + +### Local Variables: ### +### mode:shell-script ### +### End: ###
[-] [+]	Changed	x86info-1.30.tar.bz2/AMD/identify.c ^
@@ -91,26 +91,51 @@ cpuid(c->number, 0x80000001, &eax, &ebx, &ecx, &edx); pkg_id = (ebx >> 28) & 0xf; - switch (pkg_id) { - case 0: - c->connector = CONN_SOCKET_F_R2; - break; - case 1: - c->connector = CONN_SOCKET_AM3; - break; - case 2: - c->connector = CONN_SOCKET_S1G3; - break; - case 3: - c->connector = CONN_SOCKET_G34; - break; - case 4: - c->connector = CONN_SOCKET_ASB2; - break; - case 5: - c->connector = CONN_SOCKET_C32; - default: - c->connector = 0; + if ((family(c) == 0x10) \|\| (family(c) == 0x11) \|\| (family(c) == 0x15)) { + switch (pkg_id) { + case 0: + c->connector = CONN_SOCKET_F_R2; + break; + case 1: + c->connector = CONN_SOCKET_AM3; + break; + case 2: + c->connector = CONN_SOCKET_S1G3; + break; + case 3: + c->connector = CONN_SOCKET_G34; + break; + case 4: + c->connector = CONN_SOCKET_ASB2; + break; + case 5: + c->connector = CONN_SOCKET_C32; + break; + default: + c->connector = 0; + } + } else if(family(c) == 0x12) { + switch (pkg_id) { + case 0: + c->connector = CONN_SOCKET_FP1; + break; + case 1: + c->connector = CONN_SOCKET_FS1; + break; + case 2: + c->connector = CONN_SOCKET_FM1; + break; + default: + c->connector = 0; + } + } else if (family(c) == 0x14) { + switch (pkg_id) { + case 0: + c->connector = CONN_SOCKET_FT1; + break; + default: + c->connector = 0; + } } } @@ -143,6 +168,49 @@ set_connector(c); } +static void set_fam12h_revinfo(int id, struct cpudata c) +{ + const char p; + + p = get_fam12h_revision_name(id); + if(p) + snprintf(c->name, CPU_NAME_LEN, + "AMD A/E2-Series Processor (%s)", p); + else + snprintf(c->name, CPU_NAME_LEN, "Unknown CPU"); + + set_connector(c); +} + +static void set_fam14h_revinfo(int id, struct cpudata c) +{ + const char p; + + p = get_fam14h_revision_name(id); + if (p) + snprintf(c->name, CPU_NAME_LEN, + "AMD C/E/G-Series Processor (%s)", p); + else + snprintf(c->name, CPU_NAME_LEN, "Unknown CPU"); + + + set_connector(c); +} + +static void set_fam15h_revinfo(int id, struct cpudata c) +{ + const char p; + + p = get_fam15h_revision_name(id); + if (p) + snprintf(c->name, CPU_NAME_LEN, + "AMD FX Series Processor (%s)", p); + else + snprintf(c->name, CPU_NAME_LEN, "Unknown CPU"); + set_connector(c); +} + + static void do_assoc(unsigned long assoc) { switch (assoc & 0xff) { @@ -294,12 +362,12 @@ printf("\n\t"); printf("lines per tag=%u\t", (ecx >> 8) & 0x0f); printf("line size=%u bytes.\n", ecx & 0xff); - if (family(cpu) == 0x10) { + if ((family(cpu) == 0x10) \|\| (family(cpu) == 0x15)) { printf("L3 (shared) cache:\n\t"); if (!(edx >> 18)) printf("none/disabled\n"); else { - /* family 0x10 has shared L3 cache / + / shared L3 cache / printf("Size: %uKb\t", (edx >> 18) 512); do_l2assoc((edx >> 12) & 0x0f); @@ -369,8 +437,8 @@ if (cpu->cpuid_level < 1) return; + cpuid(cpu->number, 0x00000001, &eax, &ebx, &ecx, &edx); if (cpu->family == 0xf) { - cpuid(cpu->number, 0x00000001, &eax, &ebx, &ecx, &edx); cpu->emodel = (eax >> 16) & 0xf; cpu->efamily= (eax >> 20) & 0xff; } else { @@ -378,14 +446,32 @@ cpu->efamily = 0; } - if (family(cpu) == 0xf) { - set_k8_revinfo(eax, cpu); - return; - } else if (family(cpu) == 0x10) { - set_fam10h_revinfo(eax, cpu); - return; - } else if (family(cpu) == 0x11) { - set_fam11h_revinfo(eax, cpu); + if (family(cpu) >= 0xf) { + switch family(cpu) { + case 0xf: + set_k8_revinfo(eax, cpu); + break; + case 0x10: + set_fam10h_revinfo(eax, cpu); + break; + case 0x11: + set_fam11h_revinfo(eax, cpu); + break; + case 0x12: + set_fam12h_revinfo(eax, cpu); + break; + case 0x14: + set_fam14h_revinfo(eax, cpu); + break; + case 0x15: + set_fam15h_revinfo(eax, cpu); + break; + default: + printf("Unknown CPU family: 0x%x\n", + family(cpu)); + break; + } + return; }
[-] [+]	Changed	x86info-1.30.tar.bz2/AMD/powernow.c ^
@@ -132,6 +132,33 @@ return t; } +static int get_main_pll_fid(void) +{ + struct pci_filter filter_nb_misc = { -1, -1, -1, -1, 0x1022, 0x1703}; + struct pci_access pacc; + struct pci_dev z = NULL; + u8 val; + + pacc = pci_alloc(); + pci_init(pacc); + pci_scan_bus(pacc); + + for (z=pacc->devices; z; z=z->next) { + if (pci_filter_match(&filter_nb_misc, z)) + break; + } + + val = 0; + if (z) { + val = pci_read_byte(z, 0xd4); + val &= 0x3f; + } + + pci_cleanup(pacc); + + return val; +} + static int get_cof(int family, union msr_pstate pstate) { int t; @@ -141,16 +168,57 @@ t = 0x10; fid = pstate.bits.fid; - if (family == 0x11) + if ((family == 0x10) \|\| (family == 0x15)) + goto out; + + if (family == 0x11) { t = 0x8; + goto out; + } + if (family == 0x12) { + int f, d; + t = 0x10; + fid = (pstate.val >> 4) & 0x1f; + + switch (did) { + case 0: + goto out; + case 2: + did = 1; goto out; + case 4: + did = 2; goto out; + case 6: + did = 3; goto out; + case 8: + did = 4; goto out; + case 1: + f = 2; d = 3; break; + case 3: + f = 1; d = 3; break; + case 5: + f = 1; d = 6; break; + case 7: + f = 1; d = 12; break; + default: + printf("Invalid divisor ID: %d\n", did); + return 0; + } + return (100 * (fid + t) * f / d); + } + if (family == 0x14) { + fid = get_main_pll_fid(); //from PCI + return (((fid + 0x10) 100) 4 / did); + } + + out: return ((100 * (fid + t)) >> did); } static int get_num_boost_states(void) { struct pci_filter filter_nb_link = { -1, -1, -1, -1, 0x1022, 0}; - int dev_ids[3] = {0x1204}; + int dev_ids[3] = {0x1204, 0x1604, 0x1704}; struct pci_access pacc; struct pci_dev z = NULL; u8 val; @@ -176,7 +244,7 @@ printf("Boosting enabled\n"); else printf("Boosting disabled\n"); - val = (val >> 2) & 1; + val = (val >> 2) & 7; printf("Number of boost states: %d\n", val); } @@ -218,13 +286,15 @@ i); return; } - if (i < boost_states) + if (i < boost_states) { printf("Pstate-Pb%d: %dMHz (boost state)\n", i, get_cof(fam, pstate)); - else + } else if (pstate.bits.en) { + /* show information only if pstate is enabled */ printf("Pstate-P%d: %dMHz%s\n", i - boost_states, get_cof(fam, pstate), (i == pscur) ? " (current)" : ""); + } } printf("\n"); }
[-] [+]	Changed	x86info-1.30.tar.bz2/AMD/revision.h ^
@@ -147,4 +147,20 @@ }; get_name(fam11h_revision, int, fam11h_revisions); +struct id_string fam12h_revisions[] = { + {0x0300f10, "LN1-B0"}, +}; +get_name(fam12h_revision, int, fam12h_revisions); + +struct id_string fam14h_revisions[] = { + {0x00500f10, "ON-B0"}, +}; +get_name(fam14h_revision, int, fam14h_revisions); + +struct id_string fam15h_revisions[] = { + + {0x00600f12, "OR-B2"}, +}; +get_name(fam15h_revision, int, fam15h_revisions); + #endif /* _amd_revision_h_ */
[-] [+]	Changed	x86info-1.30.tar.bz2/Intel/identify-family6-extended.c ^
@@ -289,10 +289,18 @@ add_to_cpuname("Core i7 (Nehalem) [Gulftown/Westmere-EP]"); break; + case 0x2d: + add_to_cpuname("Core i7 (Sandybridge) [Romely-EP]"); + break; + case 0x2e: add_to_cpuname("Core i7 (Nehalem) [Beckton]"); break; + case 0x2f: + add_to_cpuname("Core i7 (Nehalem-EX) [Westmere] [Xeon E7]"); + break; + default: add_to_cpuname("Unknown model. "); }
[-] [+]	Changed	x86info-1.30.tar.bz2/Intel/info.c ^
@@ -131,8 +131,8 @@ if (show_eblcr) { if (cpu->family == 6 && cpu->model >= 3) { unsigned long long eblcr; - read_msr(cpu->number, 0x2A, &eblcr); - interpret_eblcr(eblcr); + if (read_msr(cpu->number, 0x2A, &eblcr) == 1) + interpret_eblcr(eblcr); } }
[-] [+]	Changed	x86info-1.30.tar.bz2/Makefile ^
@@ -1,4 +1,4 @@ -VERSION=1.29 +VERSION=1.30 CFLAGS = -g -O2 -Werror -Wall -Wshadow -Wextra -Wmissing-declarations -Wdeclaration-after-statement -Wredundant-decls LDFLAGS = -Wl,-z,relro,-z,now @@ -9,7 +9,8 @@ all: x86info test lsmsr -LSMSR_TMP_HEADERS=AMD/k8.h AMD/fam10h.h AMD/fam11h.h generic_msr.h +LSMSR_TMP_HEADERS=AMD/k8.h AMD/fam10h.h AMD/fam11h.h AMD/fam12h.h \ + AMD/fam14h.h AMD/fam15h.h generic_msr.h %.h: %.regs scripts/createheader.py python scripts/createheader.py $< `basename $< .regs` >$@ @@ -23,6 +24,8 @@ lsmsr.c: $(LSMSR_TMP_HEADERS) +lsmsr.o: $(LSMSR_TMP_HEADERS) + lsmsr: $(LSMSR_TMP_HEADERS) $(LSMSR_OBJS) $(CC) $(CFLAGS) $(LDFLAGS) -o lsmsr $(LSMSR_OBJS)
[-] [+]	Changed	x86info-1.30.tar.bz2/README ^
@@ -1,4 +1,4 @@ -x86info v1.29 http://www.codemonkey.org.uk/projects/x86info +x86info v1.30 http://www.codemonkey.org.uk/projects/x86info Dave Jones <davej@redhat.com> Somewhere in the mists of time, there was a program by Phil Karn (KA9Q)
[-] [+]	Changed	x86info-1.30.tar.bz2/TODO ^
@@ -1,5 +1,6 @@ higher priority stuff --------------------- +- handle error better in mptable. Propagate values up. - feature flag handling code could use more cleanup. - Would be nice to have something similar to the kernels CPU_HAS macros too. - Make intel cache sizing use cpuid(4) where present.
[-] [+]	Changed	x86info-1.30.tar.bz2/connector.c ^
@@ -39,6 +39,10 @@ {CONN_SOCKET_G34, "Socket G34"}, {CONN_SOCKET_ASB2, "Socket ASB2"}, {CONN_SOCKET_C32, "Socket C32"}, + {CONN_SOCKET_FP1, "Socket FP1"}, + {CONN_SOCKET_FS1, "Socket FS1"}, + {CONN_SOCKET_FM1, "Socket FM1"}, + {CONN_SOCKET_FT1, "Socket FT1"}, /* Intel specific sockets */ {CONN_SOCKET_57B, "Socket 5/7 (320 Pin PGA)"}, {CONN_MOBILE_7, "Mobile Module (320 Lead TCP)"},
[-] [+]	Changed	x86info-1.30.tar.bz2/features.c ^
@@ -372,8 +372,8 @@ "3dnowPref", "osvw", "ibs", "xop", "skinit", "wdt", NULL, "lwp", "fma4", NULL, NULL, "NodeId", - NULL, "tbm", "TopoExt", NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL + NULL, "tbm", "TopoExt", "PerfCtrExtCore", + "PerfCtrExtNB", NULL, NULL, NULL, NULL, NULL, NULL, NULL }; const char centaur_cap_extended_ecx_flags[] = { @@ -469,7 +469,7 @@ died = sigsetjmp(out, 1); if (!died) - asm volatile("nopl 0(%eax)"); + asm volatile(".byte 0x0f,0x1f,0x00 / nopl 0(%eax) */"); printf("Long NOPs supported: %s\n", died ? "no" : "yes"); }
[-] [+]	Changed	x86info-1.30.tar.bz2/lsmsr.c ^
@@ -29,6 +29,9 @@ #include "AMD/k8.h" #include "AMD/fam10h.h" #include "AMD/fam11h.h" +#include "AMD/fam12h.h" +#include "AMD/fam14h.h" +#include "AMD/fam15h.h" #include "generic_msr.h" /* Todos: @@ -284,6 +287,15 @@ case 0x11: g.msr_table = fam11h_spec; break; + case 0x12: + g.msr_table = fam12h_spec; + break; + case 0x14: + g.msr_table = fam14h_spec; + break; + case 0x15: + g.msr_table = fam15h_spec; + break; default: g.msr_table = generic_msr_spec; } @@ -304,6 +316,8 @@ return 0; } +struct reg_spec unknown_msr = {0, "unknown", "(at your own risk)", NULL, NULL}; + #define OPT_MAX 32 int main(int argc, char *argv[]) { @@ -360,7 +374,12 @@ } } - if((optind > -1) && argv[optind]) { + if (argc < 2) { + usage(); + goto out; + } + + if ((optind > -1) && argv[optind]) { if ((argc - optind) != 1) usage(); if (strlen(argv[optind]) >= OPT_MAX) { @@ -391,8 +410,10 @@ reg = get_reg_spec(g.reg, g.msr_table); if (!reg) { fflush(stdout); - fprintf(stderr, "error: unknown MSR %x\n", g.reg); - goto out; + fprintf(stderr, "warning: unknown MSR %x\n", g.reg); + g.verbosity = 0; + unknown_msr.address = g.reg; + reg = &unknown_msr; } if (_show_msr(reg)) goto out;
[-] [+]	Changed	x86info-1.30.tar.bz2/mptable.c ^
@@ -140,12 +140,13 @@ } } -static void readEntry(void* entry, int size) +static int readEntry(void* entry, int size) { if (read(pfd, entry, size) != size) { perror("readEntry"); - exit(EXIT_FAILURE); + return -1; } + return 0; } static int readType(void) @@ -171,7 +172,10 @@ int t, family, model; /* read it into local memory / - readEntry(&entry, sizeof(entry)); + if (readEntry(&entry, sizeof(entry)) < 0) { + printf("Error reading processor entry\n"); + exit(EXIT_FAILURE); + } / count it / ++ncpu; @@ -216,7 +220,10 @@ / read in cth structure / seekEntry(paddr); - readEntry(&cth, sizeof(cth)); + if(readEntry(&cth, sizeof(cth))) { + printf("error reading MP Config table header structure\n"); + exit(EXIT_FAILURE); + } totalSize = cth.base_table_length - sizeof(struct MPCTH); count = cth.entry_count; @@ -260,11 +267,23 @@ / search Extended Bios Data Area, if present / seekEntry((vm_offset_t)EBDA_POINTER); - readEntry(&segment, 2); + if (readEntry(&segment, 2)) { + printf("error reading EBDA pointer\n"); + exit(EXIT_FAILURE); + } + if (debug) + printf("\nEBDA points to: %x\n", segment); + if (segment) { / search EBDA / target = (vm_offset_t)segment << 4; seekEntry(target); - readEntry(buffer, ONE_KBYTE); + if (debug) + printf("EBDA segment ptr: %lx\n", target); + if (readEntry(buffer, ONE_KBYTE)) { + printf("error reading 1K from %p\n", (void )target); + exit(EXIT_FAILURE); + } + for (x = 0; x < ONE_KBYTE / 4; NEXT(x)) { if (!strncmp((char )&buffer[x], MP_SIG, 4)) { @@ -276,11 +295,19 @@ / read CMOS for real top of mem / seekEntry((vm_offset_t)TOPOFMEM_POINTER); - readEntry(&segment, 2); + if (readEntry(&segment, 2)) { + printf("error reading CMOS for real top of mem (%p)\n", (void ) TOPOFMEM_POINTER); + exit(EXIT_FAILURE); + } + --segment; /* less ONE_KBYTE / target = segment 1024; seekEntry(target); - readEntry(buffer, ONE_KBYTE); + if (readEntry(buffer, ONE_KBYTE)) { + printf("error reading 1KB from %p\n", (void )target); + exit(EXIT_FAILURE); + } + for (x = 0; x < ONE_KBYTE/4; NEXT(x)) { if (!strncmp((char )&buffer[x], MP_SIG, 4)) { @@ -293,7 +320,10 @@ if (target != (DEFAULT_TOPOFMEM - 1024)) { target = (DEFAULT_TOPOFMEM - 1024); seekEntry(target); - readEntry(buffer, ONE_KBYTE); + if (readEntry(buffer, ONE_KBYTE)) { + printf("error reading DEFAULT_TOPOFMEM - 1024 from %p\n", (void ) target); + exit(EXIT_FAILURE); + } for (x = 0; x < ONE_KBYTE/4; NEXT(x)) { if (!strncmp((char )&buffer[x], MP_SIG, 4)) { @@ -305,7 +335,11 @@ /* search the BIOS / seekEntry(BIOS_BASE); - readEntry(buffer, BIOS_SIZE); + if (readEntry(buffer, BIOS_SIZE)) { + printf("error reading BIOS_BASE from %p\n", (void )BIOS_BASE); + exit(EXIT_FAILURE); + } + for (x = 0; x < BIOS_SIZE/4; NEXT(x)) { if (!strncmp((char )&buffer[x], MP_SIG, 4)) { @@ -316,7 +350,11 @@ / search the extended BIOS / seekEntry(BIOS_BASE2); - readEntry(buffer, BIOS_SIZE); + if (readEntry(buffer, BIOS_SIZE)) { + printf("error reading BIOS_BASE2 from %p\n", (void )BIOS_BASE2); + exit(EXIT_FAILURE); + } + for (x = 0; x < BIOS_SIZE/4; NEXT(x)) { if (!strncmp((char )&buffer[x], MP_SIG, 4)) { @@ -328,7 +366,11 @@ / search additional memory / target = GROPE_AREA1; seekEntry(target); - readEntry(buffer, GROPE_SIZE); + if (readEntry(buffer, GROPE_SIZE)) { + printf("error reading GROPE_AREA1 from %p\n", (void )target); + exit(EXIT_FAILURE); + } + for (x = 0; x < GROPE_SIZE/4; NEXT(x)) { if (!strncmp((char )&buffer[x], MP_SIG, 4)) { @@ -339,7 +381,11 @@ target = GROPE_AREA2; seekEntry(target); - readEntry(buffer, GROPE_SIZE); + if (readEntry(buffer, GROPE_SIZE)) { + printf("error reading GROPE_AREA2 from %p\n", (void )target); + exit(EXIT_FAILURE); + } + for (x = 0; x < GROPE_SIZE/4; NEXT(x)) { if (!strncmp((char )&buffer[x], MP_SIG, 4)) { @@ -372,7 +418,11 @@ / read in mpfps structure/ seekEntry(paddr); - readEntry(&mpfps, sizeof(mpfps_t)); + if (readEntry(&mpfps, sizeof(mpfps_t))) { + printf("error reading mpfpsfrom %p\n", (void )paddr); + exit(EXIT_FAILURE); + } + /* check whether an MP config table exists / if (!mpfps.mpfb1) @@ -401,7 +451,11 @@ / read in mpfps structure/ seekEntry(paddr); - readEntry(&mpfps, sizeof(mpfps_t)); + if (readEntry(&mpfps, sizeof(mpfps_t))) { + printf("error reading mpfps from %p\n", (void )paddr); + exit(EXIT_FAILURE); + } + /* parse an MP config table if it exists */ if (!mpfps.mpfb1)
[-] [+]	Changed	x86info-1.30.tar.bz2/rdmsr.c ^
@@ -70,10 +70,10 @@ { char cpuname[16]; unsigned char buffer[8]; - unsigned long lo, hi; + unsigned long long lo, hi; int fh; static int nodriver=0; - unsigned long ptr = (unsigned long ) buffer; + unsigned int ptr = (unsigned int ) buffer; if (nodriver==1) return 0; @@ -101,10 +101,9 @@ return 0; } - lo = (ptr)++; - hi = (ptr); - val = hi; - val = (val<<32) \| lo; + lo = ptr; + hi = (++ptr); + val = (hi << 32) \| lo; } if (close(fh) == -1) { perror("close");
[-] [+]	Changed	x86info-1.30.tar.bz2/scripts/createheader.py ^
@@ -39,27 +39,27 @@ progname=os.path.basename(sys.argv[0]) if len(sys.argv) < 3: - print progname + ": invalid number of argumenst" - print "\nUSAGE:" - print progname + " <input file> <struct name>" - print "\nEXAMPLE:" - print progname + " k8regs.txt k8 >k8.h" + print(progname + ": invalid number of argumenst") + print("\nUSAGE:") + print(progname + " <input file> <struct name>") + print("\nEXAMPLE:") + print(progname + " k8regs.txt k8 >k8.h") sys.exit(1) f=open(sys.argv[1]) family=sys.argv[2] -print \ +print(\ "/\n"\ " Licensed under the terms of the GNU GENERAL PUBLIC LICENSE version 2.\n"\ " * See file COPYING for details.\n"\ -" /\n" -print "#ifndef " + family + "_h" -print "#define " + family + "_h\n" +" /\n") +print("#ifndef " + family + "_h") +print("#define " + family + "_h\n") if (re.search("/", sys.argv[1])): - print "#include \"../msr.h\"\n" + print("#include \"../msr.h\"\n") else: - print "#include \"msr.h\"\n" + print("#include \"msr.h\"\n") struct=[] for line in f: if (re.search("^#",line)): @@ -88,8 +88,8 @@ str1 += "," + e[1] str1 += ",0);" str2 += ");" - print str1 - print str2 + print(str1) + print(str2) str3 = "_SPEC(" + reg_addr + ", " + reg_name + ", " if reg_desc != "": str3 += "\"" + reg_desc + "\", " @@ -104,10 +104,10 @@ fwidth=field[1].strip() spec.append([fname, fwidth]) -print "\nstruct reg_spec " + family + "_spec [] = {" +print("\nstruct reg_spec " + family + "_spec [] = {") for i in struct: - print "\t" + i + "," -print " {0, NULL, NULL, NULL, NULL}," -print "};\n" -print "#endif /* " + family + "_h /" + print("\t" + i + ",") +print(" {0, NULL, NULL, NULL, NULL},") +print("};\n") +print("#endif / " + family + "_h */") f.close()
[-] [+]	Changed	x86info-1.30.tar.bz2/topology.c ^
@@ -114,4 +114,6 @@ if (cpu->flags_edx & X86_FEATURE_HT && cpu->num_siblings > 1) printf(" with hyper-threading (%d threads per core)", cpu->num_siblings); + + free(sockets); }
[-] [+]	Changed	x86info-1.30.tar.bz2/x86info.c ^
@@ -169,7 +169,7 @@ parse_command_line(argc, argv); - printf("x86info v1.29. Dave Jones 2001-2011\n"); + printf("x86info v1.30. Dave Jones 2001-2011\n"); printf("Feedback to <davej@redhat.com>.\n\n"); if ((HaveCPUID()) == 0) {
[-] [+]	Changed	x86info-1.30.tar.bz2/x86info.h ^
@@ -58,6 +58,10 @@ CONN_SOCKET_G34, CONN_SOCKET_ASB2, CONN_SOCKET_C32, + CONN_SOCKET_FP1, + CONN_SOCKET_FS1, + CONN_SOCKET_FM1, + CONN_SOCKET_FT1, }; #define CPU_NAME_LEN 80

Changes of Revision 13