|
[-]
[+]
|
Added |
memtest86+.changes
|
|
|
|
[-]
[+]
|
Changed |
memtest86+.spec
^
|
|
|
|
[-]
[+]
|
Deleted |
fix-overflows.diff
^
|
| @@ -1,341 +0,0 @@
-diff -urp memtest86+-2.01.mm/io.h memtest86+-2.01/io.h
---- memtest86+-2.01.mm/io.h 2008-02-21 12:26:05.000000000 +0100
-+++ memtest86+-2.01/io.h 2008-04-30 12:32:34.787275000 +0200
-@@ -31,7 +31,7 @@
- */
-
- #define __OUT1(s,x) \
--extern inline void __out##s(unsigned x value, unsigned short port) {
-+static inline void __out##s(unsigned x value, unsigned short port) {
-
- #define __OUT2(s,s1,s2) \
- __asm__ __volatile__ ("out" #s " %" s1 "0,%" s2 "1"
-@@ -43,7 +43,7 @@ __OUT1(s##_p,x) __OUT2(s,s1,"w") : : "a"
- __OUT1(s##c_p,x) __OUT2(s,s1,"") : : "a" (value), "id" (port)); SLOW_DOWN_IO; }
-
- #define __IN1(s) \
--extern inline RETURN_TYPE __in##s(unsigned short port) { RETURN_TYPE _v;
-+static inline RETURN_TYPE __in##s(unsigned short port) { RETURN_TYPE _v;
-
- #define __IN2(s,s1,s2) \
- __asm__ __volatile__ ("in" #s " %" s2 "1,%" s1 "0"
-@@ -55,7 +55,7 @@ __IN1(s##_p) __IN2(s,s1,"w") : "=a" (_v)
- __IN1(s##c_p) __IN2(s,s1,"") : "=a" (_v) : "id" (port) ,##i ); SLOW_DOWN_IO; return _v; }
-
- #define __OUTS(s) \
--extern inline void outs##s(unsigned short port, const void * addr, unsigned long count) \
-+static inline void outs##s(unsigned short port, const void * addr, unsigned long count) \
- { __asm__ __volatile__ ("cld ; rep ; outs" #s \
- : "=S" (addr), "=c" (count) : "d" (port),"0" (addr),"1" (count)); }
-
-diff -urp memtest86+-2.01.mm/test.c memtest86+-2.01/test.c
---- memtest86+-2.01.mm/test.c 2008-02-21 12:26:05.000000000 +0100
-+++ memtest86+-2.01/test.c 2008-04-30 14:15:56.666389000 +0200
-@@ -25,6 +25,22 @@ void poll_errors();
-
- int ecount = 0;
-
-+static inline volatile ulong * sat_add(volatile ulong *ptr, ulong i, volatile ulong *end)
-+{
-+ if ((ulong)ptr + i * sizeof(*ptr) > (ulong)ptr)
-+ return ptr + i;
-+ else
-+ return end;
-+}
-+
-+static inline volatile ulong * sat_sub(volatile ulong *ptr, ulong i, volatile ulong *start)
-+{
-+ if ((ulong)ptr > i * sizeof(*ptr))
-+ return ptr - i;
-+ else
-+ return start;
-+}
-+
- static inline ulong roundup(ulong value, ulong mask)
- {
- return (value + mask) & ~mask;
-@@ -150,11 +166,7 @@ void addr_tst2()
- done = 0;
- do {
- /* Check for overflow */
-- if (pe + SPINSZ > pe) {
-- pe += SPINSZ;
-- } else {
-- pe = end;
-- }
-+ pe = sat_add(pe, SPINSZ, end);
- if (pe >= end) {
- pe = end;
- done++;
-@@ -194,11 +206,7 @@ void addr_tst2()
- done = 0;
- do {
- /* Check for overflow */
-- if (pe + SPINSZ > pe) {
-- pe += SPINSZ;
-- } else {
-- pe = end;
-- }
-+ pe = sat_add(pe, SPINSZ, end);
- if (pe >= end) {
- pe = end;
- done++;
-@@ -280,11 +288,7 @@ void movinvr()
- done = 0;
- do {
- /* Check for overflow */
-- if (pe + SPINSZ > pe) {
-- pe += SPINSZ;
-- } else {
-- pe = end;
-- }
-+ pe = sat_add(pe, SPINSZ, end);
- if (pe >= end) {
- pe = end;
- done++;
-@@ -331,11 +335,7 @@ void movinvr()
- done = 0;
- do {
- /* Check for overflow */
-- if (pe + SPINSZ > pe) {
-- pe += SPINSZ;
-- } else {
-- pe = end;
-- }
-+ pe = sat_add(pe, SPINSZ, end);
- if (pe >= end) {
- pe = end;
- done++;
-@@ -419,7 +419,8 @@ void movinv1(int iter, ulong p1, ulong p
- hprint(LINE_PAT, COL_PAT, p1);
-
- /* Initialize memory with the initial pattern. */
-- for (j=0; j<segs; j++) {
-+ for (j=0; j<segs; j++)
-+ {
- start = v->map[j].start;
- end = v->map[j].end;
- pe = start;
-@@ -427,11 +428,7 @@ void movinv1(int iter, ulong p1, ulong p
- done = 0;
- do {
- /* Check for overflow */
-- if (pe + SPINSZ > pe) {
-- pe += SPINSZ;
-- } else {
-- pe = end;
-- }
-+ pe = sat_add(pe, SPINSZ, end);
- if (pe >= end) {
- pe = end;
- done++;
-@@ -440,17 +437,19 @@ void movinv1(int iter, ulong p1, ulong p
- if (p == pe ) {
- break;
- }
--/* Original C code replaced with hand tuned assembly code
-- * for (; p < pe; p++) {
-- * *p = p1;
-- * }
-- */
-+/* Original C code replaced with hand tuned assembly code */
-+#if 0
-+ for (; p < pe; p++) {
-+ *p = p1;
-+ }
-+#else
- asm __volatile__ (
- "rep\n\t" \
- "stosl\n\t"
- : "=D" (p)
- : "c" (len), "0" (p), "a" (p1)
- );
-+#endif
- do_tick();
- BAILR
- } while (!done);
-@@ -460,7 +459,8 @@ void movinv1(int iter, ulong p1, ulong p
- * write the complement for each memory location. Test from bottom
- * up and then from the top down. */
- for (i=0; i<iter; i++) {
-- for (j=0; j<segs; j++) {
-+ for (j=0; j<segs; j++)
-+ {
- start = v->map[j].start;
- end = v->map[j].end;
- pe = start;
-@@ -468,11 +468,7 @@ void movinv1(int iter, ulong p1, ulong p
- done = 0;
- do {
- /* Check for overflow */
-- if (pe + SPINSZ > pe) {
-- pe += SPINSZ;
-- } else {
-- pe = end;
-- }
-+ pe = sat_add(pe, SPINSZ, end);
- if (pe >= end) {
- pe = end;
- done++;
-@@ -480,14 +476,16 @@ void movinv1(int iter, ulong p1, ulong p
- if (p == pe ) {
- break;
- }
--/* Original C code replaced with hand tuned assembly code
-- * for (; p < pe; p++) {
-- * if ((bad=*p) != p1) {
-- * error((ulong*)p, p1, bad);
-- * }
-- * *p = p2;
-- * }
-- */
-+/* Original C code replaced with hand tuned assembly code */
-+#if 0
-+ for (; p < pe; p++) {
-+ ulong bad;
-+ if ((bad=*p) != p1) {
-+ error((ulong*)p, p1, bad);
-+ }
-+ *p = p2;
|
|
[-]
[+]
|
Deleted |
include-gnuhash
^
|
| @@ -1,10 +0,0 @@
---- memtest86+-1.70/memtest_shared.lds 2007-02-19 16:00:35.000000000 +0100
-+++ memtest86+-1.70/memtest_shared.lds.fixed 2007-02-19 15:55:24.000000000 +0100
-@@ -19,6 +19,7 @@
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .hash : { *(.hash) }
-+ .gnu.hash : { *(.gnu.hash) }
- .dynamic : { *(.dynamic) }
-
- .rel.text : { *(.rel.text .rel.text.*) }
|
|
|
Deleted |
memtest86+-2.01.tar.gz
^
|
|
|
Deleted |
memtest86+-2.10.tar.gz
^
|
|
|
Deleted |
memtest86+-2.11.tar.gz
^
|
|
|
Deleted |
memtest86+-4.00.tar.gz
^
|
|
|
Deleted |
memtest86+-4.10.tar.gz
^
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/FAQ
^
|
| @@ -304,7 +304,7 @@
- When I run install.bat it doesn't write anything to floppy.
- You most likely have unpacked the memtest+-1.xx.floppy.zip file into a
+ You most likely have unpacked the memtest+-2.xx.floppy.zip file into a
folder with a long pathname and/or containing + and - signs. It seems
rawrite doesn't like that. Just move the files you unpacked to a directory
like c:\memtest and execure it from there.
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/Makefile
^
|
| @@ -1,4 +1,4 @@
-# Makefile for MemTest-86
+# Makefile for MemTest86+
#
# Author: Chris Brady
# Created: January 1, 1996
@@ -8,80 +8,23 @@
#
FDISK=/dev/fd0
+AS=as -32
CC=gcc
-#
-# gcc compiler options, these settings should suffice
-#
-CCFLAGS=-Wall -m32 -march=i486 -Os -fomit-frame-pointer -fno-builtin -ffreestanding
-AS=as -32
+CFLAGS= -Wall -march=i486 -m32 -O2 -fomit-frame-pointer -fno-builtin -ffreestanding -fPIC -fno-stack-protector
-OBJS= head.o reloc.o main.o test.o init.o lib.o patn.o screen_buffer.o config.o linuxbios.o memsize.o pci.o controller.o extra.o random.o dmi.o
+OBJS= head.o reloc.o main.o test.o init.o lib.o patn.o screen_buffer.o \
+ config.o linuxbios.o memsize.o pci.o controller.o random.o spd.o \
+ error.o dmi.o cpuid.o
all: memtest.bin memtest
-reloc.o: reloc.c
- $(CC) -c -m32 -march=i486 -fPIC -Wall -g -O2 -fno-strict-aliasing reloc.c
-
-test.o: test.c test.h defs.h config.h
- $(CC) -c $(CCFLAGS) test.c
-
-main.o: main.c test.h defs.h
- $(CC) -c $(CCFLAGS) -fPIC main.c
-
-init.o: init.c test.h defs.h io.h config.h controller.h pci.h
- $(CC) -c $(CCFLAGS) -fPIC init.c
-
-linuxbios.o: linuxbios.c test.h linuxbios_tables.h defs.h config.h
- $(CC) -c $(CCFLAGS) -fPIC linuxbios.c
-
-memsize.o: memsize.c test.h defs.h config.h
- $(CC) -c $(CCFLAGS) -fPIC memsize.c
-
-lib.o: lib.c test.h defs.h io.h screen_buffer.h serial.h config.h
- $(CC) -c $(CCFLAGS) -fPIC lib.c
-
-screen_buffer.o: screen_buffer.c screen_buffer.h test.h config.h
- $(CC) -c $(CCFLAGS) -fPIC screen_buffer.c
-
-random.o: random.c
- $(CC) -c $(CCFLAGS) -fPIC random.c
-
-patn.o: patn.c
- $(CC) -c $(CCFLAGS) -fPIC patn.c
-
-config.o: config.c test.h controller.h screen_buffer.h
- $(CC) -c $(CCFLAGS) -fPIC config.c
-
-pci.o: pci.c pci.h io.h
- $(CC) -c $(CCFLAGS) -fPIC pci.c
-
-controller.o: controller.c defs.h config.h test.h pci.h controller.h
- $(CC) -c $(CCFLAGS) -fPIC controller.c
-
-extra.o: config.c test.h screen_buffer.h extra.h
- $(CC) -c $(CCFLAGS) -fPIC extra.c
-
-controller.s: controller.c defs.h config.h test.h pci.h controller.h
- $(CC) -S $(CCFLAGS) -fPIC controller.c
-
-head.s: head.S
- $(CC) -E -m32 -traditional $< -o $@
-
-head.o: head.s
- $(AS) -o $@ $<
-dmi.o: dmi.c test.h
- $(CC) -c $(CCFLAGS) -fPIC dmi.c
-
-makedefs: makedefs.c defs.h
- $(CC) $(CCFLAGS) makedefs.c -o $@
-
-
# Link it statically once so I know I don't have undefined
# symbols and then link it dynamically so I have full
# relocation information
memtest_shared: $(OBJS) memtest_shared.lds Makefile
- $(LD) --warn-constructors --warn-common -static -T memtest_shared.lds -o $@ $(OBJS) && \
+ $(LD) --warn-constructors --warn-common -static -T memtest_shared.lds \
+ -o $@ $(OBJS) && \
$(LD) -shared -Bsymbolic -T memtest_shared.lds -o $@ $(OBJS)
memtest_shared.bin: memtest_shared
@@ -90,34 +33,42 @@
memtest: memtest_shared.bin memtest.lds
$(LD) -s -T memtest.lds -b binary memtest_shared.bin -o $@
-bootsect.s: bootsect.S defs.h
+head.s: head.S config.h defs.h test.h
$(CC) -E -traditional $< -o $@
-bootsect.o: bootsect.s
- $(AS) -o $@ $<
-
-bootsect: bootsect.o
- $(LD) -Ttext 0x00 -s --oformat binary -e _main --just-symbols=memtest_shared.o -o $@ $<
+bootsect.s: bootsect.S config.h defs.h
+ $(CC) -E -traditional $< -o $@
setup.s: setup.S config.h defs.h
$(CC) -E -traditional $< -o $@
-setup.o: setup.s
- $(AS) -o $@ $<
+memtest.bin: memtest_shared.bin bootsect.o setup.o memtest.bin.lds
+ $(LD) -T memtest.bin.lds bootsect.o setup.o -b binary \
+ memtest_shared.bin -o memtest.bin
+reloc.o: reloc.c
+ $(CC) -c $(CFLAGS) -fno-strict-aliasing reloc.c
-memtest.bin: memtest_shared.bin bootsect.o setup.o memtest.bin.lds
- $(LD) -T memtest.bin.lds bootsect.o setup.o -b binary memtest_shared.bin -o memtest.bin
+test.o: test.c
+ $(CC) -c -Wall -march=i486 -m32 -Os -fomit-frame-pointer -fno-builtin -ffreestanding test.c
clean:
- rm -f *.o *.s memtest.bin bootsect setup low_mapfile high_mapfile \
- memtest memtest.out makedefs defs.lds memtest_shared memtest_shared.bin
+ rm -f *.o *.s *.iso memtest.bin memtest memtest_shared memtest_shared.bin
+
+asm:
+ @./makedos.sh
-wormkill:
- rm -f *~
+iso:
+ make all
+ ./makeiso.sh
+ rm -f *.o *.s memtest.bin memtest memtest_shared memtest_shared.bin
install: all
dd <memtest.bin >$(FDISK) bs=8192
-install-bin:
+install-precomp:
dd <precomp.bin >$(FDISK) bs=8192
+
+dos: all
+ cat mt86+_loader memtest.bin > memtest.exe
+
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/README
^
|
| @@ -1,8 +1,5 @@
- ====================
- = MemTest-86 v3.2 =
- = Nov 11, 2004 =
- = Chris Brady =
- ====================
+Memtest86++ v4.20
+====================
Table of Contents
=================
@@ -16,42 +13,39 @@
8) Trouble-shooting Memory Errors
9) Execution Time
10) Memory Testing Philosophy
- 11) Memtest86 Test Algorithms
+ 11) Memtest86+ Test Algorithms
12) Individual Test Descriptions
13) Problem Reporting - Contact Information
14) Known Problems
- 15) Planned Features List
- 16) Change Log
- 17) Donations
- 18) Acknowledgments
+
1) Introduction
===============
-Memtest86 is thorough, stand alone memory test for Intel/AMD x86 architecture
+Memtest86+ is thorough, stand alone memory test for Intel/AMD x86 architecture
systems. BIOS based memory tests are only a quick check and often miss
-failures that are detected by Memtest86.
+failures that are detected by Memtest86+.
-For updates go to the Memtest86 web page:
+For updates go to the Memtest86+ web page:
- http://www.memtest86.com
+ http://www.memtest.org
2) Licensing
============
-Memtest86 is released under the terms of the Gnu Public License (GPL). Other
+Memtest86+ is released under the terms of the Gnu Public License (GPL). Other
than the provisions of the GPL there are no restrictions for use, private or
commercial. See: http://www.gnu.org/licenses/gpl.html for details.
-Explicit permission for inclusion of Memtest86 in software compilations and
+Explicit permission for inclusion of Memtest86+ in software compilations and
publications is hereby granted.
3) Installation (Linux Only)
============================
-Memtest86 is a stand alone program and can be loaded from either a disk
+Memtest86+ is a stand alone program and can be loaded from either a disk
partition or from a floppy disk.
-To build Memtest86:
+To build Memtest86+:
1) Review the Makefile and adjust options as needed.
2) Type "make"
@@ -59,22 +53,22 @@
image file may be copied to a floppy disk or lilo may be used to boot this
image from a hard disk partition.
-To create a Memtest86 bootdisk
+To create a Memtest86+ bootdisk
1) Insert a blank write enabled floppy disk.
2) As root, Type "make install"
To boot from a disk partition via lilo
1) Copy the image file to a permanent location (ie. /memtest).
2) Add an entry in the lilo config file (usually /etc/lilo.conf) to boot
- memtest86. Only the image and label fields need to be specified.
- The following is a sample lilo entry for booting memtest86:
+ Memtest86+. Only the image and label fields need to be specified.
+ The following is a sample lilo entry for booting Memtest86+:
image = /memtest
label = memtest
3) As root, type "lilo"
- At the lilo prompt enter memtest to boot memtest86.
+ At the lilo prompt enter memtest to boot Memtest86+.
If you encounter build problems a binary image has been included (precomp.bin).
To create a boot-disk with this pre-built image do the following:
@@ -84,19 +78,19 @@
4) Serial Console
=================
-Memtest86 can be used on PC's equipped with a serial port for the console.
+Memtest86+ can be used on PC's equipped with a serial port for the console.
By default serial port console support is not enabled since it slows
down testing. To enable change the SERIAL_CONSOLE_DEFAULT define in
config.h from a zero to a one. The serial console baud rate may also
be set in config.h with the SERIAL_BAUD_RATE define. The other serial
port settings are no parity, 8 data bits, 1 stop bit. All of the features
-used by memtest86 are accessible via the serial console. However, the
+used by Memtest86+ are accessible via the serial console. However, the
screen sometimes is garbled when the online commands are used.
5) Online Commands
==================
-Memtest86 has a limited number of online commands. Online commands
+Memtest86+ has a limited number of online commands. Online commands
provide control over caching, test selection, address range and error
scrolling. A help bar is displayed at the bottom of the screen listing
the available on-line commands.
@@ -131,19 +125,19 @@
ACPI tables). It is just as important to test these reserved memory blocks
as it is for the remainder of memory. For proper operation all of memory
needs to function properly regardless of what the eventual use is. For
-this reason Memtest86 has been designed to test as much memory as is
+this reason Memtest86+ has been designed to test as much memory as is
possible.
However, safely and reliably detecting all of the available memory has been
-problematic. Versions of Memtest86 prior to v2.9 would probe to find where
+problematic. Versions of Memtest86+ prior to v0.91 would probe to find where
memory is. This works for the vast majority of motherboards but is not 100%
reliable. Sometimes the memory size is incorrect and worse probing the wrong
places can in some cases cause the test to hang or crash.
-Starting in version 2.9 alternative methods are available for determining the
+Starting in version 0.91 alternative methods are available for determining the
memory size. By default the test attempts to get the memory size from the
BIOS using the "e820" method. With "e820" the BIOS provides a table of memory
-segments and identifies what they will be used for. By default Memtest86
+segments and identifies what they will be used for. By default Memtest86+
will test all of the ram marked as available and also the area reserved for
the ACPI tables. This is safe since the test does not use the ACPI tables
and the "e820" specifications state that this memory may be reused after the
@@ -213,7 +207,7 @@
8) Trouble-shooting Memory Errors
================================
-Please be aware that not all errors reported by Memtest86 are due to
+Please be aware that not all errors reported by Memtest86+ are due to
bad memory. The test implicitly tests the CPU, L1 and L2 caches as well as
the motherboard. It is impossible for the test to determine what causes
the failure to occur. Most failures will be due to a problem with memory.
@@ -263,9 +257,9 @@
uncommon and is a source of confusion. The components are not necessarily
bad but certain combinations may need to be avoided.
-I am often asked about the reliability of errors reported by Mestest86.
+I am often asked about the reliability of errors reported by Memtest86+.
In the vast majority of cases errors reported by the test are valid.
-There are some systems that cause Memtest86 to be confused about the size of
+There are some systems that cause Memtest86+ to be confused about the size of
memory and it will try to test non-existent memory. This will cause a large
number of consecutive addresses to be reported as bad and generally there
will be many bits in error. If you have a relatively small number of
@@ -278,15 +272,15 @@
disk corruption. You can be sure that Murphy will get you if you know
about a memory error and ignore it.
-Memtest86 can not diagnose many types of PC failures. For example a
+Memtest86+ can not diagnose many types of PC failures. For example a
faulty CPU that causes Windows to crash will most likely just cause
-Memtest86 to crash in the same way.
+Memtest86+ to crash in the same way.
9) Execution Time
==================
-The time required for a complete pass of Memtest86 will vary greatly
-depending on CPU speed, memory speed and memory size. Memtest86 executes
+The time required for a complete pass of Memtest86+ will vary greatly
+depending on CPU speed, memory speed and memory size. Memtest86+ executes
indefinitely. The pass counter increments each time that all of the
selected tests have been run. Generally a single pass is sufficient to
catch all but the most obscure errors. However, for complete confidence
@@ -320,9 +314,9 @@
are testing algorithms that can approximate this ideal strategy.
-11) Memtest86 Test Algorithms
+11) Memtest86+ Test Algorithms
=============================
-Memtest86 uses two algorithms that provide a reasonable approximation
+Memtest86+ uses two algorithms that provide a reasonable approximation
of the ideal test strategy above. The first of these strategies is called
moving inversions. The moving inversion test works as follows:
@@ -371,7 +365,7 @@
12) Individual Test Descriptions
================================
-Memtest86 executes a series of numbered test sections to check for
+Memtest86+ executes a series of numbered test sections to check for
errors. These test sections consist of a combination of test
algorithm, data pattern and caching. The execution order for these tests
were arranged so that errors will be detected as rapidly as possible.
@@ -447,50 +441,6 @@
sequence and must be run manually via the runtime configuration menu.
-13) Problem Reporting - Contact Information
-===========================================
-Due to the growing popularity of Memtest86 (more than 200,000 downloads per
-month) I have been inundated by, questions, feedback, problem reports and
-requests for enhancements. I simply do not have time to repond to ANY Memtest86
-emails. Bug reports and suggestions are welcome but will typically not be
-responded to.
-
-*** NOTE: *** The Keyword MEM86 must appear in the subject of all emails or
-the message will be automaticly deleted before it gets to me. This thanks to
-spam and viruses!
-
-Problems/Bugs:
-Before submitting a problem report please check the Known Problems section
-to see if this problem has already been reported. Be sure to include the
-version number and also any details that may be relevant.
-
-Chris Brady, Email: bugs@memtest86.com
-
-With some PC's Memtest86 will just die with no hints as to what went wrong.
-Without any details it is impossible to fix these failures. Fixing these
-problems will require debugging on your part. There is no point in reporting
-these failures unless you have a Linux system and would be willing to debug
-the failure.
-
-Enhancements:
-If you would like to request an enhancement please see if is already on
-the Planned Features List before sending your request. All requests will
-be considered, but not all can be implemented. If you are be interested in
-contributing code please contact me so that the integration can be
-co-ordinated.
-
-Chris Brady, Email: enhance@memtest86.com
-
-Questions:
-Unfortunately, I do not have time to respond to any questions or provide
-assistance with troubleshooting problems. Please read the Troubleshooting
-and Known Problems sections for assistance with problems. These sections have
-the answers for the questions that I have answers to. If there is not an
-answer for your problem in these sections it is probably not something I can
-help you with.
-
-
-
14) Known Problems
==================
Sometimes when booting from a floppy disk the following messages scroll up
@@ -503,12 +453,12 @@
This the BIOS reporting floppy disk read errors. Either re-write or toss
the floppy disk.
-Memtest86 has no support for multiple CPUs. Memtest86 should run
+Memtest86+ has no support for multiple CPUs. Memtest86+ should run
without problems, but it will only use one CPU.
-Memtest86 can not diagnose many types of PC failures. For example a
+Memtest86+ can not diagnose many types of PC failures. For example a
faulty CPU that causes Windows to crash will most likely just cause
-Memtest86 to crash in the same way.
+Memtest86+ to crash in the same way.
There have been numerous reports of errors in only tests 5 and 8 on Athlon
systems. Often the memory works in a different system or the vendor insists
@@ -518,333 +468,13 @@
cases the only option is to replace the memory with better quality, higher
speed memory. Don't buy cheap memory and expect it to work with an Athlon!
-Memtest86 supports all types of memory. If fact the test has absolutely
+Memtest86+ supports all types of memory. If fact the test has absolutely
no knowledge of the memory type nor does it need to. This not a problem
or bug but is listed here due to the many questions I get about this issue.
Changes in the compiler and loader have caused problems with
-Memtest86 resulting in both build failures and errors in execution. A
+Memtest86+ resulting in both build failures and errors in execution. A
binary image (precomp.bin) of the test is included and may be used if
problems are encountered.
-15) Planned Features List
-=========================
-This is a list of enhancements planned for future releases of Memtest86.
-There is no timetable for when these will be implemented, if ever.
-
- - Option to allow printing of error information on an attached printer.
- - Option to write error information to a floppy disk.
- - Supply Memtest in RPM format.
- - Read and display RAM SPD information.
-
-
-16) Change Log
-==============
-Enhancements in v3.2 (11/Nov/2004)
-
- Added two new, highly effective tests that use random number patterns
- (tests 4 and 6).
-
- Reworked the online commands:
- - Changed wording for better clarity
- - Dropped Cache Mode menu
-
- Updated CPU detection for newer AMD, Intel and Cyrix CPUs.
-
- Reworked test sequence:
- - Dropped ineffective non cached tests (Numbers 7-11)
- - Changed cache mode to cached for test 2
- - Fixed bug that did not allow tsome tests to be skipped
- - Added bailout for Bit fade test
-
- Error reports are highlighted in red to provide a more vivid error
- indication.
-
- Added support for a large number of additional chipsets. (from Memtest86+
- v1.30)
-
- Added an advanced setup feature that with new chiset allows memory timings
- to be altered from inside Memtest86. (from Memtest86+ v1.30)
-
-
-Enhancements in v3.1 (11/Mar/2004)
-
- Added processor detection for newer AMD processors.
-
- Added new "Bit Fade" extended test.
-
- Fixed a complile time bug with gcc version 3.x.
-
- E7500 memory controller ECC support
-
- Added support for 16bit ECC syndromes
-
- Option to keep the serial port baud rate of the boot loader
-
-
-Enhancements in v3.0 (22/May/2002) Provided by Eric Biederman
-
- Testing of more than 2gb of memory is at last fixed (tested with 6Gb)
-
- The infrastructure is to poll ecc error reporting chipset regisets,
- and the support has been done for some chipsets.
-
- Uses dynamic relocation information records to make itself PIC
- instead of requiring 2 copies of memtest86 in the binary.
-
- The serial console code does not do redundant writes to the serial port
- Very little slow down at 9600 baud.
-
- You can press ^l or just l to get a screen refresh, when you are
- connecting and unconnecting a serial cable.
-
- Netbooting is working again
-
- LinuxBIOS support (To get the memory size)
-
- Many bugfixes and code cleanup.
-
-Enhancements in v2.9 (29/Feb/2002)
-
- The memory sizing code has been completely rewritten. By default
- Memtest86 gets a memory map from the BIOS that is now used to find
- available memory. A new online configuration option provides three
- choices for how memory will be sized, including the old "probe" method.
- The default mode generally will not test all of memory, but should be more
- stable. See the "Memory Sizing" section for details.
-
- Testing of more than 2gb of memory should now work. A number of bugs
- were found and corrected that prevented testing above 2gb. Testing
- with more than 2gb has been limited and there could be problems with a
- full 4gb of memory.
-
- Memory is divided into segments for testing. This allow for frequent
- progress updates and responsiveness to interactive commands. The
- memory segment size has been increased from 8 to 32mb. This should
- improve testing effectivness but progress reports will be less frequent.
-
- Minor bug fixes.
-
-Enhancements in v2.8 (18/Oct/2001)
- Eric Biederman reworked the build process making it far simpler and also
- to produce a network bootable ELF image.
-
- Re-wrote the memory and cache speed detection code. Previously the
- reported numbers were inaccurate for intel CPU's and completely wrong
- for Athlon/Duron CPU's.
-
- By default the serial console is disabled since this was slowing
- down testing.
-
- Added CPU detection for Pentium 4.
-
-
-Enhancements in v2.7 (12/Jul/2001)
- Expanded workaround for errors caused by BIOS USB keyboard support to
- include test #5.
-
- Re-worked L1 / L2 cache detection code to provide clearer reporting.
-
- Fixed an obvious bug in the computation of cache and memory speeds.
-
- Changed on-line menu to stay in the menu between option selections.
-
- Fixed bugs in the test restart and redraw code.
-
- Adjusted code size to fix compilation problems with RedHat 7.1.
-
- Misc updates to the documentation.
-
-Enhancements in v2.6 (25/May/2001)
- Added workaround for errors caused by BIOS USB keyboard support.
-
- Fixed problems with reporting of 1 GHZ + processor speeds.
-
- Fixed Duron cache detection.
-
- Added screen buffer so that menus will work correctly from a serial
- console.
-
- The Memtest86 image is now built in ELF format.
-
-Enhancements in v2.5 (14/Dec/00)
- Enhanced CPU and cache detection to correctly identify Duron CPU
- and K6-III 1MB cache.
-
- Added code to report cache-able memory size.
-
- Added limited support for parity memory.
-
- Support was added to allow use of on-line commands from a serial
- port.
-
- Dropped option for changing refresh rates. This was not useful
- and did not work on newer motherboards.
-
- Improved fatal exception reporting to include a register and stack
- dump.
-
- The pass number is now displayed in the error report.
-
- Fixed a bug that crashed the test when selecting one of the extended
- tests.
-
-Enhancements in v2.4
- The error report format was reworked for better clarity and now
- includes a decimal address in megabytes.
-
- A new memory move test was added (from Robert Redelmeier's CPU-Burn)
-
- The test sequence and iterations were modified.
-
- Fixed scrolling problems with the BadRAM patterns.
-
-
-Enhancements in v2.3
- A progress meter was added to replace the spinner and dots.
-
- Measurement and reporting of memory and cache performance
- was added.
-
- Support for creating BadRAM patterns was added.
-
- All of the test routines were rewritten in assembler to
- improve both test performance and speed.
-
- The screen layout was reworked to hopefully be more readable.
-
- An error summary option was added to the online commands.
-
-
-Enhancements in v2.2
- Added two new address tests
-
- Added an on-line command for setting test address range
-
- Optimized test code for faster execution (-O3, -funroll-loops and
- -fomit-frame-pointer)
-
- Added and elapsed time counter.
-
- Adjusted menu options for better consistency
-
-
-Enhancements in v2.1
- Fixed a bug in the CPU detection that caused the test to
- hang or crash with some 486 and Cryrix CPU's
-
- Added CPU detection for Cyrix CPU's
-
- Extended and improved CPU detection for Intel and AMD CPU's
-
- Added a compile time option (BIOS_MEMSZ) for obtaining the last
- memory address from the BIOS. This should fix problems with memory
- sizing on certain motherboards. This option is not enabled by default.
- It may be enabled be default in a future release.
-
-Enhancements in v2.0
- Added new Modulo-20 test algorithm.
-
- Added a 32 bit shifting pattern to the moving inversions algorithm.
-
- Created test sections to specify algorithm, pattern and caching.
-
- Improved test progress indicators.
-
- Created popup menus for configuration.
-
- Added menu for test selection.
-
- Added CPU and cache identification.
-
- Added a "bail out" feature to quit the current test when it does not
- fit the test selection parameters.
-
- Re-arranged the screen layout and colors.
-
- Created local include files for I/O and serial interface definitions
- rather than using the sometimes incompatible system include files.
-
- Broke up the "C" source code into four separate source modules.
-
-Enhancements in v1.5
- Some additional changes were made to fix obscure memory sizing
- problems.
-
- The 4 bit wide data pattern was increased to 8 bits since 8 bit
- wide memory chips are becoming more common.
-
- A new test algorithm was added to improve detection of data
- pattern sensitive errors.
-
-
-Enhancements in v1.4
- Changes to the memory sizing code to avoid problems with some
- motherboards where memtest would find more memory than actually
- exists.
-
- Added support for a console serial port. (thanks to Doug Sisk)
-
- On-line commands are now available for configuring Memtest86 on
- the fly (see On-line Commands).
-
-
-Enhancements in v1.3
- Scrolling of memory errors is now provided. Previously, only one screen
- of error information was displayed.
-
- Memtest86 can now be booted from any disk via lilo.
-
- Testing of up to 4gb of memory has been fixed is now enabled by default.
- This capability was clearly broken in v1.2a and should work correctly
- now but has not been fully tested (4gb PC's are a bit rare).
-
- The maximum memory size supported by the motherboard is now being
- calculated correctly. In previous versions there were cases where not
- all of memory would be tested and the maximum memory size supported
- was incorrect.
-
- For some types of failures the good and bad values were reported to be
- same with an Xor value of 0. This has been fixed by retaining the data
- read from memory and not re-reading the bad data in the error reporting
- routine.
-
- APM (advanced power management) is now disabled by Memtest86. This
- keeps the screen from blanking while the test is running.
-
- Problems with enabling & disabling cache on some motherboards have been
- corrected.
-
-
-17) Donations
-=============
-With considerable reluctance I am resorting to a low key solicitation for
-donations. It never has been my intent to profit from this program and I am
-pleased that Memtest86 has been helpful. However, the time required to
-support this program has grown significantly. I also have the modest
-cost of hosting this web-site that I would like to recover. So if you find
-Memtest86 useful and you feel inclined to make a small PayPal donation please
-do so. Use "cbrady@memtest86.com" for the recipient.
-
-
-18) Acknowledgments
-===================
-Memtest86 was developed by Chris Brady with the resources and assistance
-listed below:
-
-- The initial versions of the source files bootsect.S, setup.S, head.S and
- build.c are from the Linux 1.2.1 kernel and have been heavily modified.
-
-- Doug Sisk provided code to support a console connected via a serial port.
-
-- Code to create BadRAM patterns was provided by Rick van Rein.
-
-- Tests 5 and 8 are based on Robert Redelmeier's burnBX test.
-
-- Screen buffer code was provided by Jani Averbach.
-
-- Eric Biederman provided all of the feature content for version 3.0
- plus many bugfixes and significant code cleanup.
-- Major enhancements to hardware detection and reporting in version 3.2
- provided by Samuel Demeulemeester (from Memtest86+ v1.11).
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/README.build-process
^
|
| @@ -1,7 +1,7 @@
-During memory testing memtest86 relocates itself in memory so it can test the
-memory it was previously running from. memtest86 is compiled as position mostly
+During memory testing memtest86+ relocates itself in memory so it can test the
+memory it was previously running from. memtest86+ is compiled as position mostly
independent code. Some relocations records must be processed to achieve the
-affect of position independent code. A 16 bit loader is prepended to memtest86
+affect of position independent code. A 16 bit loader is prepended to memtest86+
so it can be loaded from a floppy, or from lilo.
In restructuring the build process I had several goals. Maintainability and
@@ -11,16 +11,16 @@
With the ability to proecess relocation records, memtest.bin has been
reduced in size from 84480 bytes to 49308 bytes. And now only requires one copy
-of memtest86. A reduction in size of 35K. And the build process can now ignore
-the size of memtest86.
+of memtest86+. A reduction in size of 35K. And the build process can now ignore
+the size of memtest86+.
BIOS calls have been moved from setup.S to head.S making bootsect.S and
setup.S exclusively for booting.
-memtest86 is built in three stages. In the first stage the relocatable object
+memtest86+ is built in three stages. In the first stage the relocatable object
files are built as with any program. In the second stage the relocatable object
files are linked together into memtest_shared, a shared library version
-of memtest86. In the third stage a raw memory image of memtest_shared is formed
+of memtest86+. In the third stage a raw memory image of memtest_shared is formed
and linked into memtest.bin, and memtest.
memtest.bin is the floppy/lilo bootable target.
@@ -28,11 +28,11 @@
memtest is the ELF bootable target.
Another major change is now data in the bss segment is also preserved
-when memtest86 is relocated, and memtest86 can be relocated to any address.
+when memtest86+ is relocated, and memtest86+ can be relocated to any address.
-The one thing to watch out for is pointers to data inside of memtest86. Except
+The one thing to watch out for is pointers to data inside of memtest86+. Except
for constant pointers to static data there is not enough information to generate
-relocation records for pointers so they will not change when memtest86 is
+relocation records for pointers so they will not change when memtest86+ is
relocated, which might lead to nasty surpises.
Eric Biederman <ebiederman@lnxi.com>
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/bootsect.S
^
|
| @@ -165,6 +165,7 @@
movw %ax, %es # segment of 0x010000
call read_it
call kill_motor
+ call turnoffcursor
call print_nl
# after that (everyting loaded), we jump to
@@ -354,6 +355,13 @@
popw %dx
ret
+turnoffcursor:
+ movb $0x01, %ah # turn off the cursor
+ movb $0x00, %bh
+ movw $0x2000, %cx
+ int $0x10
+ ret
+
sectors:
.word 0
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/changelog
^
|
| @@ -1,25 +1,9 @@
-Memtest86+ V.70 changelog
--------------------------
-
-- Added new DMI polling feature (Thanks to Joachim D.)
-- Added Support for Core/Core2 Solo/Duo/Quad CPU
-- Added Support for AMD K8 with DDR2 Memory
-- Added Support for Intel CPU with 192/384 KB L2 Cache
-- Added Support for FB-DIMM based memory (DMI)
-- Added Detection for ALI CyberAladdin-T (M1644)
-- Added Detection for Turion 64 X2
-- Added Detection for AMD K8 with unknown chipsets
-- Added Support for ATi Radeon xPress 3200
-- Added Support for Intel i975X
-- Added Support for Intel Q965/P965
-- Added Support for Intel Q963/Q965
-
-Thanks to Jesper Ekhall for betatesting.
-
-
-
-
-
-
-
+Memtest86+ V4.20 changelog
+--------------------------
+ - Added failsafe mode (F1 at startup)
+ - Added support for Intel "Sandy Bridge" CPU
+ - Added support for AMD "fusion" CPU
+ - Added Coreboot "table forward" support
+ - Corrected some memory brand not detected
+ - Various bug fixes
\ No newline at end of file
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/config.c
^
|
| @@ -1,9 +1,9 @@
-/* config.c - MemTest-86 Version 3.2
+/* config.c - MemTest-86 Version 3.4
*
* Released under version 2 of the Gnu Public License.
* By Chris Brady
* ----------------------------------------------------
- * MemTest86+ V2.00 Specific code (GPL V2.0)
+ * MemTest86+ V4.00 Specific code (GPL V2.0)
* By Samuel DEMEULEMEESTER, sdemeule@memtest.org
* http://www.x86-secret.com - http://www.memtest.org
*/
@@ -17,6 +17,8 @@
extern struct tseq tseq[];
extern short e820_nr;
extern char memsz_mode;
+extern int find_ticks_for_pass();
+//void performance();
char save[2][POP_H][POP_W];
char save2[2][POP2_H][POP2_W];
@@ -30,16 +32,16 @@
popup();
wait_keyup();
while(!flag) {
- cprint(POP_Y+1, POP_X+2, "Configuration:");
+ cprint(POP_Y+1, POP_X+2, "Settings:");
cprint(POP_Y+3, POP_X+6, "(1) Test Selection");
cprint(POP_Y+4, POP_X+6, "(2) Address Range");
cprint(POP_Y+5, POP_X+6, "(3) Memory Sizing");
- cprint(POP_Y+6, POP_X+6, "(4) Error Summary");
- cprint(POP_Y+7, POP_X+6, "(5) Error Report Mode");
+ cprint(POP_Y+6, POP_X+6, "(4) Error Report Mode");
+ cprint(POP_Y+7, POP_X+6, "(5) Show DMI Memory Info");
cprint(POP_Y+8, POP_X+6, "(6) ECC Mode");
cprint(POP_Y+9, POP_X+6, "(7) Restart");
cprint(POP_Y+10, POP_X+6, "(8) Refresh Screen");
- cprint(POP_Y+11, POP_X+6, "(9) Adv. Options");
+ cprint(POP_Y+11, POP_X+6, "(9) Display SPD Data");
cprint(POP_Y+12, POP_X+6, "(0) Continue");
/* Wait for key release */
@@ -54,7 +56,7 @@
cprint(POP_Y+4, POP_X+6, "(2) Skip Current Test");
cprint(POP_Y+5, POP_X+6, "(3) Select Test");
cprint(POP_Y+6, POP_X+6, "(4) Select Bit Fade Test");
- cprint(POP_Y+7, POP_X+6, "(5) Select Uncached Test");
+ //cprint(POP_Y+7, POP_X+6, "(5) Select Uncached Test");
cprint(POP_Y+8, POP_X+6, "(0) Continue");
if (v->testsel < 0) {
cprint(POP_Y+3, POP_X+5, ">");
@@ -66,11 +68,11 @@
switch(get_key()) {
case 2:
/* Default */
- if (v->testsel > 8) {
+ if (v->testsel >= 9) {
bail++;
}
v->testsel = -1;
- find_ticks();
+ find_ticks_for_pass();
sflag++;
cprint(LINE_INFO, COL_TST, "Std");
break;
@@ -85,16 +87,16 @@
cprint(POP_Y+1, POP_X+3,
"Test Selection:");
cprint(POP_Y+4, POP_X+5,
- "Test Number [0-10]: ");
+ "Test Number [0-9]: ");
i = getval(POP_Y+4, POP_X+24, 0);
- if (i <= 10) {
+ if (i <= 9) {
if (i != v->testsel) {
v->pass = -1;
v->test = -1;
}
v->testsel = i;
}
- find_ticks();
+ find_ticks_for_pass();
sflag++;
bail++;
cprint(LINE_INFO, COL_TST, "#");
@@ -106,24 +108,26 @@
v->test = -1;
}
v->testsel = 9;
- find_ticks();
+ find_ticks_for_pass();
sflag++;
bail++;
cprint(LINE_INFO, COL_TST, "#");
dprint(LINE_INFO, COL_TST+1, 9, 3, 1);
break;
+/*
case 6:
if (v->testsel != 10) {
v->pass = -1;
v->test = -1;
}
v->testsel = 9+1;
- find_ticks();
+ find_ticks_for_pass();
sflag++;
bail++;
cprint(LINE_INFO, COL_TST, "#");
dprint(LINE_INFO, COL_TST+1, 10, 3, 1);
break;
+*/
case 11:
case 57:
sflag++;
@@ -156,10 +160,11 @@
page = getval(POP_Y+6, POP_X+9, 12);
if (page + 1 <= v->plim_upper) {
v->plim_lower = page;
+ v->test--;
bail++;
}
adj_mem();
- find_ticks();
+ find_ticks_for_pass();
sflag++;
break;
case 3:
@@ -175,19 +180,21 @@
page = getval(POP_Y+6, POP_X+9, 12);
if (page - 1 >= v->plim_lower) {
v->plim_upper = page;
+ v->test--;
bail++;
}
adj_mem();
- find_ticks();
+ find_ticks_for_pass();
sflag++;
break;
case 4:
/* All of memory */
v->plim_lower = 0;
v->plim_upper = v->pmap[v->msegs - 1].end;
+ v->test--;
bail++;
adj_mem();
- find_ticks();
+ find_ticks_for_pass();
sflag++;
break;
case 11:
@@ -204,14 +211,9 @@
popclear();
cprint(POP_Y+1, POP_X+2, "Memory Sizing:");
cprint(POP_Y+3, POP_X+6, "(1) BIOS - Std");
- if (e820_nr) {
- cprint(POP_Y+4, POP_X+6, "(2) BIOS - All");
- cprint(POP_Y+5, POP_X+6, "(3) Probe");
- cprint(POP_Y+6, POP_X+6, "(0) Continue");
- cprint(POP_Y+2+memsz_mode, POP_X+5, ">");
- } else {
- cprint(POP_Y+4, POP_X+6, "(3) Probe");
+ cprint(POP_Y+4, POP_X+6, "(2) Probe");
cprint(POP_Y+5, POP_X+6, "(0) Continue");
+ if(!e820_nr){
if (memsz_mode == SZ_MODE_BIOS) {
cprint(POP_Y+3, POP_X+5, ">");
} else {
@@ -225,40 +227,13 @@
memsz_mode = SZ_MODE_BIOS;
wait_keyup();
restart();
-/*
- mem_size();
- v->test = 0;
- v->pass = 0;
- v->total_ticks = 0;
- bail++;
- sflag++;
-*/
+
break;
case 3:
- memsz_mode = SZ_MODE_BIOS_RES;
- wait_keyup();
- restart();
-/*
- mem_size();
- v->test = 0;
- v->pass = 0;
- v->total_ticks = 0;
- bail++;
- sflag++;
-*/
- break;
- case 4:
memsz_mode = SZ_MODE_PROBE;
wait_keyup();
restart();
-/*
- mem_size();
- v->test = 0;
- v->pass = 0;
- v->total_ticks = 0;
- bail++;
- sflag++;
-*/
+
break;
case 11:
case 57:
@@ -270,68 +245,60 @@
popclear();
break;
case 5:
- /* 4 - Show error summary */
- popclear();
- for (i=0; tseq[i].msg != NULL; i++) {
- cprint(POP_Y+1+i, POP_X+2, "Test:");
- dprint(POP_Y+1+i, POP_X+8, i, 2, 1);
- cprint(POP_Y+1+i, POP_X+12, "Errors:");
- dprint(POP_Y+1+i, POP_X+20, tseq[i].errors,
- 5, 1);
- }
- wait_keyup();
- while (get_key() == 0);
- popclear();
- break;
- case 6:
- /* 5 - Printing Mode */
+ /* 4 - Show error Mode */
popclear();
cprint(POP_Y+1, POP_X+2, "Printing Mode:");
- cprint(POP_Y+3, POP_X+6, "(1) Individual Errors");
- cprint(POP_Y+4, POP_X+6, "(2) BadRAM Patterns");
- cprint(POP_Y+5, POP_X+6, "(3) DMI Device Name");
+ cprint(POP_Y+3, POP_X+6, "(1) Error Summary");
+ cprint(POP_Y+4, POP_X+6, "(2) Individual Errors");
+ cprint(POP_Y+5, POP_X+6, "(3) BadRAM Patterns");
cprint(POP_Y+6, POP_X+6, "(4) Error Counts Only");
- cprint(POP_Y+7, POP_X+6, "(5) Beep on Error");
- cprint(POP_Y+8, POP_X+6, "(6) Show DMI Memory Info");
- cprint(POP_Y+9, POP_X+6, "(0) Cancel");
+ cprint(POP_Y+7, POP_X+6, "(5) DMI Device Name");
+ cprint(POP_Y+8, POP_X+6, "(6) Beep on Error");
+ cprint(POP_Y+10, POP_X+6, "(0) Cancel");
cprint(POP_Y+3+v->printmode, POP_X+5, ">");
- if (beepmode) { cprint(POP_Y+7, POP_X+5, ">"); }
+ if (beepmode) { cprint(POP_Y+8, POP_X+5, ">"); }
wait_keyup();
while (!sflag) {
- switch(get_key()) {
+ switch(get_key()) {
case 2:
+ /* Error Summary */
+ v->printmode=PRINTMODE_SUMMARY;
+ v->erri.eadr = 0;
+ v->erri.hdr_flag = 0;
+ sflag++;
+ break;
+ case 3:
/* Separate Addresses */
v->printmode=PRINTMODE_ADDRESSES;
- v->eadr = 0;
+ v->erri.eadr = 0;
+ v->erri.hdr_flag = 0;
+ v->msg_line = LINE_SCROLL-1;
sflag++;
break;
- case 3:
+ case 4:
/* BadRAM Patterns */
v->printmode=PRINTMODE_PATTERNS;
+ v->erri.hdr_flag = 0;
sflag++;
prt++;
break;
- case 4:
- /* DMI Devices */
- v->printmode=PRINTMODE_DMI;
- sflag++;
- break;
- case 5:
+ case 5:
/* Error Counts Only */
v->printmode=PRINTMODE_NONE;
+ v->erri.hdr_flag = 0;
sflag++;
break;
case 6:
- /* Set Beep On Error mode */
- beepmode = !beepmode;
+ /* Error Counts Only */
+ v->printmode=PRINTMODE_DMI;
+ v->erri.hdr_flag = 0;
sflag++;
break;
case 7:
- /* Display DMI Memory Info */
- pop2up();
- print_dmi_info();
- pop2down();
- break;
+ /* Set Beep On Error mode */
+ beepmode = !beepmode;
+ sflag++;
+ break;
case 11:
case 57:
/* 0/CR - Continue */
@@ -341,6 +308,12 @@
}
popclear();
break;
+ case 6:
+ /* Display DMI Memory Info */
+ pop2up();
+ print_dmi_info();
+ pop2down();
+ break;
case 7:
/* 6 - ECC Polling Mode */
popclear();
@@ -382,7 +355,10 @@
flag++;
break;
case 10:
- get_menu();
+ popdown();
+ show_spd();
+ popup();
+ sflag++;
break;
case 11:
case 57:
@@ -560,3 +536,58 @@
}
}
}
+
+/*
+void performance()
+{
+ extern int l1_cache, l2_cache;
+ ulong speed;
+ int i;
+
+ popclear();
+
+ cprint(POP_Y+1, POP_X+1, " Read Write Copy");
+ cprint(POP_Y+3, POP_X+1, "L1 Cache:");
+ speed=memspeed((ulong)mapping(0x100), (l1_cache/4)*1024, 500, MS_READ);
+ dprint(POP_Y+3, POP_X+10, speed, 6, 0);
+ speed=memspeed((ulong)mapping(0x100), (l1_cache/4)*1024, 50, MS_WRITE);
+ dprint(POP_Y+3, POP_X+17, speed, 6, 0);
+ speed=memspeed((ulong)mapping(0x100), (l1_cache/4)*1024, 50, MS_COPY);
+ dprint(POP_Y+3, POP_X+24, speed, 6, 0);
+
+ if (l2_cache < l1_cache) {
+ i = l1_cache / 4 + l2_cache / 4;
+ } else {
+ i = l1_cache;
+ }
+ cprint(POP_Y+5, POP_X+1, "L2 Cache:");
+ speed=memspeed((ulong)mapping(0x100), i*1024, 500, MS_READ);
+ dprint(POP_Y+5, POP_X+10, speed, 6, 0);
+ speed=memspeed((ulong)mapping(0x100), i*1024, 50, MS_WRITE);
+ dprint(POP_Y+5, POP_X+17, speed, 6, 0);
+ speed=memspeed((ulong)mapping(0x100), i*1024, 50, MS_COPY);
+ dprint(POP_Y+5, POP_X+24, speed, 6, 0);
+
+ // Determine memory speed. To find the memory spped we use
+ // A block size that is 5x the sum of the L1 and L2 caches
+ i = (l2_cache + l1_cache) * 5;
+
+ // Make sure that we have enough memory to do the test
+ if ((1 + (i * 2)) > (v->plim_upper << 2)) {
+ i = ((v->plim_upper <<2) - 1) / 2;
+ }
+
+
+ cprint(POP_Y+7, POP_X+1, "Memory:");
+ speed=memspeed((ulong)mapping(0x100), i*1024, 500, MS_READ);
+ dprint(POP_Y+7, POP_X+10, speed, 6, 0);
+ speed=memspeed((ulong)mapping(0x100), i*1024, 50, MS_WRITE);
+ dprint(POP_Y+7, POP_X+17, speed, 6, 0);
+ speed=memspeed((ulong)mapping(0x100), i*1024, 50, MS_COPY);
+ dprint(POP_Y+7, POP_X+24, speed, 6, 0);
+
+ wait_keyup();
+ while (get_key() == 0);
+ popclear();
+}
+*/
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/config.h
^
|
| @@ -15,12 +15,24 @@
/* to enable. */
#define SERIAL_CONSOLE_DEFAULT 0
+/* SERIAL_TTY - The default serial port to use. 0=ttyS0, 1=ttyS1 */
+#define SERIAL_TTY 0
+
/* SERIAL_BAUD_RATE - Baud rate for the serial console */
#define SERIAL_BAUD_RATE 9600
+/* START_FAIL_SAFE - Default 0 = normal. Change to 1 to always start in fail safe mode */
+#define START_FAIL_SAFE 0
+
/* BEEP_MODE - Beep on error. Default off, Change to 1 to enable */
#define BEEP_MODE 0
+/* BEEP_END_NO_ERROR - Beep at end of each pass without error. Default off, Change to 1 to enable */
+#define BEEP_END_NO_ERROR 0
+
+/* FIRST_PASS_HALF_ITERATIONS - First pass twice faster / half iterations. Change to 0 to disable */
+#define FIRST_PASS_HALF_ITERATIONS 1
+
/* SCRN_DEBUG - extra check for SCREEN_BUFFER
*/
/* #define SCRN_DEBUG */
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/controller.c
^
|
| @@ -3,9 +3,9 @@
* Released under version 2 of the Gnu Public License.
* By Chris Brady, cbrady@sgi.com
* ----------------------------------------------------
- * MemTest86+ V1.70 Specific code (GPL V2.0)
+ * MemTest86+ V4.20 Specific code (GPL V2.0)
* By Samuel DEMEULEMEESTER, sdemeule@memtest.org
- * http://www.x86-secret.com - http://www.memtest.org
+ * http://www.canardpc.com - http://www.memtest.org
*/
#include "defs.h"
@@ -13,11 +13,17 @@
#include "test.h"
#include "pci.h"
#include "controller.h"
+#include "spd.h"
+#include "test.h"
-int col, col2;
+int col, col2;
+int nhm_bus = 0x3F;
+
extern ulong extclock;
+extern unsigned long imc_type;
extern struct cpu_ident cpu_id;
+extern int fail_safe;
#define rdmsr(msr,val1,val2) \
__asm__ __volatile__("rdmsr" \
@@ -29,7 +35,6 @@
: /* no outputs */ \
: "c" (msr), "a" (val1), "d" (val2))
-
/* controller ECC capabilities and mode */
#define __ECC_UNEXPECTED 1 /* Unknown ECC capability present */
#define __ECC_DETECT 2 /* Can detect ECC errors */
@@ -80,62 +85,85 @@
void (*poll_errors)(void);
};
+
void print_timings_info(float cas, int rcd, int rp, int ras) {
/* Now, we could print some additionnals timings infos) */
- cprint(LINE_CPU+5, col2 +1, "/ CAS : ");
+ cprint(LINE_CPU+6, col2 +1, "/ CAS : ");
col2 += 9;
// CAS Latency (tCAS)
if (cas == 1.5) {
- cprint(LINE_CPU+5, col2, "1.5"); col2 += 3;
+ cprint(LINE_CPU+6, col2, "1.5"); col2 += 3;
} else if (cas == 2.5) {
- cprint(LINE_CPU+5, col2, "2.5"); col2 += 3;
+ cprint(LINE_CPU+6, col2, "2.5"); col2 += 3;
+ } else if (cas < 10) {
+ dprint(LINE_CPU+6, col2, cas, 1, 0); col2 += 1;
} else {
- dprint(LINE_CPU+5, col2, cas, 1, 0); col2 += 1;
+ dprint(LINE_CPU+6, col2, cas, 2, 0); col2 += 2;
}
- cprint(LINE_CPU+5, col2, "-"); col2 += 1;
+ cprint(LINE_CPU+6, col2, "-"); col2 += 1;
// RAS-To-CAS (tRCD)
- dprint(LINE_CPU+5, col2, rcd, 1, 0);
- cprint(LINE_CPU+5, col2+1, "-");
- col2 +=2;
+ if (rcd < 10) {
+ dprint(LINE_CPU+6, col2, rcd, 1, 0);
+ col2 += 1;
+ } else {
+ dprint(LINE_CPU+6, col2, rcd, 2, 0);
+ col2 += 2;
+ }
+ cprint(LINE_CPU+6, col2, "-"); col2 += 1;
// RAS Precharge (tRP)
- dprint(LINE_CPU+5, col2, rp, 1, 0);
- cprint(LINE_CPU+5, col2+1, "-");
- col2 +=2;
+ if (rp < 10) {
+ dprint(LINE_CPU+6, col2, rp, 1, 0);
+ col2 += 1;
+ } else {
+ dprint(LINE_CPU+6, col2, rp, 2, 0);
+ col2 += 2;
+ }
+ cprint(LINE_CPU+6, col2, "-"); col2 += 1;
// RAS Active to precharge (tRAS)
- if (ras < 9) {
- dprint(LINE_CPU+5, col2, ras, 1, 0);
+ if (ras < 10) {
+ dprint(LINE_CPU+6, col2, ras, 1, 0);
col2 += 2;
} else {
- dprint(LINE_CPU+5, col2, ras, 2, 0);
+ dprint(LINE_CPU+6, col2, ras, 2, 0);
col2 += 3;
}
}
+void print_fsb_info(float val, const char *text_fsb, const char *text_ddr) {
-void print_fsb_info(float val, const char *text_fsb) {
+ int i;
- cprint(LINE_CPU+5, col2, "Settings: ");
+ cprint(LINE_CPU+6, col2, "Settings: ");
col2 += 10;
- cprint(LINE_CPU+5, col2, text_fsb);
+ cprint(LINE_CPU+6, col2, text_fsb);
col2 += 6;
- dprint(LINE_CPU+5, col2, val ,3 ,0);
+ dprint(LINE_CPU+6, col2, val ,3 ,0);
col2 += 3;
- cprint(LINE_CPU+5, col2 +1, "MHz ");
- col2 += 5;
- cprint(LINE_CPU+5, col2, "(DDR");
- col2 += 4;
- dprint(LINE_CPU+5, col2, val*2 ,3 ,0);
- col2 += 3;
- cprint(LINE_CPU+5, col2, ")");
+ cprint(LINE_CPU+6, col2 +1, "MHz (");
+ col2 += 6;
+
+ cprint(LINE_CPU+6, col2, text_ddr);
+ for(i = 0; text_ddr[i] != '\0'; i++) { col2++; }
+
+ if(val < 500) {
+ dprint(LINE_CPU+6, col2, val*2 ,3 ,0);
+ col2 += 3;
+ } else {
+ dprint(LINE_CPU+6, col2, val*2 ,4 ,0);
+ col2 += 4;
+ }
+ cprint(LINE_CPU+6, col2, ")");
col2 += 1;
}
+
+
static void poll_fsb_nothing(void)
{
/* Code to run for no specific fsb detection */
@@ -148,7 +176,13 @@
return;
}
-
+static void poll_fsb_failsafe(void)
+{
+/* Code to run for no specific fsb detection */
+ cprint(LINE_CPU+5, 0, "Chipset/IMC : ***FAIL SAFE***FAIL SAFE***FAIL SAFE***FAIL SAFE***FAIL SAFE***");
+ cprint(LINE_CPU+6, 0, "*** Memtest86+ is running in fail safe mode. Same reliability, less details ***");
+ return;
+}
static void setup_nothing(void)
{
ctrl.cap = ECC_NONE;
@@ -163,6 +197,94 @@
return;
}
+static void setup_wmr(void)
+{
+
+ // Activate MMR I/O
+ ulong dev0;
+ ctrl.cap = ECC_CORRECT;
+
+ pci_conf_read( 0, 0, 0, 0x48, 4, &dev0);
+ if (!(dev0 & 0x1)) {
+ pci_conf_write( 0, 0, 0, 0x48, 1, dev0 | 1);
+ }
+
+ ctrl.mode = ECC_NONE;
+
+}
+
+
+static void setup_nhm(void)
+{
+ static float possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};
+ unsigned long did, vid, mc_control, mc_ssrcontrol;
+ int i;
+
+ //Nehalem supports Scrubbing */
+ ctrl.cap = ECC_SCRUB;
+ ctrl.mode = ECC_NONE;
+
+ /* First, locate the PCI bus where the MCH is located */
+
+ for(i = 0; i < sizeof(possible_nhm_bus); i++) {
+ pci_conf_read( possible_nhm_bus[i], 3, 4, 0x00, 2, &vid);
+ pci_conf_read( possible_nhm_bus[i], 3, 4, 0x02, 2, &did);
+ vid &= 0xFFFF;
+ did &= 0xFF00;
+ if(vid == 0x8086 && did >= 0x2C00) {
+ nhm_bus = possible_nhm_bus[i];
+ }
+}
+
+ /* Now, we have the last IMC bus number in nhm_bus */
+ /* Check for ECC & Scrub */
+
+ pci_conf_read(nhm_bus, 3, 0, 0x4C, 2, &mc_control);
+ if((mc_control >> 4) & 1) {
+ ctrl.mode = ECC_CORRECT;
+ pci_conf_read(nhm_bus, 3, 2, 0x48, 2, &mc_ssrcontrol);
+ if(mc_ssrcontrol & 3) {
+ ctrl.mode = ECC_SCRUB;
+ }
+ }
+
+}
+
+static void setup_nhm32(void)
+{
+ static float possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};
+ unsigned long did, vid, mc_control, mc_ssrcontrol;
+ int i;
+
+ //Nehalem supports Scrubbing */
+ ctrl.cap = ECC_SCRUB;
+ ctrl.mode = ECC_NONE;
+
+ /* First, locate the PCI bus where the MCH is located */
+
+ for(i = 0; i < sizeof(possible_nhm_bus); i++) {
+ pci_conf_read( possible_nhm_bus[i], 3, 4, 0x00, 2, &vid);
+ pci_conf_read( possible_nhm_bus[i], 3, 4, 0x02, 2, &did);
+ vid &= 0xFFFF;
+ did &= 0xFF00;
+ if(vid == 0x8086 && did >= 0x2C00) {
+ nhm_bus = possible_nhm_bus[i];
+ }
+}
+
+ /* Now, we have the last IMC bus number in nhm_bus */
+ /* Check for ECC & Scrub */
+ pci_conf_read(nhm_bus, 3, 0, 0x48, 2, &mc_control);
+ if((mc_control >> 1) & 1) {
+ ctrl.mode = ECC_CORRECT;
+ pci_conf_read(nhm_bus, 3, 2, 0x48, 2, &mc_ssrcontrol);
+ if(mc_ssrcontrol & 1) {
+ ctrl.mode = ECC_SCRUB;
+ }
+ }
+
+}
+
static void setup_amd64(void)
{
@@ -215,11 +337,47 @@
/* Clear any previous error */
pci_conf_read(0, 24, 3, 0x4C, 4, &mcanb);
pci_conf_write(0, 24, 3, 0x4C, 4, mcanb & 0x7F801EFC );
-
-
}
}
+static void setup_k10(void)
+{
+ static const int ddim[] = { ECC_NONE, ECC_CORRECT, ECC_CHIPKILL, ECC_CHIPKILL };
+ unsigned long nbxcfg;
+ unsigned int mcgsrl;
+ unsigned int mcgsth;
+ unsigned long mcanb;
+ unsigned long dramcl;
+ ulong msr_low, msr_high;
+
+ /* All AMD64 support Chipkill */
+ ctrl.cap = ECC_CHIPKILL;
+
+ /* Check First if ECC DRAM Modules are used */
+ pci_conf_read(0, 24, 2, 0x90, 4, &dramcl);
+
+ if ((dramcl >> 19)&1){
+ /* Fill in the correct memory capabilites */
+ pci_conf_read(0, 24, 3, 0x44, 4, &nbxcfg);
+ ctrl.mode = ddim[(nbxcfg >> 22)&3];
+ } else {
+ ctrl.mode = ECC_NONE;
+ }
+ /* Enable NB ECC Logging by MSR Write */
+ rdmsr(0x017B, mcgsrl, mcgsth);
+ wrmsr(0x017B, 0x10, mcgsth);
+
+ /* Clear any previous error */
+ pci_conf_read(0, 24, 3, 0x4C, 4, &mcanb);
+ pci_conf_write(0, 24, 3, 0x4C, 4, mcanb & 0x7FFFFFFF );
+
+ /* Enable ECS */
+ rdmsr(0xC001001F, msr_low, msr_high);
+ wrmsr(0xC001001F, msr_low, (msr_high | 0x4000));
+ rdmsr(0xC001001F, msr_low, msr_high);
+
+}
+
static void poll_amd64(void)
{
@@ -392,6 +550,30 @@
*/
}
+static void setup_E5400(void)
+{
+ unsigned long mcs;
+
+
+ /* Read the hardware capabilities */
+ pci_conf_read(ctrl.bus, 16, 1, 0x40, 4, &mcs);
+
+ /* Fill in the correct memory capabilities */
+ ctrl.mode = 0;
+ ctrl.cap = ECC_SCRUB;
+
+ /* Checking and correcting enabled */
+ if (((mcs >> 5) & 1) == 1) {
+ ctrl.mode |= ECC_CORRECT;
+ }
+
+ /* scrub enabled */
+ if (((mcs >> 7) & 1) == 1) {
+ ctrl.mode |= __ECC_SCRUB;
+ }
+}
+
+
static void setup_iE7xxx(void)
{
unsigned long mchcfgns;
@@ -642,10 +824,8 @@
/* Reseting state */
pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, 0x81);
-
}
-
static void setup_i925(void)
{
@@ -682,6 +862,28 @@
}
+static void setup_p35(void)
+{
+
+ // Activate MMR I/O
+ ulong dev0, capid0;
+
+ pci_conf_read( 0, 0, 0, 0x48, 4, &dev0);
+ if (!(dev0 & 0x1)) {
+ pci_conf_write( 0, 0, 0, 0x48, 1, dev0 | 1);
+ }
+
+ // ECC Checking (No poll on X38/48 for now)
+ pci_conf_read( 0, 0, 0, 0xE4, 4, &capid0);
+ if ((capid0 >> 8) & 1) {
+ ctrl.cap = ECC_NONE;
+ } else {
+ ctrl.cap = ECC_CORRECT;
+ }
+
+ ctrl.mode = ECC_NONE;
+
+}
static void poll_i875(void)
{
@@ -975,22 +1177,30 @@
}
+
+
/* ------------------ Here the code for FSB detection ------------------ */
/* --------------------------------------------------------------------- */
static float athloncoef[] = {11, 11.5, 12.0, 12.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 8.5, 9.0, 9.5, 10.0, 10.5};
static float athloncoef2[] = {12, 19.0, 12.0, 20.0, 13.0, 13.5, 14.0, 21.0, 15.0, 22, 16.0, 16.5, 17.0, 18.0, 23.0, 24.0};
-static int p4model1ratios[] = {16, 17, 18, 19, 20, 21, 22, 23, 8, 9, 10, 11, 12, 13, 14, 15};
+static float p4model1ratios[] = {16, 17, 18, 19, 20, 21, 22, 23, 8, 9, 10, 11, 12, 13, 14, 15};
-static int getP4PMmultiplier(void)
+static float getP4PMmultiplier(void)
{
unsigned int msr_lo, msr_hi;
- int coef;
+ float coef;
/* Find multiplier (by MSR) */
if (cpu_id.type == 6) {
- rdmsr(0x2A, msr_lo, msr_hi);
- coef = (msr_lo >> 22) & 0x1F;
+ if((cpu_id.feature_flag >> 7) & 1) {
+ rdmsr(0x198, msr_lo, msr_hi);
+ coef = ((msr_lo >> 8) & 0x1F);
+ if ((msr_lo >> 14) & 0x1) { coef = coef + 0.5f; }
+ } else {
+ rdmsr(0x2A, msr_lo, msr_hi);
+ coef = (msr_lo >> 22) & 0x1F;
+ }
}
else
{
@@ -998,7 +1208,7 @@
{
rdmsr(0x2A, msr_lo, msr_hi);
coef = (msr_lo >> 8) & 0xF;
- coef = p4model1ratios[coef];
+ coef = p4model1ratios[(int)coef];
}
else
{
@@ -1009,6 +1219,94 @@
return coef;
}
+static float getNHMmultiplier(void)
+{
+ unsigned int msr_lo, msr_hi;
+ float coef;
+
+ /* Find multiplier (by MSR) */
+ /* First, check if Flexible Ratio is Enabled */
+ rdmsr(0x194, msr_lo, msr_hi);
+ if((msr_lo >> 16) & 1){
+ coef = (msr_lo >> 8) & 0xFF;
+ } else {
+ rdmsr(0xCE, msr_lo, msr_hi);
+ coef = (msr_lo >> 8) & 0xFF;
+ }
+
+ return coef;
+}
+
+static float getSNBmultiplier(void)
+{
+ unsigned int msr_lo, msr_hi;
+ float coef;
+
+ rdmsr(0x198, msr_lo, msr_hi);
+ coef = (msr_lo >> 8) & 0xFF;
+ if(coef < 4)
+ {
+ rdmsr(0xCE, msr_lo, msr_hi);
+ coef = (msr_lo >> 16) & 0xFF;
+ }
+
+
+
+ return coef;
+}
+
+
+void getIntelPNS(void)
+{
+ int i,j;
+ long psn_eax, psn_ebx, psn_ecx, psn_edx;
+ long char_hex;
+ long ocpuid = 0x80000002;
+
+ for(j = 0; j < 4; j++)
+ {
+
+ asm __volatile__(
+ "pushl %%ebx\n\t" \
+ "cpuid\n\t" \
+ "movl %%ebx, %1\n\t" \
+ "popl %%ebx\n\t" \
+ : "=a" (psn_eax), "=r" (psn_ebx), "=c" (psn_ecx), "=d" (psn_edx)
+ : "a" (ocpuid)
+ : "cc"
+ );
+
+
+ for(i = 0; i < 4; i++)
+ {
+ char_hex = (psn_eax >> (i*8)) & 0xff;
+ cprint(LINE_CPU+5, col + i, convert_hex_to_char(char_hex));
+
+ char_hex = (psn_ebx >> (i*8)) & 0xff;
+ cprint(LINE_CPU+5, col + i + 4, convert_hex_to_char(char_hex));
+
+ if(psn_ecx != 0x20202020)
+ {
+ char_hex = (psn_ecx >> (i*8)) & 0xff;
+ cprint(LINE_CPU+5, col + i + 8, convert_hex_to_char(char_hex));
+
+ char_hex = (psn_edx >> (i*8)) & 0xff;
+ cprint(LINE_CPU+5, col + i + 12, convert_hex_to_char(char_hex));
+ }
+ else
+ {
+ char_hex = (psn_edx >> (i*8)) & 0xff;
+ cprint(LINE_CPU+5, col + i + 8, convert_hex_to_char(char_hex));
+ }
+ }
+ (psn_ecx != 0x20202020)?(col += 16):(col +=12);
+ if(psn_edx == 0x20202020) { col -= 4; }
+ ocpuid++;
+ }
+
+ col -= 16;
+}
+
static void poll_fsb_amd64(void) {
unsigned int mcgsrl;
@@ -1091,7 +1389,147 @@
dramclock = (extclock /1000) / clockratio;
/* ...and print */
- print_fsb_info(dramclock, "RAM : ");
+ print_fsb_info(dramclock, "RAM : ", "DDR");
+
+}
+
+static void poll_fsb_k10(void) {
+
+ unsigned int mcgsrl;
+ unsigned int mcgsth;
+ unsigned long temp2;
+ unsigned long dramchr;
+ unsigned long mainPllId;
+ double dramclock;
+ unsigned long pns_low;
+ unsigned long pns_high;
+ unsigned long msr_psn;
+
+
+ /* If ECC not enabled : display CPU name as IMC */
+ if(ctrl.mode == ECC_NONE)
+ {
+ cprint(LINE_CPU+5, 0, "IMC : ");
+ for(msr_psn = 0; msr_psn < 5; msr_psn++)
+ {
+ rdmsr(0xC0010030+msr_psn, pns_low, pns_high);
+ cprint(LINE_CPU+5, 6+(msr_psn*8), convert_hex_to_char(pns_low & 0xff));
+ cprint(LINE_CPU+5, 7+(msr_psn*8), convert_hex_to_char((pns_low >> 8) & 0xff));
+ cprint(LINE_CPU+5, 8+(msr_psn*8), convert_hex_to_char((pns_low >> 16) & 0xff));
+ cprint(LINE_CPU+5, 9+(msr_psn*8), convert_hex_to_char((pns_low >> 24) & 0xff));
+ cprint(LINE_CPU+5, 10+(msr_psn*8), convert_hex_to_char(pns_high & 0xff));
+ cprint(LINE_CPU+5, 11+(msr_psn*8), convert_hex_to_char((pns_high >> 8) & 0xff));
+ cprint(LINE_CPU+5, 12+(msr_psn*8), convert_hex_to_char((pns_high >> 16) & 0xff));
+ cprint(LINE_CPU+5, 13+(msr_psn*8), convert_hex_to_char((pns_high >> 24) & 0xff));
+ }
+ cprint(LINE_CPU+5, 41, "(ECC : Disabled)");
+ }
+
+ /* First, we need the clock ratio */
+ pci_conf_read(0, 24, 2, 0x94, 4, &dramchr);
+ temp2 = (dramchr & 0x7);
+
+ switch (temp2) {
+ case 0x7: temp2++;
+ case 0x6: temp2++;
+ case 0x5: temp2++;
+ case 0x4: temp2++;
+ default: temp2 += 3;
+ }
+
+
+ /* Compute the final DRAM Clock */
+ if (((cpu_id.ext >> 20) & 0xFF) == 1)
+ dramclock = ((temp2 * 200) / 3.0) + 0.25;
+ else {
+ unsigned long target;
+ unsigned long dx;
+ unsigned divisor;
+
+
+ target = temp2 * 400;
+
+ /* Get the FID by MSR */
+ rdmsr(0xc0010071, mcgsrl, mcgsth);
+
+ pci_conf_read(0, 24, 3, 0xD4, 4, &mainPllId);
+
+ if ( mainPllId & 0x40 )
+ mainPllId &= 0x3F;
+ else
+ mainPllId = 8; /* FID for 1600 */
+
+ mcgsth = (mcgsth >> 17) & 0x3F;
+ if ( mcgsth ) {
+ if ( mainPllId > mcgsth )
+ mainPllId = mcgsth;
+ }
+
+ dx = (mainPllId + 8) * 1200;
+ for ( divisor = 3; divisor < 100; divisor++ )
+ if ( (dx / divisor) <= target )
+ break;
+
+ dramclock = ((dx / divisor) / 6.0) + 0.25;
+/*
+ * dramclock = ((((dx * extclock) / divisor) / (mainPllId+8)) / 600000.0) + 0.25;
+ */
+}
+
+ /* ...and print */
+ print_fsb_info(dramclock, "RAM : ", "DDR");
+
+}
+
+static void poll_fsb_k14(void) {
+
+ unsigned long temp2;
+ unsigned long dramchr;
+ double dramclock;
+ unsigned long pns_low;
+ unsigned long pns_high;
+ unsigned long msr_psn;
+
+
+ /* If ECC not enabled : display CPU name as IMC */
+ if(ctrl.mode == ECC_NONE)
+ {
+ cprint(LINE_CPU+5, 0, "IMC : ");
+ for(msr_psn = 0; msr_psn < 5; msr_psn++)
+ {
+ rdmsr(0xC0010030+msr_psn, pns_low, pns_high);
+ cprint(LINE_CPU+5, 6+(msr_psn*8), convert_hex_to_char(pns_low & 0xff));
+ cprint(LINE_CPU+5, 7+(msr_psn*8), convert_hex_to_char((pns_low >> 8) & 0xff));
+ cprint(LINE_CPU+5, 8+(msr_psn*8), convert_hex_to_char((pns_low >> 16) & 0xff));
+ cprint(LINE_CPU+5, 9+(msr_psn*8), convert_hex_to_char((pns_low >> 24) & 0xff));
+ cprint(LINE_CPU+5, 10+(msr_psn*8), convert_hex_to_char(pns_high & 0xff));
+ cprint(LINE_CPU+5, 11+(msr_psn*8), convert_hex_to_char((pns_high >> 8) & 0xff));
+ cprint(LINE_CPU+5, 12+(msr_psn*8), convert_hex_to_char((pns_high >> 16) & 0xff));
+ cprint(LINE_CPU+5, 13+(msr_psn*8), convert_hex_to_char((pns_high >> 24) & 0xff));
+ }
+ cprint(LINE_CPU+5, 41, "(ECC : Disabled)");
+ }
+
+ /* First, we need the clock ratio */
+ pci_conf_read(0, 24, 2, 0x94, 4, &dramchr);
+ temp2 = (dramchr & 0x1F);
+
+ switch (temp2) {
+ default:
+ case 6:
+ dramclock = 400;
+ break;
+ case 10:
+ dramclock = 533;
+ break;
+ case 14:
+ dramclock = 667;
+ break;
+ }
+
+
+ /* print */
+ print_fsb_info(dramclock, "RAM : ", "DDR-");
}
@@ -1099,7 +1537,7 @@
double dramclock, dramratio, fsb;
unsigned long mchcfg, mchcfg2, dev0, drc, idetect;
- int coef = getP4PMmultiplier();
+ float coef = getP4PMmultiplier();
long *ptr;
pci_conf_read( 0, 0, 0, 0x02, 2, &idetect);
@@ -1144,14 +1582,14 @@
dramclock = fsb * dramratio;
// Print DRAM Freq
- print_fsb_info(dramclock, "RAM : ");
+ print_fsb_info(dramclock, "RAM : ", "DDR");
/* Print FSB (only if ECC is not enabled) */
- cprint(LINE_CPU+4, col +1, "- FSB : ");
+ cprint(LINE_CPU+5, col +1, "- FSB : ");
col += 9;
- dprint(LINE_CPU+4, col, fsb, 3,0);
+ dprint(LINE_CPU+5, col, fsb, 3,0);
col += 3;
- cprint(LINE_CPU+4, col +1, "MHz");
+ cprint(LINE_CPU+5, col +1, "MHz");
col += 4;
}
@@ -1160,7 +1598,7 @@
double dramclock, dramratio, fsb;
unsigned long mchcfg, dev0;
- int coef = getP4PMmultiplier();
+ float coef = getP4PMmultiplier();
long *ptr;
/* Find dramratio */
@@ -1182,14 +1620,14 @@
dramclock = fsb * dramratio;
// Print DRAM Freq
- print_fsb_info(dramclock, "RAM : ");
+ print_fsb_info(dramclock, "RAM : ", "DDR");
/* Print FSB (only if ECC is not enabled) */
- cprint(LINE_CPU+4, col +1, "- FSB : ");
+ cprint(LINE_CPU+5, col +1, "- FSB : ");
col += 9;
- dprint(LINE_CPU+4, col, fsb, 3,0);
+ dprint(LINE_CPU+5, col, fsb, 3,0);
col += 3;
- cprint(LINE_CPU+4, col +1, "MHz");
+ cprint(LINE_CPU+5, col +1, "MHz");
col += 4;
}
@@ -1198,7 +1636,7 @@
double dramclock, dramratio, fsb;
unsigned long mchcfg, dev0, fsb_mch;
- int coef = getP4PMmultiplier();
+ float coef = getP4PMmultiplier();
long *ptr;
/* Find dramratio */
@@ -1251,14 +1689,14 @@
dramclock = fsb * dramratio;
// Print DRAM Freq
- print_fsb_info(dramclock, "RAM : ");
+ print_fsb_info(dramclock, "RAM : ", "DDR");
/* Print FSB (only if ECC is not enabled) */
- cprint(LINE_CPU+4, col +1, "- FSB : ");
+ cprint(LINE_CPU+5, col +1, "- FSB : ");
col += 9;
- dprint(LINE_CPU+4, col, fsb, 3,0);
+ dprint(LINE_CPU+5, col, fsb, 3,0);
col += 3;
- cprint(LINE_CPU+4, col +1, "MHz");
+ cprint(LINE_CPU+5, col +1, "MHz");
col += 4;
}
@@ -1267,11 +1705,11 @@
double dramclock, dramratio, fsb;
unsigned long mchcfg, dev0, fsb_mch;
- int coef = getP4PMmultiplier();
+ float coef = getP4PMmultiplier();
long *ptr;
/* Find dramratio */
- pci_conf_read( 0, 0, 0, 0x44, 4, &dev0);
+ pci_conf_read( 0, 0, 0, 0x48, 4, &dev0);
dev0 &= 0xFFFFC000;
ptr=(long*)(dev0+0xC00);
mchcfg = *ptr & 0xFFFF;
@@ -1281,7 +1719,9 @@
case 0: fsb_mch = 1066; break;
case 1: fsb_mch = 533; break;
default: case 2: fsb_mch = 800; break;
- case 3: fsb_mch = 667; break;
+ case 3: fsb_mch = 667; break;
+ case 4: fsb_mch = 1333; break;
+ case 6: fsb_mch = 1600; break;
}
@@ -1298,20 +1738,42 @@
case 800:
switch ((mchcfg >> 4)&7) {
case 0: dramratio = 1.0; break;
- case 1: dramratio = 1.33334; break;
- case 2: dramratio = 1.66667; break;
+ case 1: dramratio = 5.0f/4.0f; break;
+ case 2: dramratio = 5.0f/3.0f; break;
case 3: dramratio = 2.0; break;
+ case 4: dramratio = 8.0f/3.0f; break;
+ case 5: dramratio = 10.0f/3.0f; break;
}
break;
case 1066:
switch ((mchcfg >> 4)&7) {
- case 1: dramratio = 1.0; break;
- case 2: dramratio = 1.25; break;
- case 3: dramratio = 1.5; break;
- case 4: dramratio = 2.0; break;
+ case 1: dramratio = 1.0f; break;
+ case 2: dramratio = 5.0f/4.0f; break;
+ case 3: dramratio = 3.0f/2.0f; break;
+ case 4: dramratio = 2.0f; break;
+ case 5: dramratio = 5.0f/2.0f; break;
+ }
+ break;
+
+ case 1333:
+ switch ((mchcfg >> 4)&7) {
+ case 2: dramratio = 1.0f; break;
+ case 3: dramratio = 6.0f/5.0f; break;
+ case 4: dramratio = 8.0f/5.0f; break;
+ case 5: dramratio = 2.0f; break;
+ }
+ break;
+
+ case 1600:
+ switch ((mchcfg >> 4)&7) {
+ case 3: dramratio = 1.0f; break;
+ case 4: dramratio = 4.0f/3.0f; break;
+ case 5: dramratio = 3.0f/2.0f; break;
+ case 6: dramratio = 2.0f; break;
}
break;
+
}
// Compute RAM Frequency
@@ -1319,24 +1781,149 @@
dramclock = fsb * dramratio;
// Print DRAM Freq
- print_fsb_info(dramclock, "RAM : ");
+ print_fsb_info(dramclock, "RAM : ", "DDR");
/* Print FSB (only if ECC is not enabled) */
- cprint(LINE_CPU+4, col +1, "- FSB : ");
+ cprint(LINE_CPU+5, col +1, "- FSB : ");
col += 9;
- dprint(LINE_CPU+4, col, fsb, 3,0);
+ dprint(LINE_CPU+5, col, fsb, 3,0);
col += 3;
- cprint(LINE_CPU+4, col +1, "MHz");
+ cprint(LINE_CPU+5, col +1, "MHz");
col += 4;
}
+static void poll_fsb_im965(void) {
+
+ double dramclock, dramratio, fsb;
+ unsigned long mchcfg, dev0, fsb_mch;
+ float coef = getP4PMmultiplier();
+ long *ptr;
+
+ /* Find dramratio */
+ pci_conf_read( 0, 0, 0, 0x48, 4, &dev0);
+ dev0 &= 0xFFFFC000;
+ ptr=(long*)(dev0+0xC00);
+ mchcfg = *ptr & 0xFFFF;
+ dramratio = 1;
+
+ switch (mchcfg & 7) {
+ case 1: fsb_mch = 533; break;
+ default: case 2: fsb_mch = 800; break;
+ case 3: fsb_mch = 667; break;
+ case 6: fsb_mch = 1066; break;
+ }
+
+
+ switch (fsb_mch) {
+ case 533:
+ switch ((mchcfg >> 4)&7) {
+ case 1: dramratio = 5.0f/4.0f; break;
+ case 2: dramratio = 3.0f/2.0f; break;
+ case 3: dramratio = 2.0f; break;
+ }
+ break;
+
+ case 667:
+ switch ((mchcfg >> 4)&7) {
+ case 1: dramratio = 1.0f; break;
+ case 2: dramratio = 6.0f/5.0f; break;
+ case 3: dramratio = 8.0f/5.0f; break;
+ case 4: dramratio = 2.0f; break;
+ case 5: dramratio = 12.0f/5.0f; break;
+ }
+ break;
+ default:
+ case 800:
+ switch ((mchcfg >> 4)&7) {
+ case 1: dramratio = 5.0f/6.0f; break;
+ case 2: dramratio = 1.0f; break;
+ case 3: dramratio = 4.0f/3.0f; break;
+ case 4: dramratio = 5.0f/3.0f; break;
+ case 5: dramratio = 2.0f; break;
+ }
+ break;
+ case 1066:
+ switch ((mchcfg >> 4)&7) {
+ case 5: dramratio = 3.0f/2.0f; break;
+ case 6: dramratio = 2.0f; break;
+ }
+ break;
+}
+
+ // Compute RAM Frequency
+ fsb = ((extclock / 1000) / coef);
+ dramclock = fsb * dramratio;
+
+ // Print DRAM Freq
+ print_fsb_info(dramclock, "RAM : ", "DDR");
+
+ /* Print FSB (only if ECC is not enabled) */
+ cprint(LINE_CPU+5, col +1, "- FSB : ");
+ col += 9;
+ dprint(LINE_CPU+5, col, fsb, 3,0);
+ col += 3;
+ cprint(LINE_CPU+5, col +1, "MHz");
+ col += 4;
+
+}
+
+
+static void poll_fsb_5400(void) {
+
+ double dramclock, dramratio, fsb;
+ unsigned long ambase_low, ambase_high, ddrfrq;
+ float coef = getP4PMmultiplier();
+
+ /* Find dramratio */
+ pci_conf_read( 0, 16, 0, 0x48, 4, &ambase_low);
+ ambase_low &= 0xFFFE0000;
+ pci_conf_read( 0, 16, 0, 0x4C, 4, &ambase_high);
+ ambase_high &= 0xFF;
+ pci_conf_read( 0, 16, 1, 0x56, 1, &ddrfrq);
+ ddrfrq &= 7;
+ dramratio = 1;
+
+ switch (ddrfrq) {
+ case 0:
+ case 1:
+ case 4:
+ dramratio = 1.0;
+ break;
+ case 2:
+ dramratio = 5.0f/4.0f;
+ break;
+ case 3:
+ case 7:
+ dramratio = 4.0f/5.0f;
+ break;
+ }
+
+
+ // Compute RAM Frequency
+ fsb = ((extclock / 1000) / coef);
+ dramclock = fsb * dramratio;
+
+ // Print DRAM Freq
+ print_fsb_info(dramclock, "RAM : ", "DDR");
+
+ /* Print FSB (only if ECC is not enabled) */
+ cprint(LINE_CPU+5, col +1, "- FSB : ");
+ col += 9;
+ dprint(LINE_CPU+5, col, fsb, 3,0);
+ col += 3;
+ cprint(LINE_CPU+5, col +1, "MHz");
+ col += 4;
+
+}
+
+
static void poll_fsb_nf4ie(void) {
double dramclock, dramratio, fsb;
float mratio, nratio;
unsigned long reg74, reg60;
- int coef = getP4PMmultiplier();
+ float coef = getP4PMmultiplier();
/* Find dramratio */
pci_conf_read(0, 0, 2, 0x74, 2, ®74);
@@ -1360,14 +1947,14 @@
dramclock = fsb * dramratio;
/* Print DRAM Freq */
- print_fsb_info(dramclock, "RAM : ");
+ print_fsb_info(dramclock, "RAM : ", "DDR");
/* Print FSB */
- cprint(LINE_CPU+4, col, "- FSB : ");
+ cprint(LINE_CPU+5, col, "- FSB : ");
col += 9;
- dprint(LINE_CPU+4, col, fsb, 3,0);
+ dprint(LINE_CPU+5, col, fsb, 3,0);
col += 3;
- cprint(LINE_CPU+4, col +1, "MHz");
+ cprint(LINE_CPU+5, col +1, "MHz");
col += 4;
}
@@ -1376,7 +1963,7 @@
double dramclock, dramratio, fsb;
unsigned long mchcfg, smfs;
- int coef = getP4PMmultiplier();
+ float coef = getP4PMmultiplier();
/* Find dramratio */
pci_conf_read(0, 0, 0, 0xC6, 2, &mchcfg);
@@ -1402,15 +1989,15 @@
fsb = ((extclock /1000) / coef);
/* Print DRAM Freq */
- print_fsb_info(dramclock, "RAM : ");
+ print_fsb_info(dramclock, "RAM : ", "DDR");
/* Print FSB (only if ECC is not enabled) */
if ( ctrl.mode == ECC_NONE ) {
- cprint(LINE_CPU+4, col +1, "- FSB : ");
+ cprint(LINE_CPU+5, col +1, "- FSB : ");
col += 9;
- dprint(LINE_CPU+4, col, fsb, 3,0);
+ dprint(LINE_CPU+5, col, fsb, 3,0);
col += 3;
- cprint(LINE_CPU+4, col +1, "MHz");
+ cprint(LINE_CPU+5, col +1, "MHz");
col += 4;
}
}
@@ -1418,22 +2005,22 @@
static void poll_fsb_p4(void) {
ulong fsb, idetect;
- int coef = getP4PMmultiplier();
+ float coef = getP4PMmultiplier();
fsb = ((extclock /1000) / coef);
/* Print FSB */
- cprint(LINE_CPU+4, col +1, "/ FSB : ");
+ cprint(LINE_CPU+5, col +1, "/ FSB : ");
col += 9;
- dprint(LINE_CPU+4, col, fsb, 3,0);
+ dprint(LINE_CPU+5, col, fsb, 3,0);
col += 3;
- cprint(LINE_CPU+4, col +1, "MHz");
+ cprint(LINE_CPU+5, col +1, "MHz");
col += 4;
/* For synchro only chipsets */
pci_conf_read( 0, 0, 0, 0x02, 2, &idetect);
if (idetect == 0x2540 || idetect == 0x254C) {
- print_fsb_info(fsb, "RAM : ");
+ print_fsb_info(fsb, "RAM : ", "DDR");
}
}
@@ -1456,27 +2043,27 @@
/* Is it an i855GM or PM ? */
if (idetect == 0x3580) {
- cprint(LINE_CPU+4, col-1, "i855GM/GME ");
+ cprint(LINE_CPU+5, col-1, "i855GM/GME ");
col += 10;
}
} else {
rdmsr(0x2C, msr_lo, msr_hi);
coef = (msr_lo >> 24) & 0x1F;
- cprint(LINE_CPU+4, col-1, "i852PM/GM ");
+ cprint(LINE_CPU+5, col-1, "i852PM/GM ");
col += 9;
}
fsb = ((extclock /1000) / coef);
/* Print FSB */
- cprint(LINE_CPU+4, col, "/ FSB : "); col += 8;
- dprint(LINE_CPU+4, col, fsb, 3,0); col += 3;
- cprint(LINE_CPU+4, col +1, "MHz"); col += 4;
+ cprint(LINE_CPU+5, col, "/ FSB : "); col += 8;
+ dprint(LINE_CPU+5, col, fsb, 3,0); col += 3;
+ cprint(LINE_CPU+5, col +1, "MHz"); col += 4;
/* Is it a Centrino platform or only an i855 platform ? */
pci_conf_read( 2, 2, 0, 0x02, 2, ¢ri);
- if (centri == 0x1043) { cprint(LINE_CPU+4, col +1, "/ Centrino Mobile Platform"); }
- else { cprint(LINE_CPU+4, col +1, "/ Mobile Platform"); }
+ if (centri == 0x1043) { cprint(LINE_CPU+5, col +1, "/ Centrino Mobile Platform"); }
+ else { cprint(LINE_CPU+5, col +1, "/ Mobile Platform"); }
/* Compute DRAM Clock */
@@ -1501,7 +2088,7 @@
dramclock = fsb * dramratio;
/* ...and print */
- print_fsb_info(dramclock, "RAM : ");
+ print_fsb_info(dramclock, "RAM : ", "DDR");
}
@@ -1526,7 +2113,7 @@
dramclock = (extclock /1000) / coef2;
/* ...and print */
- print_fsb_info(dramclock, "FSB : ");
+ print_fsb_info(dramclock, "FSB : ", "DDR");
}
@@ -1540,203 +2127,857 @@
float coef;
coef = 10;
- /* First, got the FID */
- rdmsr(0x0c0010015, mcgsrl, mcgsth);
- temp = (mcgsrl >> 24)&0x0F;
+ /* First, got the FID */
+ rdmsr(0x0c0010015, mcgsrl, mcgsth);
+ temp = (mcgsrl >> 24)&0x0F;
+
+ if ((mcgsrl >> 19)&1) { coef = athloncoef2[temp]; }
+ else { coef = athloncoef[temp]; }
+
+ /* Get the coef (COEF = N/M) - Here is for Crush17 */
+ pci_conf_read(0, 0, 3, 0x70, 4, &mempll);
+ mem_m = (mempll&0x0F);
+ mem_n = ((mempll >> 4) & 0x0F);
+
+ /* If something goes wrong, the chipset is probably a Crush18 */
+ if ( mem_m == 0 || mem_n == 0 ) {
+ pci_conf_read(0, 0, 3, 0x7C, 4, &mempll);
+ mem_m = (mempll&0x0F);
+ mem_n = ((mempll >> 4) & 0x0F);
+ }
+
+ /* Compute the final FSB Clock */
+ dramclock = ((extclock /1000) / coef) * (mem_n/mem_m);
+ fsb = ((extclock /1000) / coef);
+
+ /* ...and print */
+
+ cprint(LINE_CPU+5, col, "/ FSB : ");
+ col += 8;
+ dprint(LINE_CPU+5, col, fsb, 3,0);
+ col += 3;
+ cprint(LINE_CPU+5, col +1, "MHz");
+
+ print_fsb_info(dramclock, "RAM : ", "DDR");
+
+}
+
+static void poll_fsb_us15w(void) {
+
+ double dramclock, dramratio, fsb, gfx;
+ unsigned long msr;
+
+ /* Find dramratio */
+ /* D0 MsgRd, 05 Zunit, 03 MSR */
+ pci_conf_write(0, 0, 0, 0xD0, 4, 0xD0050300 );
+ pci_conf_read(0, 0, 0, 0xD4, 4, &msr );
+ fsb = ( msr >> 3 ) & 1;
+
+ dramratio = 0.5;
+
+ // Compute RAM Frequency
+ if (( msr >> 3 ) & 1) {
+ fsb = 533;
+ } else {
+ fsb = 400;
+ }
+
+ switch (( msr >> 0 ) & 7) {
+ case 0:
+ gfx = 100;
+ break;
+ case 1:
+ gfx = 133;
+ break;
+ case 2:
+ gfx = 150;
+ break;
+ case 3:
+ gfx = 178;
+ break;
+ case 4:
+ gfx = 200;
+ break;
+ case 5:
+ gfx = 266;
+ break;
+ default:
+ gfx = 0;
+ break;
+ }
+
+ dramclock = fsb * dramratio;
+
+ // Print DRAM Freq
+ print_fsb_info(dramclock, "RAM : ", "DDR");
+
+ /* Print FSB (only if ECC is not enabled) */
+ cprint(LINE_CPU+4, col +1, "- FSB : ");
+ col += 9;
+ dprint(LINE_CPU+4, col, fsb, 3,0);
+ col += 3;
+ cprint(LINE_CPU+4, col +1, "MHz");
+ col += 4;
+
+ cprint(LINE_CPU+4, col +1, "- GFX : ");
+ col += 9;
+ dprint(LINE_CPU+4, col, gfx, 3,0);
+ col += 3;
+ cprint(LINE_CPU+4, col +1, "MHz");
+ col += 4;
+
+}
+
+static void poll_fsb_nhm(void) {
+
+ double dramclock, dramratio, fsb;
+ unsigned long mc_dimm_clk_ratio, qpi_pll_status;
+ float coef = getNHMmultiplier();
+ float qpi_speed;
+
+ fsb = ((extclock /1000) / coef);
+
+ /* Print FSB */
+ cprint(LINE_CPU+5, col +1, "/ BCLK : ");
+ col += 10;
+ dprint(LINE_CPU+5, col, fsb, 3,0);
+ col += 3;
+ cprint(LINE_CPU+5, col +1, "MHz");
+ col += 4;
+
+ /* Print QPI Speed (if ECC not supported) */
+ if(ctrl.mode == ECC_NONE && cpu_id.model == 10) {
+ pci_conf_read(nhm_bus, 2, 1, 0x50, 2, &qpi_pll_status);
+ qpi_speed = (qpi_pll_status & 0x7F) * ((extclock / 1000) / coef) * 2;
+ cprint(LINE_CPU+5, col +1, "/ QPI : ");
+ col += 9;
+ dprint(LINE_CPU+5, col, qpi_speed/1000, 1,0);
+ col += 1;
+ cprint(LINE_CPU+5, col, ".");
+ col += 1;
+ qpi_speed = ((qpi_speed / 1000) - (int)(qpi_speed / 1000)) * 10;
+ dprint(LINE_CPU+5, col, qpi_speed, 1,0);
+ col += 1;
+ cprint(LINE_CPU+5, col +1, "GT/s");
+ col += 5;
+ }
+
+ /* Get the clock ratio */
+
+ pci_conf_read(nhm_bus, 3, 4, 0x54, 2, &mc_dimm_clk_ratio);
+ dramratio = (mc_dimm_clk_ratio & 0x1F);
+
+ // Compute RAM Frequency
+ fsb = ((extclock / 1000) / coef);
+ dramclock = fsb * dramratio / 2;
+
+ // Print DRAM Freq
+ print_fsb_info(dramclock, "RAM : ", "DDR3-");
+
+}
+
+static void poll_fsb_nhm32(void) {
+
+ double dramclock, dramratio, fsb;
+ unsigned long mc_dimm_clk_ratio, qpi_pll_status;
+ float coef = getNHMmultiplier();
+ float qpi_speed;
+
+ fsb = ((extclock /1000) / coef);
+
+ /* Print FSB */
+ cprint(LINE_CPU+5, col +1, "/ BCLK : ");
+ col += 10;
+ dprint(LINE_CPU+5, col, fsb, 3,0);
+ col += 3;
+ cprint(LINE_CPU+5, col +1, "MHz");
+ col += 4;
+
+ /* Print QPI Speed (if ECC not supported) */
+ if(ctrl.mode == ECC_NONE && cpu_id.model == 12) {
+ pci_conf_read(nhm_bus, 2, 1, 0x50, 2, &qpi_pll_status);
+ qpi_speed = (qpi_pll_status & 0x7F) * ((extclock / 1000) / coef) * 2;
+ cprint(LINE_CPU+5, col +1, "/ QPI : ");
+ col += 9;
+ dprint(LINE_CPU+5, col, qpi_speed/1000, 1,0);
+ col += 1;
+ cprint(LINE_CPU+5, col, ".");
+ col += 1;
+ qpi_speed = ((qpi_speed / 1000) - (int)(qpi_speed / 1000)) * 10;
+ dprint(LINE_CPU+5, col, qpi_speed, 1,0);
+ col += 1;
+ cprint(LINE_CPU+5, col +1, "GT/s");
+ col += 5;
+ }
+
+ /* Get the clock ratio */
+
+ pci_conf_read(nhm_bus, 3, 4, 0x50, 2, &mc_dimm_clk_ratio);
+ dramratio = (mc_dimm_clk_ratio & 0x1F);
+
+ // Compute RAM Frequency
+ fsb = ((extclock / 1000) / coef);
+ dramclock = fsb * dramratio / 2;
+
+ // Print DRAM Freq
+ print_fsb_info(dramclock, "RAM : ", "DDR3-");
+
+}
+
+static void poll_fsb_wmr(void) {
+
+ double dramclock, dramratio, fsb;
+ unsigned long dev0, mchcfg;
+ float coef = getNHMmultiplier();
+ long *ptr;
+
+ fsb = ((extclock / 1000) / coef);
+
+ if(ctrl.mode == ECC_NONE)
+ {
+ col = 0;
+ cprint(LINE_CPU+5, col, "IMC : "); col += 6;
+ getIntelPNS();
+ //cprint(LINE_CPU+5, col, "(ECC : Disabled)");
+ //col += 16;
+ }
+
+ /* Print FSB */
+ cprint(LINE_CPU+5, col +1, "/ BCLK : ");
+ col += 10;
+ dprint(LINE_CPU+5, col, fsb, 3,0);
+ col += 3;
+ cprint(LINE_CPU+5, col +1, "MHz");
+ col += 4;
+
+ /* Find dramratio */
+ pci_conf_read( 0, 0, 0, 0x48, 4, &dev0);
+ dev0 &= 0xFFFFC000;
+ ptr=(long*)(dev0+0x2C20);
+ mchcfg = *ptr & 0xFFFF;
+ dramratio = 1;
+
+ /* Get the clock ratio */
+ dramratio = 0.25 * (float)(*ptr & 0x1F);
+
+ // Compute RAM Frequency
+ dramclock = fsb * dramratio;
+
+ // Print DRAM Freq
+ print_fsb_info(dramclock, "RAM : ", "DDR3-");
+
+}
+
+static void poll_fsb_snb(void) {
+
+ double dramclock, dramratio, fsb;
+ unsigned long dev0, mchcfg;
+ float coef = getSNBmultiplier();
+ long *ptr;
+
+ fsb = ((extclock / 1000) / coef);
+
+ if(ctrl.mode == ECC_NONE)
+ {
+ col = 0;
+ cprint(LINE_CPU+5, col, "IMC : "); col += 6;
+ getIntelPNS();
+ //cprint(LINE_CPU+5, col, "(ECC : Disabled)");
+ //col += 16;
+ }
+
+ /* Print FSB */
+ cprint(LINE_CPU+5, col +1, "/ BCLK : ");
+ col += 10;
+ dprint(LINE_CPU+5, col, fsb, 3,0);
+ col += 3;
+ cprint(LINE_CPU+5, col +1, "MHz");
+ col += 4;
+
+ /* Find dramratio */
+ pci_conf_read( 0, 0, 0, 0x48, 4, &dev0);
+ dev0 &= 0xFFFFC000;
+ ptr=(long*)(dev0+0x5E04);
+ mchcfg = *ptr & 0xFFFF;
+ dramratio = 1;
+
+ /* Get the clock ratio */
+ dramratio = (float)(*ptr & 0x1F) * (133.34f / 100.0f);
+
+ // Compute RAM Frequency
+ dramclock = fsb * dramratio;
+
+ // Print DRAM Freq
+ print_fsb_info(dramclock, "RAM : ", "DDR3-");
+
+}
+
+/* ------------------ Here the code for Timings detection ------------------ */
+/* ------------------------------------------------------------------------- */
+
+static void poll_timings_nf4ie(void) {
+
+
+ ulong regd0, reg8c, reg9c, reg80;
+ int cas, rcd, rp, ras;
+
+ cprint(LINE_CPU+5, col +1, "- Type : DDR-II");
+
+ //Now, read Registers
+ pci_conf_read( 0, 1, 1, 0xD0, 4, ®d0);
+ pci_conf_read( 0, 1, 1, 0x80, 1, ®80);
+ pci_conf_read( 0, 1, 0, 0x8C, 4, ®8c);
+ pci_conf_read( 0, 1, 0, 0x9C, 4, ®9c);
+
+ // Then, detect timings
+ cas = (regd0 >> 4) & 0x7;
+ rcd = (reg8c >> 24) & 0xF;
+ rp = (reg9c >> 8) & 0xF;
+ ras = (reg8c >> 16) & 0x3F;
+
+ print_timings_info(cas, rcd, rp, ras);
+
+ if (reg80 & 0x3) {
+ cprint(LINE_CPU+6, col2, "/ Dual Channel (128 bits)");
+ } else {
+ cprint(LINE_CPU+6, col2, "/ Single Channel (64 bits)");
+ }
+
+}
+
+static void poll_timings_i875(void) {
+
+ ulong dev6, dev62;
+ ulong temp;
+ float cas;
+ int rcd, rp, ras;
+ long *ptr, *ptr2;
+
+ /* Read the MMR Base Address & Define the pointer */
+ pci_conf_read( 0, 6, 0, 0x10, 4, &dev6);
+
+ /* Now, the PAT ritual ! (Kant and Luciano will love this) */
+ pci_conf_read( 0, 6, 0, 0x40, 4, &dev62);
+ ptr2=(long*)(dev6+0x68);
+
+ if ((dev62&0x3) == 0 && ((*ptr2 >> 14)&1) == 1) {
+ cprint(LINE_CPU+5, col +1, "- PAT : Enabled");
+ } else {
+ cprint(LINE_CPU+5, col +1, "- PAT : Disabled");
+ }
+
+ /* Now, we could check some additionnals timings infos) */
+
+ ptr=(long*)(dev6+0x60);
+ // CAS Latency (tCAS)
+ temp = ((*ptr >> 5)& 0x3);
+ if (temp == 0x0) { cas = 2.5; } else if (temp == 0x1) { cas = 2; } else { cas = 3; }
+
+ // RAS-To-CAS (tRCD)
+ temp = ((*ptr >> 2)& 0x3);
+ if (temp == 0x0) { rcd = 4; } else if (temp == 0x1) { rcd = 3; } else { rcd = 2; }
+
+ // RAS Precharge (tRP)
+ temp = (*ptr&0x3);
+ if (temp == 0x0) { rp = 4; } else if (temp == 0x1) { rp = 3; } else { rp = 2; }
+
+ // RAS Active to precharge (tRAS)
+ temp = ((*ptr >> 7)& 0x7);
+ ras = 10 - temp;
+
+ // Print timings
+ print_timings_info(cas, rcd, rp, ras);
+
+ // Print 64 or 128 bits mode
+ if (((*ptr2 >> 21)&3) > 0) {
+ cprint(LINE_CPU+6, col2, "/ Dual Channel (128 bits)");
+ } else {
+ cprint(LINE_CPU+6, col2, "/ Single Channel (64 bits)");
+ }
+}
+
+static void poll_timings_i925(void) {
+
+ // Thanks for CDH optis
+ ulong dev0, drt, drc, dcc, idetect, temp;
+ long *ptr;
+
+ //Now, read MMR Base Address
+ pci_conf_read( 0, 0, 0, 0x44, 4, &dev0);
+ pci_conf_read( 0, 0, 0, 0x02, 2, &idetect);
+ dev0 &= 0xFFFFC000;
+
+ //Set pointer for DRT
+ ptr=(long*)(dev0+0x114);
+ drt = *ptr & 0xFFFFFFFF;
+
+ //Set pointer for DRC
+ ptr=(long*)(dev0+0x120);
+ drc = *ptr & 0xFFFFFFFF;
+
+ //Set pointer for DCC
+ ptr=(long*)(dev0+0x200);
+ dcc = *ptr & 0xFFFFFFFF;
+
+ //Determine DDR or DDR-II
+ if ((drc & 3) == 2) {
+ cprint(LINE_CPU+5, col +1, "- Type : DDR2");
+ } else {
+ cprint(LINE_CPU+5, col +1, "- Type : DDR1");
+ }
+
+ // Now, detect timings
+ cprint(LINE_CPU+6, col2 +1, "/ CAS : ");
+ col2 += 9;
+
+ // CAS Latency (tCAS)
+ temp = ((drt >> 8)& 0x3);
+
+ if ((drc & 3) == 2){
+ // Timings DDR-II
+ if (temp == 0x0) { cprint(LINE_CPU+6, col2, "5-"); }
+ else if (temp == 0x1) { cprint(LINE_CPU+6, col2, "4-"); }
+ else if (temp == 0x2) { cprint(LINE_CPU+6, col2, "3-"); }
+ else { cprint(LINE_CPU+6, col2, "6-"); }
+ } else {
+ // Timings DDR-I
+ if (temp == 0x0) { cprint(LINE_CPU+6, col2, "3-"); }
+ else if (temp == 0x1) { cprint(LINE_CPU+6, col2, "2.5-"); col2 +=2;}
+ else { cprint(LINE_CPU+6, col2, "2-"); }
+ }
+ col2 +=2;
+
+ // RAS-To-CAS (tRCD)
+ dprint(LINE_CPU+6, col2, ((drt >> 4)& 0x3)+2, 1 ,0);
+ cprint(LINE_CPU+6, col2+1, "-");
+ col2 +=2;
+
+ // RAS Precharge (tRP)
+ dprint(LINE_CPU+6, col2, (drt&0x3)+2, 1 ,0);
+ cprint(LINE_CPU+6, col2+1, "-");
+ col2 +=2;
+
+ // RAS Active to precharge (tRAS)
+ // If Lakeport, than change tRAS computation (Thanks to CDH, again)
+ if (idetect > 0x2700)
+ temp = ((drt >> 19)& 0x1F);
+ else
+ temp = ((drt >> 20)& 0x0F);
+
+ dprint(LINE_CPU+6, col2, temp , 1 ,0);
+ (temp < 10)?(col2 += 1):(col2 += 2);
+
+ cprint(LINE_CPU+6, col2+1, "/"); col2 +=2;
+
+ temp = (dcc&0x3);
+ if (temp == 1) { cprint(LINE_CPU+6, col2, " Dual Channel (Asymmetric)"); }
+ else if (temp == 2) { cprint(LINE_CPU+6, col2, " Dual Channel (Interleaved)"); }
+ else { cprint(LINE_CPU+6, col2, " Single Channel (64 bits)"); }
+
+}
+
+static void poll_timings_i965(void) {
+
+ // Thanks for CDH optis
+ ulong dev0, temp, c0ckectrl, c1ckectrl, offset;
+ ulong ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register, Misc_Register;
+ long *ptr;
+
+ //Now, read MMR Base Address
+ pci_conf_read( 0, 0, 0, 0x48, 4, &dev0);
+ dev0 &= 0xFFFFC000;
+
+ ptr = (long*)(dev0+0x260);
+ c0ckectrl = *ptr & 0xFFFFFFFF;
+
+ ptr = (long*)(dev0+0x660);
+ c1ckectrl = *ptr & 0xFFFFFFFF;
+
+ // If DIMM 0 not populated, check DIMM 1
+ ((c0ckectrl) >> 20 & 0xF)?(offset = 0):(offset = 0x400);
+
+ ptr = (long*)(dev0+offset+0x29C);
+ ODT_Control_Register = *ptr & 0xFFFFFFFF;
+
+ ptr = (long*)(dev0+offset+0x250);
+ Precharge_Register = *ptr & 0xFFFFFFFF;
+
+ ptr = (long*)(dev0+offset+0x252);
+ ACT_Register = *ptr & 0xFFFFFFFF;
+
+ ptr = (long*)(dev0+offset+0x258);
+ Read_Register = *ptr & 0xFFFFFFFF;
+
+ ptr = (long*)(dev0+offset+0x244);
+ Misc_Register = *ptr & 0xFFFFFFFF;
+
+ //Intel 965 Series only support DDR2
+ cprint(LINE_CPU+5, col +1, "- Type : DDR-II");
+
+ // Now, detect timings
+ cprint(LINE_CPU+6, col2 +1, "/ CAS : ");
+ col2 += 9;
+
+ // CAS Latency (tCAS)
+ temp = ((ODT_Control_Register >> 17)& 7) + 3.0f;
+ dprint(LINE_CPU+6, col2, temp, 1 ,0);
+ cprint(LINE_CPU+6, col2+1, "-");
+ (temp < 10)?(col2 += 2):(col2 += 3);
+
+ // RAS-To-CAS (tRCD)
+ temp = (Read_Register >> 16) & 0xF;
+ dprint(LINE_CPU+6, col2, temp, 1 ,0);
+ cprint(LINE_CPU+6, col2+1, "-");
+ (temp < 10)?(col2 += 2):(col2 += 3);
+
+ // RAS Precharge (tRP)
+ temp = (ACT_Register >> 13) & 0xF;
+ dprint(LINE_CPU+6, col2, temp, 1 ,0);
+ cprint(LINE_CPU+6, col2+1, "-");
+ (temp < 10)?(col2 += 2):(col2 += 3);
+
+ // RAS Active to precharge (tRAS)
+ temp = (Precharge_Register >> 11) & 0x1F;
+ dprint(LINE_CPU+6, col2, temp, 1 ,0);
+ (temp < 10)?(col2 += 1):(col2 += 2);
+
+ cprint(LINE_CPU+6, col2+1, "/"); col2 +=2;
+
+ if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) {
+ cprint(LINE_CPU+6, col2+1, "Dual Channel");
+ } else {
+ cprint(LINE_CPU+6, col2+1, "Single Channel");
+ }
+
+}
+
+static void poll_timings_im965(void) {
+
+ // Thanks for CDH optis
+ ulong dev0, temp, c0ckectrl, c1ckectrl, offset;
+ ulong ODT_Control_Register, Precharge_Register;
+ long *ptr;
+
+ //Now, read MMR Base Address
+ pci_conf_read( 0, 0, 0, 0x48, 4, &dev0);
+ dev0 &= 0xFFFFC000;
+
+ ptr = (long*)(dev0+0x1200);
+ c0ckectrl = *ptr & 0xFFFFFFFF;
+
+ ptr = (long*)(dev0+0x1300);
+ c1ckectrl = *ptr & 0xFFFFFFFF;
+
+ // If DIMM 0 not populated, check DIMM 1
+ ((c0ckectrl) >> 20 & 0xF)?(offset = 0):(offset = 0x100);
+
+ ptr = (long*)(dev0+offset+0x121C);
+ ODT_Control_Register = *ptr & 0xFFFFFFFF;
+
+ ptr = (long*)(dev0+offset+0x1214);
+ Precharge_Register = *ptr & 0xFFFFFFFF;
+
+ //Intel 965 Series only support DDR2
+ cprint(LINE_CPU+5, col+1, "- Type : DDR-II");
+
+ // Now, detect timings
+ cprint(LINE_CPU+6, col2 +1, "/ CAS : ");
+ col2 += 9;
+
+ // CAS Latency (tCAS)
+ temp = ((ODT_Control_Register >> 23)& 7) + 3.0f;
+ dprint(LINE_CPU+6, col2, temp, 1 ,0);
+ cprint(LINE_CPU+6, col2+1, "-");
+ (temp < 10)?(col2 += 2):(col2 += 3);
+
+ // RAS-To-CAS (tRCD)
+ temp = ((Precharge_Register >> 5)& 7) + 2.0f;
+ dprint(LINE_CPU+6, col2, temp, 1 ,0);
+ cprint(LINE_CPU+6, col2+1, "-");
+ (temp < 10)?(col2 += 2):(col2 += 3);
+
+ // RAS Precharge (tRP)
+ temp = (Precharge_Register & 7) + 2.0f;
+ dprint(LINE_CPU+6, col2, temp, 1 ,0);
+ cprint(LINE_CPU+6, col2+1, "-");
+ (temp < 10)?(col2 += 2):(col2 += 3);
+
+ // RAS Active to precharge (tRAS)
+ temp = (Precharge_Register >> 21) & 0x1F;
+ dprint(LINE_CPU+6, col2, temp, 1 ,0);
+ (temp < 10)?(col2 += 1):(col2 += 2);
+
+ cprint(LINE_CPU+6, col2+1, "/"); col2 +=2;
+
+ if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) {
+ cprint(LINE_CPU+6, col2+1, "Dual Channel");
+ } else {
+ cprint(LINE_CPU+6, col2+1, "Single Channel");
+ }
+
+}
- if ((mcgsrl >> 19)&1) { coef = athloncoef2[temp]; }
- else { coef = athloncoef[temp]; }
+static void poll_timings_p35(void) {
- /* Get the coef (COEF = N/M) - Here is for Crush17 */
- pci_conf_read(0, 0, 3, 0x70, 4, &mempll);
- mem_m = (mempll&0x0F);
- mem_n = ((mempll >> 4) & 0x0F);
+ // Thanks for CDH optis
+ float cas;
+ int rcd, rp, ras;
+ ulong dev0, Device_ID, Memory_Check, c0ckectrl, c1ckectrl, offset;
+ ulong ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register, Misc_Register;
+ long *ptr;
- /* If something goes wrong, the chipset is probably a Crush18 */
- if ( mem_m == 0 || mem_n == 0 ) {
- pci_conf_read(0, 0, 3, 0x7C, 4, &mempll);
- mem_m = (mempll&0x0F);
- mem_n = ((mempll >> 4) & 0x0F);
- }
+ pci_conf_read( 0, 0, 0, 0x02, 2, &Device_ID);
+ Device_ID &= 0xFFFF;
- /* Compute the final FSB Clock */
- dramclock = ((extclock /1000) / coef) * (mem_n/mem_m);
- fsb = ((extclock /1000) / coef);
+ //Now, read MMR Base Address
+ pci_conf_read( 0, 0, 0, 0x48, 4, &dev0);
+ dev0 &= 0xFFFFC000;
- /* ...and print */
+ ptr = (long*)(dev0+0x260);
+ c0ckectrl = *ptr & 0xFFFFFFFF;
- cprint(LINE_CPU+4, col, "/ FSB : ");
- col += 8;
- dprint(LINE_CPU+4, col, fsb, 3,0);
- col += 3;
- cprint(LINE_CPU+4, col +1, "MHz");
+ ptr = (long*)(dev0+0x660);
+ c1ckectrl = *ptr & 0xFFFFFFFF;
+
+ // If DIMM 0 not populated, check DIMM 1
+ ((c0ckectrl) >> 20 & 0xF)?(offset = 0):(offset = 0x400);
- print_fsb_info(dramclock, "RAM : ");
+ ptr = (long*)(dev0+offset+0x265);
+ ODT_Control_Register = *ptr & 0xFFFFFFFF;
-}
+ ptr = (long*)(dev0+offset+0x25D);
+ Precharge_Register = *ptr & 0xFFFFFFFF;
-/* ------------------ Here the code for Timings detection ------------------ */
-/* ------------------------------------------------------------------------- */
+ ptr = (long*)(dev0+offset+0x252);
+ ACT_Register = *ptr & 0xFFFFFFFF;
-static void poll_timings_nf4ie(void) {
+ ptr = (long*)(dev0+offset+0x258);
+ Read_Register = *ptr & 0xFFFFFFFF;
+ ptr = (long*)(dev0+offset+0x244);
+ Misc_Register = *ptr & 0xFFFFFFFF;
- ulong regd0, reg8c, reg9c, reg80;
- int cas, rcd, rp, ras;
+ // On P45, check 1A8
+ if(Device_ID > 0x2E00) {
+ ptr = (long*)(dev0+offset+0x1A8);
+ Memory_Check = *ptr & 0xFFFFFFFF;
+ Memory_Check >>= 2;
+ Memory_Check &= 1;
+ Memory_Check = !Memory_Check;
+ } else {
+ ptr = (long*)(dev0+offset+0x1E8);
+ Memory_Check = *ptr & 0xFFFFFFFF;
+ }
- cprint(LINE_CPU+4, col +1, "- Type : DDR-II");
+ //Determine DDR-II or DDR-III
+ if (Memory_Check & 1) {
+ cprint(LINE_CPU+5, col +1, "- Type : DDR2");
+ } else {
+ cprint(LINE_CPU+5, col +1, "- Type : DDR3");
+ }
- //Now, read Registers
- pci_conf_read( 0, 1, 1, 0xD0, 4, ®d0);
- pci_conf_read( 0, 1, 1, 0x80, 1, ®80);
- pci_conf_read( 0, 1, 0, 0x8C, 4, ®8c);
- pci_conf_read( 0, 1, 0, 0x9C, 4, ®9c);
+ // CAS Latency (tCAS)
+ if(Device_ID > 0x2E00) {
+ cas = ((ODT_Control_Register >> 8)& 0x3F) - 6.0f;
+ } else {
+ cas = ((ODT_Control_Register >> 8)& 0x3F) - 9.0f;
+ }
- // Then, detect timings
- cas = (regd0 >> 4) & 0x7;
- rcd = (reg8c >> 24) & 0xF;
- rp = (reg9c >> 8) & 0xF;
- ras = (reg8c >> 16) & 0x3F;
+ // RAS-To-CAS (tRCD)
+ rcd = (Read_Register >> 17) & 0xF;
+
+ // RAS Precharge (tRP)
+ rp = (ACT_Register >> 13) & 0xF;
+
+ // RAS Active to precharge (tRAS)
+ ras = Precharge_Register & 0x3F;
print_timings_info(cas, rcd, rp, ras);
-
- if (reg80 & 0x3) {
- cprint(LINE_CPU+5, col2, "/ Dual Channel (128 bits)");
- } else {
- cprint(LINE_CPU+5, col2, "/ Single Channel (64 bits)");
+
+ cprint(LINE_CPU+6, col2+1, "/"); col2 +=2;
+
+ if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) {
+ cprint(LINE_CPU+6, col2+1, "Dual Channel");
+ } else {
+ cprint(LINE_CPU+6, col2+1, "Single Channel");
}
}
-static void poll_timings_i925(void) {
+static void poll_timings_wmr(void) {
- // Thanks for CDH optis
- ulong dev0, drt, drc, dcc, idetect, temp;
+ float cas;
+ int rcd, rp, ras;
+ ulong dev0, c0ckectrl, c1ckectrl, offset;
+ ulong ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register, MRC_Register;
long *ptr;
//Now, read MMR Base Address
- pci_conf_read( 0, 0, 0, 0x44, 4, &dev0);
- pci_conf_read( 0, 0, 0, 0x02, 2, &idetect);
+ pci_conf_read( 0, 0, 0, 0x48, 4, &dev0);
dev0 &= 0xFFFFC000;
- //Set pointer for DRT
- ptr=(long*)(dev0+0x114);
- drt = *ptr & 0xFFFFFFFF;
+ ptr = (long*)(dev0+0x260);
+ c0ckectrl = *ptr & 0xFFFFFFFF;
- //Set pointer for DRC
- ptr=(long*)(dev0+0x120);
- drc = *ptr & 0xFFFFFFFF;
+ ptr = (long*)(dev0+0x660);
+ c1ckectrl = *ptr & 0xFFFFFFFF;
+
+ // If DIMM 0 not populated, check DIMM 1
+ ((c0ckectrl) >> 20 & 0xF)?(offset = 0):(offset = 0x400);
- //Set pointer for DCC
- ptr=(long*)(dev0+0x200);
- dcc = *ptr & 0xFFFFFFFF;
+ ptr = (long*)(dev0+offset+0x265);
+ ODT_Control_Register = *ptr & 0xFFFFFFFF;
- //Determine DDR or DDR-II
- if ((drc & 3) == 2) {
- cprint(LINE_CPU+4, col +1, "- Type : DDR-II");
- } else {
- cprint(LINE_CPU+4, col +1, "- Type : DDR-I");
- }
+ ptr = (long*)(dev0+offset+0x25D);
+ Precharge_Register = *ptr & 0xFFFFFFFF;
- // Now, detect timings
- cprint(LINE_CPU+5, col2 +1, "/ CAS : ");
- col2 += 9;
+ ptr = (long*)(dev0+offset+0x252);
+ ACT_Register = *ptr & 0xFFFFFFFF;
- // CAS Latency (tCAS)
- temp = ((drt >> 8)& 0x3);
+ ptr = (long*)(dev0+offset+0x258);
+ Read_Register = *ptr & 0xFFFFFFFF;
- if ((drc & 3) == 2){
- // Timings DDR-II
- if (temp == 0x0) { cprint(LINE_CPU+5, col2, "5-"); }
- else if (temp == 0x1) { cprint(LINE_CPU+5, col2, "4-"); }
- else if (temp == 0x2) { cprint(LINE_CPU+5, col2, "3-"); }
- else { cprint(LINE_CPU+5, col2, "6-"); }
+ ptr = (long*)(dev0+offset+0x240);
+ MRC_Register = *ptr & 0xFFFFFFFF;
+
+ // CAS Latency (tCAS)
+ if(MRC_Register & 0xF) {
+ cas = (MRC_Register & 0xF) + 3.0f;
} else {
- // Timings DDR-I
- if (temp == 0x0) { cprint(LINE_CPU+5, col2, "3-"); }
- else if (temp == 0x1) { cprint(LINE_CPU+5, col2, "2.5-"); col2 +=2;}
- else { cprint(LINE_CPU+5, col2, "2-"); }
+ cas = ((ODT_Control_Register >> 8)& 0x3F) - 5.0f;
}
- col2 +=2;
// RAS-To-CAS (tRCD)
- dprint(LINE_CPU+5, col2, ((drt >> 4)& 0x3)+2, 1 ,0);
- cprint(LINE_CPU+5, col2+1, "-");
- col2 +=2;
+ rcd = (Read_Register >> 17) & 0xF;
// RAS Precharge (tRP)
- dprint(LINE_CPU+5, col2, (drt&0x3)+2, 1 ,0);
- cprint(LINE_CPU+5, col2+1, "-");
- col2 +=2;
+ rp = (ACT_Register >> 13) & 0xF;
// RAS Active to precharge (tRAS)
- // If Lakeport, than change tRAS computation (Thanks to CDH, again)
- if (idetect > 0x2700)
- temp = ((drt >> 19)& 0x1F);
- else
- temp = ((drt >> 20)& 0x0F);
-
- dprint(LINE_CPU+5, col2, temp , 1 ,0);
- (temp < 10)?(col2 += 1):(col2 += 2);
+ ras = Precharge_Register & 0x3F;
+
+ print_timings_info(cas, rcd, rp, ras);
- cprint(LINE_CPU+5, col2+1, "/"); col2 +=2;
+ cprint(LINE_CPU+6, col2+1, "/"); col2 +=2;
- temp = (dcc&0x3);
- if (temp == 1) { cprint(LINE_CPU+5, col2, " Dual Channel (Asymmetric)"); }
- else if (temp == 2) { cprint(LINE_CPU+5, col2, " Dual Channel (Interleaved)"); }
- else { cprint(LINE_CPU+5, col2, " Single Channel (64 bits)"); }
+ if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) {
+ cprint(LINE_CPU+6, col2+1, "Dual Channel");
+ } else {
+ cprint(LINE_CPU+6, col2+1, "Single Channel");
+ }
}
-static void poll_timings_i875(void) {
+static void poll_timings_snb(void) {
- ulong dev6, dev62;
- ulong temp;
float cas;
int rcd, rp, ras;
- long *ptr, *ptr2;
+ ulong dev0, offset;
+ ulong IMC_Register, MCMain0_Register, MCMain1_Register;
+ long *ptr;
- /* Read the MMR Base Address & Define the pointer */
- pci_conf_read( 0, 6, 0, 0x10, 4, &dev6);
+ //Now, read MMR Base Address
+ pci_conf_read( 0, 0, 0, 0x48, 4, &dev0);
+ dev0 &= 0xFFFFC000;
+
+ offset = 0x0000;
- /* Now, the PAT ritual ! (Kant and Luciano will love this) */
- pci_conf_read( 0, 6, 0, 0x40, 4, &dev62);
- ptr2=(long*)(dev6+0x68);
+ ptr = (long*)(dev0+offset+0x4000);
+ IMC_Register = *ptr & 0xFFFFFFFF;
- if ((dev62&0x3) == 0 && ((*ptr2 >> 14)&1) == 1) {
- cprint(LINE_CPU+4, col +1, "- PAT : Enabled");
+ // CAS Latency (tCAS)
+ cas = (float)((IMC_Register >> 8) & 0x0F);
+
+ // RAS-To-CAS (tRCD)
+ rcd = IMC_Register & 0x0F;
+
+ // RAS Precharge (tRP)
+ rp = (IMC_Register >> 4) & 0x0F;
+
+ // RAS Active to precharge (tRAS)
+ ras = (IMC_Register >> 16) & 0xFF;
+
+ print_timings_info(cas, rcd, rp, ras);
+
+ cprint(LINE_CPU+6, col2+1, "/"); col2 +=2;
+
+ // Channels
+ ptr = (long*)(dev0+offset+0x5004);
+ MCMain0_Register = *ptr & 0xFFFF;
+ ptr = (long*)(dev0+offset+0x5008);
+ MCMain1_Register = *ptr & 0xFFFF;
+
+ if(MCMain0_Register == 0 || MCMain1_Register == 0) {
+ cprint(LINE_CPU+6, col2+1, "Single Channel");
} else {
- cprint(LINE_CPU+4, col +1, "- PAT : Disabled");
+ cprint(LINE_CPU+6, col2+1, "Dual Channel");
}
- /* Now, we could check some additionnals timings infos) */
+}
+
+static void poll_timings_5400(void) {
+
+ // Thanks for CDH optis
+ ulong ambase, mtr1, mtr2, offset, mca, temp;
+ long *ptr;
+
+ //Hard-coded Ambase value (should not be realocated by software when using Memtest86+
+ ambase = 0xFE000000;
+ offset = mtr1 = mtr2 = 0;
+
+ // Will loop until a valid populated channel is found
+ // Bug : DIMM 0 must be populated or it will fall in an endless loop
+ while(((mtr2 & 0xF) < 3) || ((mtr2 & 0xF) > 6)) {
+ ptr = (long*)(ambase+0x378+offset);
+ mtr1 = *ptr & 0xFFFFFFFF;
+
+ ptr = (long*)(ambase+0x37C+offset);
+ mtr2 = *ptr & 0xFFFFFFFF;
+ offset += 0x8000;
+ }
+
+ pci_conf_read( 0, 16, 1, 0x58, 4, &mca);
+
+ //This chipset only supports FB-DIMM (Removed => too long)
+ //cprint(LINE_CPU+5, col +1, "- Type : FBD");
+
+ // Now, detect timings
+ cprint(LINE_CPU+6, col2 +1, "/ CAS : ");
+ col2 += 9;
- ptr=(long*)(dev6+0x60);
// CAS Latency (tCAS)
- temp = ((*ptr >> 5)& 0x3);
- if (temp == 0x0) { cas = 2.5; } else if (temp == 0x1) { cas = 2; } else { cas = 3; }
+ temp = mtr2 & 0xF;
+ dprint(LINE_CPU+6, col2, temp, 1 ,0);
+ cprint(LINE_CPU+6, col2+1, "-");
+ col2 += 2;
// RAS-To-CAS (tRCD)
- temp = ((*ptr >> 2)& 0x3);
- if (temp == 0x0) { rcd = 4; } else if (temp == 0x1) { rcd = 3; } else { rcd = 2; }
+ temp = 6 - ((mtr1 >> 10) & 3);
+ dprint(LINE_CPU+6, col2, temp, 1 ,0);
+ cprint(LINE_CPU+6, col2+1, "-");
+ col2 += 2;
// RAS Precharge (tRP)
- temp = (*ptr&0x3);
- if (temp == 0x0) { rp = 4; } else if (temp == 0x1) { rp = 3; } else { rp = 2; }
+ temp = 6 - ((mtr1 >> 8) & 3);
+ dprint(LINE_CPU+6, col2, temp, 1 ,0);
+ cprint(LINE_CPU+6, col2+1, "-");
+ col2 += 2;
// RAS Active to precharge (tRAS)
- temp = ((*ptr >> 7)& 0x7);
- ras = 10 - temp;
+ temp = 16 - (3 * ((mtr1 >> 29) & 3)) + ((mtr1 >> 12) & 3);
+ if(((mtr1 >> 12) & 3) == 3 && ((mtr1 >> 29) & 3) == 2) { temp = 9; }
- // Print timings
- print_timings_info(cas, rcd, rp, ras);
+ dprint(LINE_CPU+6, col2, temp, 1 ,0);
+ (temp < 10)?(col2 += 1):(col2 += 2);
- // Print 64 or 128 bits mode
- if (((*ptr2 >> 21)&3) > 0) {
- cprint(LINE_CPU+5, col2, "/ Dual Channel (128 bits)");
- } else {
- cprint(LINE_CPU+5, col2, "/ Single Channel (64 bits)");
+ cprint(LINE_CPU+6, col2+1, "/"); col2 +=2;
+
+ if ((mca >> 14) & 1) {
+ cprint(LINE_CPU+6, col2+1, "Single Channel");
+ } else {
+ cprint(LINE_CPU+6, col2+1, "Dual Channel");
}
+
}
static void poll_timings_E7520(void) {
@@ -1756,9 +2997,9 @@
print_timings_info(cas, rcd, rp, ras);
if ((ddrcsr & 0xF) >= 0xC) {
- cprint(LINE_CPU+5, col2, "/ Dual Channel (128 bits)");
+ cprint(LINE_CPU+6, col2, "/ Dual Channel (128 bits)");
} else {
- cprint(LINE_CPU+5, col2, "/ Single Channel (64 bits)");
+ cprint(LINE_CPU+6, col2, "/ Single Channel (64 bits)");
}
}
@@ -1770,31 +3011,31 @@
pci_conf_read( 0, 0, 0, 0x78, 4, &drt);
/* Now, we could print some additionnals timings infos) */
- cprint(LINE_CPU+5, col2 +1, "/ CAS : ");
+ cprint(LINE_CPU+6, col2 +1, "/ CAS : ");
col2 += 9;
// CAS Latency (tCAS)
temp = ((drt >> 4)&0x1);
- if (temp == 0x0) { cprint(LINE_CPU+5, col2, "2.5-"); col2 += 4; }
- else { cprint(LINE_CPU+5, col2, "2-"); col2 +=2; }
+ if (temp == 0x0) { cprint(LINE_CPU+6, col2, "2.5-"); col2 += 4; }
+ else { cprint(LINE_CPU+6, col2, "2-"); col2 +=2; }
// RAS-To-CAS (tRCD)
temp = ((drt >> 2)& 0x1);
- if (temp == 0x0) { cprint(LINE_CPU+5, col2, "3-"); }
- else { cprint(LINE_CPU+5, col2, "2-"); }
+ if (temp == 0x0) { cprint(LINE_CPU+6, col2, "3-"); }
+ else { cprint(LINE_CPU+6, col2, "2-"); }
col2 +=2;
// RAS Precharge (tRP)
temp = (drt&0x1);
- if (temp == 0x0) { cprint(LINE_CPU+5, col2, "3-"); }
- else { cprint(LINE_CPU+5, col2, "2-"); }
+ if (temp == 0x0) { cprint(LINE_CPU+6, col2, "3-"); }
+ else { cprint(LINE_CPU+6, col2, "2-"); }
col2 +=2;
// RAS Active to precharge (tRAS)
temp = 7-((drt >> 9)& 0x3);
- if (temp == 0x0) { cprint(LINE_CPU+5, col2, "7"); }
- if (temp == 0x1) { cprint(LINE_CPU+5, col2, "6"); }
- if (temp == 0x2) { cprint(LINE_CPU+5, col2, "5"); }
+ if (temp == 0x0) { cprint(LINE_CPU+6, col2, "7"); }
+ if (temp == 0x1) { cprint(LINE_CPU+6, col2, "6"); }
+ if (temp == 0x2) { cprint(LINE_CPU+6, col2, "5"); }
col2 +=1;
}
@@ -1818,9 +3059,9 @@
print_timings_info(cas, rcd, rp, ras);
if (((drc >> 22)&1) == 1) {
- cprint(LINE_CPU+5, col2, "/ Dual Channel (128 bits)");
+ cprint(LINE_CPU+6, col2, "/ Dual Channel (128 bits)");
} else {
- cprint(LINE_CPU+5, col2, "/ Single Channel (64 bits)");
+ cprint(LINE_CPU+6, col2, "/ Single Channel (64 bits)");
}
}
@@ -1832,34 +3073,34 @@
pci_conf_read( 0, 0, 1, 0x60, 4, &drt);
/* Now, we could print some additionnals timings infos) */
- cprint(LINE_CPU+5, col2 +1, "/ CAS : ");
+ cprint(LINE_CPU+6, col2 +1, "/ CAS : ");
col2 += 9;
// CAS Latency (tCAS)
temp = ((drt >> 5)&0x1);
- if (temp == 0x0) { cprint(LINE_CPU+5, col2, "2.5-"); col2 += 4; }
- else { cprint(LINE_CPU+5, col2, "2-"); col2 +=2; }
+ if (temp == 0x0) { cprint(LINE_CPU+6, col2, "2.5-"); col2 += 4; }
+ else { cprint(LINE_CPU+6, col2, "2-"); col2 +=2; }
// RAS-To-CAS (tRCD)
temp = ((drt >> 2)& 0x3);
- if (temp == 0x0) { cprint(LINE_CPU+5, col2, "4-"); }
- if (temp == 0x1) { cprint(LINE_CPU+5, col2, "3-"); }
- else { cprint(LINE_CPU+5, col2, "2-"); }
+ if (temp == 0x0) { cprint(LINE_CPU+6, col2, "4-"); }
+ if (temp == 0x1) { cprint(LINE_CPU+6, col2, "3-"); }
+ else { cprint(LINE_CPU+6, col2, "2-"); }
col2 +=2;
// RAS Precharge (tRP)
temp = (drt&0x3);
- if (temp == 0x0) { cprint(LINE_CPU+5, col2, "4-"); }
- if (temp == 0x1) { cprint(LINE_CPU+5, col2, "3-"); }
- else { cprint(LINE_CPU+5, col2, "2-"); }
+ if (temp == 0x0) { cprint(LINE_CPU+6, col2, "4-"); }
+ if (temp == 0x1) { cprint(LINE_CPU+6, col2, "3-"); }
+ else { cprint(LINE_CPU+6, col2, "2-"); }
col2 +=2;
// RAS Active to precharge (tRAS)
temp = ((drt >> 9)& 0x3);
- if (temp == 0x0) { cprint(LINE_CPU+5, col2, "8"); col2 +=7; }
- if (temp == 0x1) { cprint(LINE_CPU+5, col2, "7"); col2 +=6; }
- if (temp == 0x2) { cprint(LINE_CPU+5, col2, "6"); col2 +=5; }
- if (temp == 0x3) { cprint(LINE_CPU+5, col2, "5"); col2 +=5; }
+ if (temp == 0x0) { cprint(LINE_CPU+6, col2, "8"); col2 +=7; }
+ if (temp == 0x1) { cprint(LINE_CPU+6, col2, "7"); col2 +=6; }
+ if (temp == 0x2) { cprint(LINE_CPU+6, col2, "6"); col2 +=5; }
+ if (temp == 0x3) { cprint(LINE_CPU+6, col2, "5"); col2 +=5; }
col2 +=1;
}
@@ -1870,7 +3111,7 @@
int temp;
int trcd, trp, tras ;
- cprint(LINE_CPU+5, col2 +1, "/ CAS : ");
+ cprint(LINE_CPU+6, col2 +1, "/ CAS : ");
col2 += 9;
pci_conf_read(0, 24, 2, 0x88, 4, &dramtlr);
@@ -1881,36 +3122,36 @@
// CAS Latency (tCAS)
temp = (dramtlr & 0x7) + 1;
- dprint(LINE_CPU+5, col2, temp , 1 ,0);
- cprint(LINE_CPU+5, col2 +1, "-"); col2 +=2;
+ dprint(LINE_CPU+6, col2, temp , 1 ,0);
+ cprint(LINE_CPU+6, col2 +1, "-"); col2 +=2;
// RAS-To-CAS (tRCD)
trcd = ((dramtlr >> 4) & 0x3) + 3;
- dprint(LINE_CPU+5, col2, trcd , 1 ,0);
- cprint(LINE_CPU+5, col2 +1, "-"); col2 +=2;
+ dprint(LINE_CPU+6, col2, trcd , 1 ,0);
+ cprint(LINE_CPU+6, col2 +1, "-"); col2 +=2;
// RAS Precharge (tRP)
trp = ((dramtlr >> 8) & 0x3) + 3;
- dprint(LINE_CPU+5, col2, trp , 1 ,0);
- cprint(LINE_CPU+5, col2 +1, "-"); col2 +=2;
+ dprint(LINE_CPU+6, col2, trp , 1 ,0);
+ cprint(LINE_CPU+6, col2 +1, "-"); col2 +=2;
// RAS Active to precharge (tRAS)
tras = ((dramtlr >> 12) & 0xF) + 3;
if (tras < 10){
- dprint(LINE_CPU+5, col2, tras , 1 ,0); col2 += 1;
+ dprint(LINE_CPU+6, col2, tras , 1 ,0); col2 += 1;
} else {
- dprint(LINE_CPU+5, col2, tras , 2 ,0); col2 += 2;
+ dprint(LINE_CPU+6, col2, tras , 2 ,0); col2 += 2;
}
- cprint(LINE_CPU+5, col2+1, "/"); col2 +=2;
+ cprint(LINE_CPU+6, col2+1, "/"); col2 +=2;
// Print 64 or 128 bits mode
if ((dramclr >> 11)&1) {
- cprint(LINE_CPU+5, col2, " DDR-2 (128 bits)");
- col2 +=17;
- } else {
- cprint(LINE_CPU+5, col2, " DDR-2 (64 bits)");
+ cprint(LINE_CPU+6, col2, " DDR2 (128 bits)");
col2 +=16;
+ } else {
+ cprint(LINE_CPU+6, col2, " DDR2 (64 bits)");
+ col2 +=15;
}
} else {
@@ -1918,41 +3159,135 @@
// CAS Latency (tCAS)
temp = (dramtlr & 0x7);
- if (temp == 0x1) { cprint(LINE_CPU+5, col2, "2-"); col2 +=2; }
- if (temp == 0x2) { cprint(LINE_CPU+5, col2, "3-"); col2 +=2; }
- if (temp == 0x5) { cprint(LINE_CPU+5, col2, "2.5-"); col2 +=4; }
+ if (temp == 0x1) { cprint(LINE_CPU+6, col2, "2-"); col2 +=2; }
+ if (temp == 0x2) { cprint(LINE_CPU+6, col2, "3-"); col2 +=2; }
+ if (temp == 0x5) { cprint(LINE_CPU+6, col2, "2.5-"); col2 +=4; }
// RAS-To-CAS (tRCD)
trcd = ((dramtlr >> 12) & 0x7);
- dprint(LINE_CPU+5, col2, trcd , 1 ,0);
- cprint(LINE_CPU+5, col2 +1, "-"); col2 +=2;
+ dprint(LINE_CPU+6, col2, trcd , 1 ,0);
+ cprint(LINE_CPU+6, col2 +1, "-"); col2 +=2;
// RAS Precharge (tRP)
trp = ((dramtlr >> 24) & 0x7);
- dprint(LINE_CPU+5, col2, trp , 1 ,0);
- cprint(LINE_CPU+5, col2 +1, "-"); col2 +=2;
+ dprint(LINE_CPU+6, col2, trp , 1 ,0);
+ cprint(LINE_CPU+6, col2 +1, "-"); col2 +=2;
// RAS Active to precharge (tRAS)
tras = ((dramtlr >> 20) & 0xF);
if (tras < 10){
- dprint(LINE_CPU+5, col2, tras , 1 ,0); col2 += 1;
+ dprint(LINE_CPU+6, col2, tras , 1 ,0); col2 += 1;
} else {
- dprint(LINE_CPU+5, col2, tras , 2 ,0); col2 += 2;
+ dprint(LINE_CPU+6, col2, tras , 2 ,0); col2 += 2;
}
- cprint(LINE_CPU+5, col2+1, "/"); col2 +=2;
+ cprint(LINE_CPU+6, col2+1, "/"); col2 +=2;
// Print 64 or 128 bits mode
if (((dramclr >> 16)&1) == 1) {
- cprint(LINE_CPU+5, col2, " DDR-1 (128 bits)");
- col2 +=17;
- } else {
- cprint(LINE_CPU+5, col2, " DDR-1 (64 bits)");
+ cprint(LINE_CPU+6, col2, " DDR1 (128 bits)");
col2 +=16;
+ } else {
+ cprint(LINE_CPU+6, col2, " DDR1 (64 bits)");
+ col2 +=15;
}
}
}
+static void poll_timings_k10(void) {
+
+ ulong dramtlr, dramclr, dramchr;
+ ulong offset = 0;
+ int cas, rcd, rp, rc, ras;
+
+ pci_conf_read(0, 24, 2, 0x94, 4, &dramchr);
+
+ // If Channel A not enabled, switch to channel B
+ if(((dramchr>>14) & 0x1))
+ {
+ offset = 0x100;
+ pci_conf_read(0, 24, 2, 0x94+offset, 4, &dramchr);
+ }
+
+ pci_conf_read(0, 24, 2, 0x88+offset, 4, &dramtlr);
+ pci_conf_read(0, 24, 2, 0x110, 4, &dramclr);
+
+ // CAS Latency (tCAS)
+ if(((dramchr >> 8)&1) || ((dramchr & 0x7) == 0x4)){
+ // DDR3 or DDR2-1066
+ cas = (dramtlr & 0xF) + 4;
+ rcd = ((dramtlr >> 4) & 0x7) + 5;
+ rp = ((dramtlr >> 7) & 0x7) + 5;
+ ras = ((dramtlr >> 12) & 0xF) + 15;
+ rc = ((dramtlr >> 16) & 0x1F) + 11;
+ } else {
+ // DDR2-800 or less
+ cas = (dramtlr & 0xF) + 1;
+ rcd = ((dramtlr >> 4) & 0x3) + 3;
+ rp = ((dramtlr >> 8) & 0x3) + 3;
+ ras = ((dramtlr >> 12) & 0xF) + 3;
+ rc = ((dramtlr >> 16) & 0x1F) + 11;
+ }
+
+ print_timings_info(cas, rcd, rp, ras);
+
+ cprint(LINE_CPU+6, col2, "/"); col2++;
+
+ //Print DDR2 or DDR3
+ if ((dramchr >> 8)&1) {
+ cprint(LINE_CPU+6, col2+1, "DDR3");
+ } else {
+ cprint(LINE_CPU+6, col2+1, "DDR2");
+ }
+ col2 += 5;
+
+ // Print 64 or 128 bits mode
+ if ((dramclr >> 4)&1) {
+ cprint(LINE_CPU+6, col2+1, "(128 bits)");
+ } else {
+ cprint(LINE_CPU+6, col2+1, "(64 bits)");
+ }
+
+}
+
+static void poll_timings_k14(void) {
+
+ ulong dramt0, dramlow;
+ int cas, rcd, rp, rc, ras;
+
+ pci_conf_read(0, 24, 2, 0x88, 4, &dramlow);
+ pci_conf_write(0, 24, 2, 0xF0, 4, 0x00000040);
+ pci_conf_read(0, 24, 2, 0xF4, 4, &dramt0);
+
+ cas = (dramlow & 0xF) + 4;
+ rcd = (dramt0 & 0xF) + 5;
+ rp = ((dramt0 >> 8) & 0xF) + 5;
+ ras = ((dramt0 >> 16) & 0x1F) + 15;
+ rc = ((dramt0 >> 24) & 0x3F) + 16;
+
+ print_timings_info(cas, rcd, rp, ras);
+
+ cprint(LINE_CPU+6, col2, "/ DDR3 (64 bits)");
+
+}
+
+static void poll_timings_EP80579(void) {
+
+ ulong drt1, drt2;
+ float cas;
+ int rcd, rp, ras;
+
+ pci_conf_read( 0, 0, 0, 0x78, 4, &drt1);
+ pci_conf_read( 0, 0, 0, 0x64, 4, &drt2);
+
+ cas = ((drt1 >> 3) & 0x7) + 3;
+ rcd = ((drt1 >> 9) & 0x7) + 3;
+ rp = ((drt1 >> 6) & 0x7) + 3;
+ ras = ((drt2 >> 28) & 0xF) + 8;
+
+ print_timings_info(cas, rcd, rp, ras);
+}
+
static void poll_timings_nf2(void) {
ulong dramtlr, dramtlr2, dramtlr3, temp;
@@ -1965,47 +3300,124 @@
pci_conf_read(0, 0, 2, 0x44, 4, &dimm2p);
pci_conf_read(0, 0, 2, 0x48, 4, &dimm3p);
- cprint(LINE_CPU+5, col2 +1, "/ CAS : ");
+ cprint(LINE_CPU+6, col2 +1, "/ CAS : ");
col2 += 9;
// CAS Latency (tCAS)
temp = ((dramtlr2 >> 4) & 0x7);
- if (temp == 0x2) { cprint(LINE_CPU+5, col2, "2-"); col2 +=2; }
- if (temp == 0x3) { cprint(LINE_CPU+5, col2, "3-"); col2 +=2; }
- if (temp == 0x6) { cprint(LINE_CPU+5, col2, "2.5-"); col2 +=4; }
+ if (temp == 0x2) { cprint(LINE_CPU+6, col2, "2-"); col2 +=2; }
+ if (temp == 0x3) { cprint(LINE_CPU+6, col2, "3-"); col2 +=2; }
+ if (temp == 0x6) { cprint(LINE_CPU+6, col2, "2.5-"); col2 +=4; }
// RAS-To-CAS (tRCD)
temp = ((dramtlr >> 20) & 0xF);
- dprint(LINE_CPU+5, col2, temp , 1 ,0);
- cprint(LINE_CPU+5, col2 +1, "-"); col2 +=2;
+ dprint(LINE_CPU+6, col2, temp , 1 ,0);
+ cprint(LINE_CPU+6, col2 +1, "-"); col2 +=2;
// RAS Precharge (tRP)
temp = ((dramtlr >> 28) & 0xF);
- dprint(LINE_CPU+5, col2, temp , 1 ,0);
- cprint(LINE_CPU+5, col2 +1, "-"); col2 +=2;
+ dprint(LINE_CPU+6, col2, temp , 1 ,0);
+ cprint(LINE_CPU+6, col2 +1, "-"); col2 +=2;
// RAS Active to precharge (tRAS)
temp = ((dramtlr >> 15) & 0xF);
if (temp < 10){
- dprint(LINE_CPU+5, col2, temp , 1 ,0); col2 += 1;
+ dprint(LINE_CPU+6, col2, temp , 1 ,0); col2 += 1;
} else {
- dprint(LINE_CPU+5, col2, temp , 2 ,0); col2 += 2;
+ dprint(LINE_CPU+6, col2, temp , 2 ,0); col2 += 2;
}
- cprint(LINE_CPU+5, col2+1, "/"); col2 +=2;
+ cprint(LINE_CPU+6, col2+1, "/"); col2 +=2;
// Print 64 or 128 bits mode
// If DIMM1 & DIMM3 or DIMM1 & DIMM2 populated, than Dual Channel.
if ((dimm3p&1) + (dimm2p&1) == 2 || (dimm3p&1) + (dimm1p&1) == 2 ) {
- cprint(LINE_CPU+5, col2, " Dual Channel (128 bits)");
+ cprint(LINE_CPU+6, col2, " Dual Channel (128 bits)");
col2 +=24;
} else {
- cprint(LINE_CPU+5, col2, " Single Channel (64 bits)");
+ cprint(LINE_CPU+6, col2, " Single Channel (64 bits)");
col2 +=15;
}
}
+static void poll_timings_us15w(void) {
+
+ // Thanks for CDH optis
+ ulong dtr, temp;
+
+ /* Find dramratio */
+ /* D0 MsgRd, 01 Dunit, 01 DTR */
+ pci_conf_write(0, 0, 0, 0xD0, 4, 0xD0010100 );
+ pci_conf_read(0, 0, 0, 0xD4, 4, &dtr );
+
+ // Now, detect timings
+ cprint(LINE_CPU+5, col2 +1, "/ CAS : ");
+ col2 += 9;
+
+ // CAS Latency (tCAS)
+ temp = ((dtr >> 4) & 0x3) + 3;
+ dprint(LINE_CPU+5, col2, temp, 1 ,0);
+ cprint(LINE_CPU+5, col2+1, "-");
+ col2 += 2;
+
+ // RAS-To-CAS (tRCD)
+ temp = ((dtr >> 2) & 0x3) + 3;
+ dprint(LINE_CPU+5, col2, temp, 1 ,0);
+ cprint(LINE_CPU+5, col2+1, "-");
+ col2 += 2;
+
+ // RAS Precharge (tRP)
+ temp = ((dtr >> 0) & 0x3) + 3;
+ dprint(LINE_CPU+5, col2, temp, 1 ,0);
+ col2 += 1;
+
+}
+
+static void poll_timings_nhm(void) {
+
+ ulong mc_channel_bank_timing, mc_control, mc_channel_mrs_value;
+ float cas;
+ int rcd, rp, ras;
+ int fvc_bn = 4;
+
+ /* Find which channels are populated */
+ pci_conf_read(nhm_bus, 3, 0, 0x48, 2, &mc_control);
+ mc_control = (mc_control >> 8) & 0x7;
+
+ /* Get the first valid channel */
+ if(mc_control & 1) {
+ fvc_bn = 4;
+ } else if(mc_control & 2) {
+ fvc_bn = 5;
+ } else if(mc_control & 4) {
+ fvc_bn = 6;
+ }
+
+ // Now, detect timings
+ // CAS Latency (tCAS) / RAS-To-CAS (tRCD) / RAS Precharge (tRP) / RAS Active to precharge (tRAS)
+ pci_conf_read(nhm_bus, fvc_bn, 0, 0x88, 4, &mc_channel_bank_timing);
+ pci_conf_read(nhm_bus, fvc_bn, 0, 0x70, 4, &mc_channel_mrs_value);
+ cas = ((mc_channel_mrs_value >> 4) & 0xF ) + 4.0f;
+ rcd = (mc_channel_bank_timing >> 9) & 0xF;
+ ras = (mc_channel_bank_timing >> 4) & 0x1F;
+ rp = mc_channel_bank_timing & 0xF;
+
+ print_timings_info(cas, rcd, rp, ras);
+
+ // Print 1, 2 or 3 Channels
+ if (mc_control == 1 || mc_control == 2 || mc_control == 4 ) {
+ cprint(LINE_CPU+6, col2, "/ Single Channel");
+ col2 += 16;
+ } else if (mc_control == 7) {
+ cprint(LINE_CPU+6, col2, "/ Triple Channel");
+ col2 += 16;
+ } else {
+ cprint(LINE_CPU+6, col2, "/ Dual Channel");
+ col2 += 14;
+ }
+
+}
/* ------------------ Let's continue ------------------ */
@@ -2019,9 +3431,6 @@
{ 0x1022, 0x7006, "AMD 751", 0, poll_fsb_nothing, poll_timings_nothing, setup_amd751, poll_amd751 },
{ 0x1022, 0x700c, "AMD 762", 0, poll_fsb_nothing, poll_timings_nothing, setup_amd76x, poll_amd76x },
{ 0x1022, 0x700e, "AMD 761", 0, poll_fsb_nothing, poll_timings_nothing, setup_amd76x, poll_amd76x },
- { 0x1022, 0x0000, "AMD K8", 0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_amd64 },
- { 0x1022, 0x1100, "AMD 8000", 0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_amd64 },
- { 0x1022, 0x7454, "AMD 8000", 0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_amd64 },
/* SiS */
{ 0x1039, 0x0600, "SiS 600", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
@@ -2036,49 +3445,43 @@
{ 0x1039, 0x0735, "SiS 735", 0, poll_fsb_amd32, poll_timings_nothing, setup_nothing, poll_nothing },
{ 0x1039, 0x0740, "SiS 740", 0, poll_fsb_amd32, poll_timings_nothing, setup_nothing, poll_nothing },
{ 0x1039, 0x0745, "SiS 745", 0, poll_fsb_amd32, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x1039, 0x0755, "SiS 755", 0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_amd64 },
{ 0x1039, 0x0748, "SiS 748", 0, poll_fsb_amd32, poll_timings_nothing, setup_nothing, poll_nothing },
{ 0x1039, 0x0655, "SiS 655", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x1039, 0x0656, "SiS 656", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
{ 0x1039, 0x0648, "SiS 648", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x1039, 0x0649, "SiS 649", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
{ 0x1039, 0x0661, "SiS 661", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x1039, 0x0671, "SiS 671", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x1039, 0x0672, "SiS 672", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
/* ALi */
- { 0x10b9, 0x1531, "Aladdin 4", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x10b9, 0x1541, "Aladdin 5", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x10b9, 0x1531, "ALi Aladdin 4", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x10b9, 0x1541, "ALi Aladdin 5", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
{ 0x10b9, 0x1644, "ALi Aladdin M1644", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x10b9, 0x1687, "ALi M1687", 0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_amd64 },
- { 0x10b9, 0x1689, "ALi M1689", 0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_amd64 },
- { 0x10b9, 0x1695, "ALi M1695", 0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_amd64 },
/* ATi */
{ 0x1002, 0x5830, "ATi Radeon 9100 IGP", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
{ 0x1002, 0x5831, "ATi Radeon 9100 IGP", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
{ 0x1002, 0x5832, "ATi Radeon 9100 IGP", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
{ 0x1002, 0x5833, "ATi Radeon 9100 IGP", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x1002, 0x5954, "ATi Radeon xPress 200", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x1002, 0x5A41, "ATi Radeon xPress 200", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x1002, 0x5950, "ATi Radeon xPress 200", 0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_amd64 },
- { 0x1002, 0x5952, "ATi Radeon xPress 3200", 0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_amd64 },
+ { 0x1002, 0x5954, "ATi Radeon Xpress 200", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x1002, 0x5A41, "ATi Radeon Xpress 200", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
/* nVidia */
{ 0x10de, 0x01A4, "nVidia nForce", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
{ 0x10de, 0x01E0, "nVidia nForce2 SPP", 0, poll_fsb_nf2, poll_timings_nf2, setup_nothing, poll_nothing },
- { 0x10de, 0x00D1, "nVidia nForce3", 0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_amd64 },
- { 0x10de, 0x00E1, "nForce3 250", 0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_amd64 },
- { 0x10de, 0x005E, "nVidia nForce4", 0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_amd64 },
- { 0x10de, 0x005F, "nVidia nForce4", 0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_amd64 },
{ 0x10de, 0x0071, "nForce4 SLI Intel Edition", 0, poll_fsb_nf4ie, poll_timings_nf4ie, setup_nothing, poll_nothing },
/* VIA */
{ 0x1106, 0x0305, "VIA KT133/KT133A", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x1106, 0x0391, "vt8371", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x1106, 0x0501, "vt8501", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x1106, 0x0585, "vt82c585", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x1106, 0x0595, "vt82c595", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x1106, 0x0597, "vt82c597", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x1106, 0x0598, "VT82C598", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x1106, 0x0691, "VT82C691/693A/694X", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x1106, 0x0693, "VT82C693", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x1106, 0x0391, "VIA KX133", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x1106, 0x0501, "VIA MVP4", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x1106, 0x0585, "VIA VP/VPX", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x1106, 0x0595, "VIA VP2", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x1106, 0x0597, "VIA VP3", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x1106, 0x0598, "VIA MVP3", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x1106, 0x0691, "VIA Apollo Pro/133/133A", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x1106, 0x0693, "VIA Apollo Pro+", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
{ 0x1106, 0x0601, "VIA PLE133", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
{ 0x1106, 0x3099, "VIA KT266(A)/KT333", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
{ 0x1106, 0x3189, "VIA KT400(A)/600", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
@@ -2089,56 +3492,90 @@
{ 0x1106, 0x3123, "VIA CLE266", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
{ 0x1106, 0x0198, "VIA PT800", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
{ 0x1106, 0x3258, "VIA PT880", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x1106, 0x3188, "VIA K8T800", 0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_amd64 },
- { 0x1106, 0x0282, "VIA K8T800Pro", 0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_amd64 },
- { 0x1106, 0x3238, "VIA K8T890", 0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_amd64 },
/* Serverworks */
{ 0x1166, 0x0008, "CNB20HE", 0, poll_fsb_nothing, poll_timings_nothing, setup_cnb20, poll_nothing },
{ 0x1166, 0x0009, "CNB20LE", 0, poll_fsb_nothing, poll_timings_nothing, setup_cnb20, poll_nothing },
/* Intel */
- { 0x8086, 0x1130, "Intel i815", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x8086, 0x122d, "Intel i430fx", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x8086, 0x1237, "Intel i440fx", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x8086, 0x1250, "Intel i430hx", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x8086, 0x1A21, "Intel i840", 0, poll_fsb_nothing, poll_timings_nothing, setup_i840, poll_i840 },
- { 0x8086, 0x1A30, "Intel i845", 0, poll_fsb_p4, poll_timings_nothing, setup_i845, poll_i845 },
- { 0x8086, 0x2560, "Intel i845E/G/PE/GE", 0, poll_fsb_p4, poll_timings_nothing, setup_i845, poll_i845 },
- { 0x8086, 0x2500, "Intel i820", 0, poll_fsb_nothing, poll_timings_nothing, setup_i820, poll_i820 },
- { 0x8086, 0x2530, "Intel i850", 0, poll_fsb_p4, poll_timings_nothing, setup_i850, poll_i850 },
- { 0x8086, 0x2531, "Intel i860", 1, poll_fsb_nothing, poll_timings_nothing, setup_i860, poll_i860 },
- { 0x8086, 0x7030, "Intel i430vx", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x8086, 0x7120, "Intel i810", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x8086, 0x7122, "Intel i810", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x8086, 0x7124, "Intel i810e", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x8086, 0x7180, "Intel i440[le]x", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x8086, 0x7190, "Intel i440BX", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x8086, 0x7192, "Intel i440BX", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x8086, 0x71A0, "Intel i440gx", 0, poll_fsb_nothing, poll_timings_nothing, setup_i440gx, poll_i440gx },
- { 0x8086, 0x71A2, "Intel i440gx", 0, poll_fsb_nothing, poll_timings_nothing, setup_i440gx, poll_i440gx },
- { 0x8086, 0x84C5, "Intel i450gx", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x8086, 0x2540, "Intel E7500", 1, poll_fsb_p4, poll_timings_E750x, setup_iE7xxx, poll_iE7xxx },
- { 0x8086, 0x254C, "Intel E7501", 1, poll_fsb_p4, poll_timings_E750x, setup_iE7xxx, poll_iE7xxx },
- { 0x8086, 0x255d, "Intel E7205", 0, poll_fsb_p4, poll_timings_nothing, setup_iE7xxx, poll_iE7xxx },
- { 0x8086, 0x3592, "Intel E7320", 0, poll_fsb_p4, poll_timings_E7520, setup_iE7520, poll_iE7520 },
- { 0x8086, 0x2588, "Intel E7221", 1, poll_fsb_i925, poll_timings_i925, setup_i925, poll_iE7221 },
- { 0x8086, 0x3590, "Intel E7520", 0, poll_fsb_p4, poll_timings_E7520, setup_iE7520, poll_nothing },
- { 0x8086, 0x2600, "Intel E8500", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
- { 0x8086, 0x2570, "Intel i848/i865", 0, poll_fsb_i875, poll_timings_i875, setup_i875, poll_nothing },
- { 0x8086, 0x2578, "Intel i875P", 0, poll_fsb_i875, poll_timings_i875, setup_i875, poll_i875 },
- { 0x8086, 0x2550, "Intel E7505", 0, poll_fsb_p4, poll_timings_nothing, setup_iE7xxx, poll_iE7xxx },
- { 0x8086, 0x3580, "Intel ", 0, poll_fsb_i855, poll_timings_i852, setup_nothing, poll_nothing },
- { 0x8086, 0x3340, "Intel i855PM", 0, poll_fsb_i855, poll_timings_i855, setup_nothing, poll_nothing },
- { 0x8086, 0x2580, "Intel i915P/G", 0, poll_fsb_i925, poll_timings_i925, setup_i925, poll_nothing },
- { 0x8086, 0x2590, "Intel i915PM/GM", 0, poll_fsb_i925, poll_timings_i925, setup_i925, poll_nothing },
- { 0x8086, 0x2584, "Intel i925X/XE", 0, poll_fsb_i925, poll_timings_i925, setup_i925, poll_iE7221 },
- { 0x8086, 0x2770, "Intel i945P/G", 0, poll_fsb_i945, poll_timings_i925, setup_i925, poll_nothing },
- { 0x8086, 0x2774, "Intel i955X", 0, poll_fsb_i945, poll_timings_i925, setup_i925, poll_nothing},
- { 0x8086, 0x277C, "Intel i975X", 0, poll_fsb_i975, poll_timings_i925, setup_i925, poll_nothing},
- { 0x8086, 0x27A0, "Intel P965/G965", 0, poll_fsb_i965, poll_timings_i925, setup_i925, poll_nothing},
- { 0x8086, 0x2790, "Intel Q963/Q965", 0, poll_fsb_i965, poll_timings_i925, setup_i925, poll_nothing}
-};
+ { 0x8086, 0x1130, "Intel i815", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x8086, 0x122d, "Intel i430FX", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x8086, 0x1235, "Intel i430MX", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x8086, 0x1237, "Intel i440FX", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x8086, 0x1250, "Intel i430HX", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x8086, 0x1A21, "Intel i840", 0, poll_fsb_nothing, poll_timings_nothing, setup_i840, poll_i840 },
+ { 0x8086, 0x1A30, "Intel i845", 0, poll_fsb_p4, poll_timings_nothing, setup_i845, poll_i845 },
+ { 0x8086, 0x2560, "Intel i845E/G/PE/GE",0, poll_fsb_p4, poll_timings_nothing, setup_i845, poll_i845 },
+ { 0x8086, 0x2500, "Intel i820", 0, poll_fsb_nothing, poll_timings_nothing, setup_i820, poll_i820 },
+ { 0x8086, 0x2530, "Intel i850", 0, poll_fsb_p4, poll_timings_nothing, setup_i850, poll_i850 },
+ { 0x8086, 0x2531, "Intel i860", 1, poll_fsb_nothing, poll_timings_nothing, setup_i860, poll_i860 },
+ { 0x8086, 0x7030, "Intel i430VX", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x8086, 0x7100, "Intel i430TX", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x8086, 0x7120, "Intel i810", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x8086, 0x7122, "Intel i810", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x8086, 0x7124, "Intel i810E", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x8086, 0x7180, "Intel i440[LE]X", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x8086, 0x7190, "Intel i440BX", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x8086, 0x7192, "Intel i440BX", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x8086, 0x71A0, "Intel i440GX", 0, poll_fsb_nothing, poll_timings_nothing, setup_i440gx, poll_i440gx },
+ { 0x8086, 0x71A2, "Intel i440GX", 0, poll_fsb_nothing, poll_timings_nothing, setup_i440gx, poll_i440gx },
+ { 0x8086, 0x84C5, "Intel i450GX", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x8086, 0x2540, "Intel E7500", 1, poll_fsb_p4, poll_timings_E750x, setup_iE7xxx, poll_iE7xxx },
+ { 0x8086, 0x254C, "Intel E7501", 1, poll_fsb_p4, poll_timings_E750x, setup_iE7xxx, poll_iE7xxx },
+ { 0x8086, 0x255d, "Intel E7205", 0, poll_fsb_p4, poll_timings_nothing, setup_iE7xxx, poll_iE7xxx },
+ { 0x8086, 0x3592, "Intel E7320", 0, poll_fsb_p4, poll_timings_E7520, setup_iE7520, poll_iE7520 },
+ { 0x8086, 0x2588, "Intel E7221", 1, poll_fsb_i925, poll_timings_i925, setup_i925, poll_iE7221 },
+ { 0x8086, 0x3590, "Intel E7520", 0, poll_fsb_p4, poll_timings_E7520, setup_iE7520, poll_nothing },
+ { 0x8086, 0x2600, "Intel E8500", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
+ { 0x8086, 0x2570, "Intel i848/i865", 0, poll_fsb_i875, poll_timings_i875, setup_i875, poll_nothing },
+ { 0x8086, 0x2578, "Intel i875P", 0, poll_fsb_i875, poll_timings_i875, setup_i875, poll_i875 },
+ { 0x8086, 0x2550, "Intel E7505", 0, poll_fsb_p4, poll_timings_nothing, setup_iE7xxx, poll_iE7xxx },
+ { 0x8086, 0x3580, "Intel ", 0, poll_fsb_i855, poll_timings_i852, setup_nothing, poll_nothing },
+ { 0x8086, 0x3340, "Intel i855PM", 0, poll_fsb_i855, poll_timings_i855, setup_nothing, poll_nothing },
+ { 0x8086, 0x2580, "Intel i915P/G", 0, poll_fsb_i925, poll_timings_i925, setup_i925, poll_nothing },
+ { 0x8086, 0x2590, "Intel i915PM/GM", 0, poll_fsb_i925, poll_timings_i925, setup_i925, poll_nothing },
+ { 0x8086, 0x2584, "Intel i925X/XE", 0, poll_fsb_i925, poll_timings_i925, setup_i925, poll_iE7221 },
+ { 0x8086, 0x2770, "Intel i945P/G", 0, poll_fsb_i945, poll_timings_i925, setup_i925, poll_nothing },
+ { 0x8086, 0x27A0, "Intel i945GM/PM", 0, poll_fsb_i945, poll_timings_i925, setup_i925, poll_nothing },
+ { 0x8086, 0x27AC, "Intel i945GME", 0, poll_fsb_i945, poll_timings_i925, setup_i925, poll_nothing },
+ { 0x8086, 0x2774, "Intel i955X", 0, poll_fsb_i945, poll_timings_i925, setup_i925, poll_nothing},
+ { 0x8086, 0x277C, "Intel i975X", 0, poll_fsb_i975, poll_timings_i925, setup_i925, poll_nothing},
+ { 0x8086, 0x2970, "Intel i946PL/GZ", 0, poll_fsb_i965, poll_timings_i965, setup_p35, poll_nothing},
+ { 0x8086, 0x2990, "Intel Q963/Q965", 0, poll_fsb_i965, poll_timings_i965, setup_p35, poll_nothing},
+ { 0x8086, 0x29A0, "Intel P965/G965", 0, poll_fsb_i965, poll_timings_i965, setup_p35, poll_nothing},
+ { 0x8086, 0x2A00, "Intel GM965/GL960", 0, poll_fsb_im965, poll_timings_im965, setup_p35, poll_nothing},
+ { 0x8086, 0x2A10, "Intel GME965/GLE960",0, poll_fsb_im965, poll_timings_im965, setup_p35, poll_nothing},
+ { 0x8086, 0x2A40, "Intel PM/GM45/47", 0, poll_fsb_im965, poll_timings_im965, setup_p35, poll_nothing},
+ { 0x8086, 0x29B0, "Intel Q35", 0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing},
+ { 0x8086, 0x29C0, "Intel P35/G33", 0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing},
+ { 0x8086, 0x29D0, "Intel Q33", 0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing},
+ { 0x8086, 0x29E0, "Intel X38/X48", 0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing},
+ { 0x8086, 0x29F0, "Intel 3200/3210", 0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing},
+ { 0x8086, 0x2E10, "Intel Q45/Q43", 0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing},
+ { 0x8086, 0x2E20, "Intel P45/G45", 0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing},
+ { 0x8086, 0x2E30, "Intel G41", 0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing},
+ { 0x8086, 0x4001, "Intel 5400A", 0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing},
+ { 0x8086, 0x4003, "Intel 5400B", 0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing},
+ { 0x8086, 0x25D8, "Intel 5000P", 0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing},
+ { 0x8086, 0x25D4, "Intel 5000V", 0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing},
+ { 0x8086, 0x25C0, "Intel 5000X", 0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing},
+ { 0x8086, 0x25D0, "Intel 5000Z", 0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing},
+ { 0x8086, 0x5020, "Intel EP80579", 0, poll_fsb_p4, poll_timings_EP80579, setup_nothing, poll_nothing },
+ { 0x8086, 0x8100, "Intel US15W", 0, poll_fsb_us15w, poll_timings_us15w, setup_nothing, poll_nothing},
+ { 0x8086, 0x8101, "Intel UL11L/US15L", 0, poll_fsb_us15w, poll_timings_us15w, setup_nothing, poll_nothing},
+
+ /* Integrated Memory Controllers */
+ { 0xFFFF, 0x0001, "Core IMC", 0, poll_fsb_nhm, poll_timings_nhm, setup_nhm, poll_nothing},
+ { 0xFFFF, 0x0002, "Core IMC 32nm", 0, poll_fsb_nhm32, poll_timings_nhm, setup_nhm32, poll_nothing},
+ { 0xFFFF, 0x0003, "Core IMC 32nm", 0, poll_fsb_wmr, poll_timings_wmr, setup_wmr, poll_nothing},
+ { 0xFFFF, 0x0004, "SNB IMC 32nm", 0, poll_fsb_snb, poll_timings_snb, setup_wmr, poll_nothing},
+ { 0xFFFF, 0x0100, "AMD K8 IMC", 0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_amd64 },
+ { 0xFFFF, 0x0101, "AMD K10 IMC", 0, poll_fsb_k10, poll_timings_k10, setup_k10, poll_nothing },
+ { 0xFFFF, 0x0102, "AMD APU IMC", 0, poll_fsb_k14, poll_timings_k14, setup_nothing, poll_nothing },
+
+ /* Fail Safe */
+ { 0xFFFF, 0xFFFF, "", 0, poll_fsb_failsafe, poll_timings_nothing, setup_nothing, poll_nothing }
+};
static void print_memory_controller(void)
{
@@ -2154,32 +3591,32 @@
/* Print the controller name */
name = controllers[ctrl.index].name;
col = 10;
- cprint(LINE_CPU+4, col, name);
+ cprint(LINE_CPU+5, col, name);
/* Now figure out how much I just printed */
while(name[col - 10] != '\0') {
col++;
}
/* Now print the memory controller capabilities */
- cprint(LINE_CPU+4, col, " "); col++;
+ cprint(LINE_CPU+5, col, " "); col++;
if (ctrl.cap == ECC_UNKNOWN) {
return;
}
if (ctrl.cap & __ECC_DETECT) {
int on;
on = ctrl.mode & __ECC_DETECT;
- cprint(LINE_CPU+4, col, "(ECC : ");
- cprint(LINE_CPU+4, col +7, on?"Detect":"Disabled)");
+ cprint(LINE_CPU+5, col, "(ECC : ");
+ cprint(LINE_CPU+5, col +7, on?"Detect":"Disabled)");
on?(col += 13):(col += 16);
}
if (ctrl.mode & __ECC_CORRECT) {
int on;
on = ctrl.mode & __ECC_CORRECT;
- cprint(LINE_CPU+4, col, " / ");
+ cprint(LINE_CPU+5, col, " / ");
if (ctrl.cap & __ECC_CHIPKILL) {
- cprint(LINE_CPU+4, col +3, on?"Correct -":"");
+ cprint(LINE_CPU+5, col +3, on?"Correct -":"");
on?(col += 12):(col +=3);
} else {
- cprint(LINE_CPU+4, col +3, on?"Correct)":"");
+ cprint(LINE_CPU+5, col +3, on?"Correct)":"");
on?(col += 11):(col +=3);
}
}
@@ -2187,26 +3624,25 @@
if (ctrl.cap & __ECC_CHIPKILL) {
int on;
on = ctrl.mode & __ECC_CHIPKILL;
- cprint(LINE_CPU+4, col, " Chipkill : ");
- cprint(LINE_CPU+4, col +12, on?"On)":"Off)");
+ cprint(LINE_CPU+5, col, " Chipkill : ");
+ cprint(LINE_CPU+5, col +12, on?"On)":"Off)");
on?(col += 15):(col +=16);
}}
if (ctrl.mode & __ECC_SCRUB) {
int on;
on = ctrl.mode & __ECC_SCRUB;
- cprint(LINE_CPU+4, col, " Scrub");
- cprint(LINE_CPU+4, col +6, on?"+ ":"- ");
+ cprint(LINE_CPU+5, col, " Scrub");
+ cprint(LINE_CPU+5, col +6, on?"+ ":"- ");
col += 7;
}
if (ctrl.cap & __ECC_UNEXPECTED) {
int on;
on = ctrl.mode & __ECC_UNEXPECTED;
- cprint(LINE_CPU+4, col, "Unknown");
- cprint(LINE_CPU+4, col +7, on?"+ ":"- ");
+ cprint(LINE_CPU+5, col, "Unknown");
+ cprint(LINE_CPU+5, col +7, on?"+ ":"- ");
col += 9;
}
-
/* Print advanced caracteristics */
col2 = 0;
d = get_key();
@@ -2227,6 +3663,11 @@
int result;
result = pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, PCI_VENDOR_ID, 2, &vendor);
result = pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, PCI_DEVICE_ID, 2, &device);
+
+ // Detect IMC by CPUID
+ if(imc_type) { vendor = 0xFFFF; device = imc_type; }
+ if(fail_safe) { vendor = 0xFFFF; device = 0xFFFF; }
+
ctrl.index = 0;
if (result == 0) {
for(i = 1; i < sizeof(controllers)/sizeof(controllers[0]); i++) {
@@ -2236,9 +3677,6 @@
}
}
}
-
- // AMD K8 use integrated mem controller. If SB not detected, force detection
- if (ctrl.index == 0 && cpu_id.type == 15 && cpu_id.vend_id[0] == 'A') { ctrl.index = 4; }
controllers[ctrl.index].setup_ecc();
/* Don't enable ECC polling by default unless it has
|
|
[-]
[+]
|
Added |
memtest86+-4.20.tar.bz2/cpuid.c
^
|
| @@ -0,0 +1,258 @@
+/*
+ * cpuid.c --
+ *
+ * Implements CPUID querying functions
+ *
+ */
+#include "cpuid.h"
+
+cpuid_t cpuid_data0;
+cpuid_t cpuid_data80;
+
+unsigned num_logical_cpus = 1; // number of logical cpus per physical package
+unsigned num_cores_per_package = 1; // number of cores in each physical cpu package
+unsigned num_hyper_threads_per_core = 1; // number of hyper-threads per core
+
+void
+cpuid_get(unsigned n, cpuid_t *data)
+{
+ data->eax = n;
+ GET_CPUID(data->eax, data->ebx, data->ecx, data->edx);
+}
+
+
+/* cpuid_get_vendor_string ---
+ *
+ * This function gets the vendor string from the processor's cpuid instruction
+ * and passes it back to the caller in an easy to use structure.
+ */
+cpuid_vendor_string_t
+cpuid_get_vendor_string(void)
+{
+ static cpuid_vendor_string_t v;
+
+ /* Note: the string gets passed in EBX-EDX-ECX, not the intuitive order. */
+ v.uint32_array[0] = cpuid_data0.ebx;
+ v.uint32_array[1] = cpuid_data0.edx;
+ v.uint32_array[2] = cpuid_data0.ecx;
+ v.char_array[CPUID_VENDOR_STR_LENGTH-1] = '\0';
+ return v;
+}
+
+
+/* cpuid_get_version ---
+ *
+ * This function reads the processors version information using CPUID and puts
+ * it into a union for easy use by the caller.
+ */
+cpuid_version_t
+cpuid_get_version(void)
+{
+ cpuid_version_t v;
+ uint32_t junkEBX = 0, junkECX = 0, junkEDX = 0;
+ v.flat = 0x1;
+ GET_CPUID(v.flat, junkEBX, junkECX, junkEDX);
+ return v;
+}
+
+
+cpuid_feature_flags_t
+cpuid_get_feature_flags(void)
+{
+ cpuid_feature_flags_t f;
+ uint32_t junkEAX = 0x1, junkEBX = 0;
+ GET_CPUID(junkEAX, junkEBX, f.uint32_array[1], f.uint32_array[0]);
+ return f;
+}
+
+
+/*
+ *-----------------------------------------------------------------------------
+ *
+ * cpuid_get_ext_feature_flags --
+ *
+ * Passes back the caller the extended feature flags supported by
+ * this CPU. This can be used, among other things, to determine if the
+ * processor supports long mode.
+ *
+ * Results:
+ * Returns TRUE if the processor supports the extended feature flags
+ * CPUID node, and FALSE otherwise.
+ *
+ * Side effects:
+ * Calls CPUID a couple of times.
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+bool
+cpuid_get_ext_feature_flags(cpuid_ext_feature_flags_t *f) // OUT: Flags for this CPU
+{
+ uint32_t eax, ebx, ecx;
+
+ if (cpuid_data80.eax < 0x80000001) {
+ // Extended feature flags not supported on this CPU
+ return FALSE;
+ }
+ eax = CPUID_EXTENDED_FEATURE;
+ GET_CPUID(eax, ebx, ecx, f->flat);
+ return TRUE;
+}
+
+#define CHAR_TO_INT(a,b,c,d) ((a) + (b) * 0x100 + (c) * 0x10000 + (d) * 0x1000000)
+
+bool
+cpuid_is_vendor_amd(void)
+{
+ return cpuid_data0.ebx == CHAR_TO_INT('A', 'u', 't', 'h')
+ && cpuid_data0.edx == CHAR_TO_INT('e', 'n', 't', 'i')
+ && cpuid_data0.ecx == CHAR_TO_INT('c', 'A', 'M', 'D');
+}
+
+
+bool
+cpuid_is_vendor_intel(void)
+{
+ return cpuid_data0.ebx == CHAR_TO_INT('G', 'e', 'n', 'u')
+ && cpuid_data0.edx == CHAR_TO_INT('i', 'n', 'e', 'I')
+ && cpuid_data0.ecx == CHAR_TO_INT('n', 't', 'e', 'l');
+}
+
+
+/*
+ *-----------------------------------------------------------------------------
+ *
+ * cpuid_is_family_p4 --
+ *
+ * Returns TRUE if the processor we're running on is an Intel processor
+ * of the P4 family.
+ *
+ * Results:
+ * The obvious.
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+bool
+cpuid_is_family_p4(void)
+{
+ cpuid_version_t v = cpuid_get_version();
+
+ return cpuid_is_vendor_intel() && v.bits.family == CPUID_FAMILY_EXTENDED &&
+ v.bits.extendedFamily == CPUID_EXTENDED_FAMILY_PENTIUM4;
+}
+
+
+/*
+ *-----------------------------------------------------------------------------
+ *
+ * cpuid_is_family_p6 --
+ *
+ * Returns TRUE if the processor we're running on belongs to the P6 family.
+ *
+ * Results:
+ * The obvious.
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+bool
+cpuid_is_family_p6(void)
+{
+ cpuid_version_t v = cpuid_get_version();
+
+ return cpuid_is_vendor_intel() && v.bits.family == CPUID_FAMILY_P6;
+}
+
+
+/*
+ *-----------------------------------------------------------------------------
+ *
+ * cpuid_is_family_opteron --
+ *
+ * Returns TRUE if the processor we're running on belongs to the
+ * Opteron family.
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+bool
+cpuid_is_family_opteron(void)
+{
+ cpuid_version_t v = cpuid_get_version();
+ return cpuid_is_vendor_amd() && CPUID_FAMILY_IS_OPTERON(v.flat);
+}
+
+
+/*
+ *-----------------------------------------------------------------------------
+ *
+ * cpuid_init --
+ *
+ * Executes CPUID and caches values in cpuid_data0 abd cpuid_data80.
+ *
+ *-----------------------------------------------------------------------------
+ */
+void
+cpuid_init(void)
+{
+ //bool htt = FALSE;
+ cpuid_t id1;
+
+ /* First get the basic cpuid information on what the
+ * type of the processor is , i.e intel or amd etc
+ * and how much of extra cpuid information is available
+ * with the processor
+ */
+ cpuid_data0.eax = 0;
+ GET_CPUID(cpuid_data0.eax, cpuid_data0.ebx,
+ cpuid_data0.ecx, cpuid_data0.edx);
+
+
+ /* Find out if hyper-threading is available and there is more than one
+ * logical processor. See section 7.6.3 in Intel IA-32 volume III.
+ */
+ cpuid_get(1, &id1);
+
+ if (cpuid_is_vendor_intel()) {
+ if (cpuid_is_family_p6()) {
+ // Extended CPUID features not supported on PIII
+ return;
+ }
+ if (cpuid_is_family_p4()) {
+ /*
+ * Multi-core processors have the HT feature bit set (even if they
+ * don't support HT).
+ * The number of HT is the total number, not per-core number.
+ * The number of cores is off by 1, i.e. single-core reports 0.
+ */
+ //htt = id1.edx & CPUID_FEATURE_COMMON_ID1EDX_HT;
+ if (id1.edx & CPUID_FEATURE_COMMON_ID1EDX_HT) {
+ num_hyper_threads_per_core = (id1.ebx >> 16) & 0xff;
+ if (cpuid_max_func() >= 4) {
+ cpuid_t id4;
+ cpuid_get(4, &id4);
+ num_cores_per_package = ((id4.eax >> 26) & 0x3f) + 1;
+ num_hyper_threads_per_core /= num_cores_per_package;
+ }
+ }
+ }
+ } else if (cpuid_is_vendor_amd()) {
+ cpuid_data80.eax = 0x80000000;
+ GET_CPUID(cpuid_data80.eax, cpuid_data80.ebx,
+ cpuid_data80.ecx, cpuid_data80.edx);
+ if (cpuid_max_ext_func() >= 0x80000008) {
+ /* Number of cores is reported in extended function 0x80000008
+ * For legacy multi-core support, AMD CPUs report the number of
+ * cores as hyper-threads. Adjust the numbers to reflect that there
+ * are no threads.
+ */
+ cpuid_t id88;
+ cpuid_get(0x80000008, &id88);
+ num_cores_per_package = id88.ecx & 0xff;
+ num_hyper_threads_per_core = 1;
+ }
+ } else {
+ /* Unknown cpu type. we use the defaults */
+ }
+}
|
|
[-]
[+]
|
Added |
memtest86+-4.20.tar.bz2/cpuid.h
^
|
| @@ -0,0 +1,217 @@
+/*
+ * cpuid.h --
+ *
+ * contains the data structures required for CPUID
+ * implementation.
+ *
+ */
+
+#ifndef _CPUID_H_
+#define _CPUID_H_
+#include "stdint.h"
+#include "defs.h"
+#include "smp.h"
+
+#define CPUID_EXTENDED_BASE 0x80000000
+#define CPUID_EXTENDED_FEATURE 0x80000001
+#define CPUID_EXTENDED_BRAND1 0x80000002
+#define CPUID_EXTENDED_BRAND2 0x80000003
+#define CPUID_EXTENDED_BRAND3 0x80000004
+
+#define CPUID_VENDOR_LENGTH 3 /* 3 GPRs hold vendor ID */
+#define CPUID_VENDOR_STR_LENGTH (CPUID_VENDOR_LENGTH * sizeof(uint32_t) + 1)
+#define CPUID_BRAND_LENGTH 12 /* 12 GPRs hold vendor ID */
+#define CPUID_BRAND_STR_LENGTH (CPUID_BRAND_LENGTH * sizeof(uint32_t) + 1)
+
+#define CPUID_FAMILY(_eax) (((_eax) >> 8) & 0xf)
+/* Intel CPU Family */
+#define CPUID_FAMILY_486 4
+#define CPUID_FAMILY_P5 5
+#define CPUID_FAMILY_P6 6
+#define CPUID_FAMILY_EXTENDED 15
+
+#define CPUID_EXTENDED_FAMILY(_eax) (((_eax) >> 20) & 0xff)
+#define CPUID_EXTENDED_FAMILY_PENTIUM4 0
+#define CPUID_EXTENDED_FAMILY_OPTERON 0
+
+
+#define CPUID_FAMILY_IS_OPTERON(_eax) \
+ (CPUID_FAMILY(_eax) == CPUID_FAMILY_EXTENDED && \
+ CPUID_EXTENDED_FAMILY(_eax) == CPUID_EXTENDED_FAMILY_OPTERON)
+#define CPUID_FEATURE_COMMON_ID1EDX_HT 0x10000000 /* 28 */
+
+
+typedef struct {
+ uint32_t eax;
+ uint32_t ebx;
+ uint32_t ecx;
+ uint32_t edx;
+} cpuid_t;
+
+/* cached CPUID data for CPUID(0) and CPUID(0x80000000) */
+extern cpuid_t cpuid_data0;
+extern cpuid_t cpuid_data80;
+
+
+static inline unsigned
+cpuid_max_func()
+{
+ return cpuid_data0.eax;
+}
+
+
+static inline unsigned
+cpuid_max_ext_func()
+{
+ return cpuid_data80.eax;
+}
+
+
+/* Typedef for storing the CPUID Vendor String */
+typedef union {
+ /* Note: the extra byte in the char array is for '\0'. */
+ char char_array[CPUID_VENDOR_STR_LENGTH];
+ uint32_t uint32_array[CPUID_VENDOR_LENGTH];
+} cpuid_vendor_string_t;
+
+/* Typedef for storing the CPUID Brand String */
+typedef union {
+ /* Note: the extra byte in the char array is for '\0'. */
+ char char_array[CPUID_BRAND_STR_LENGTH];
+ uint32_t uint32_array[CPUID_BRAND_LENGTH];
+} cpuid_brand_string_t;
+
+/* Typedef for storing CPUID Version */
+typedef union {
+ uint32_t flat;
+ struct {
+ uint32_t stepping:4; /* Bit 0 */
+ uint32_t model:4;
+ uint32_t family:4;
+ uint32_t processorType:2;
+ uint32_t reserved1514:2;
+ uint32_t extendedModel:4;
+ uint32_t extendedFamily:8;
+ uint32_t reserved3128:4; /* Bit 31 */
+ } bits;
+} cpuid_version_t;
+
+/* Typedef for storing CPUID Processor Information */
+typedef union {
+ uint32_t flat;
+ struct {
+ uint32_t brandIndex:8; /* Bit 0 */
+ uint32_t cflushLineSize:8;
+ uint32_t logicalProcessorCount:8;
+ uint32_t apicID:8; /* Bit 31 */
+ } bits;
+} cpuid_proc_info_t;
+
+/* Typedef for storing CPUID Feature flags */
+typedef union {
+ uint64_t flat;
+ uint32_t uint32_array[2];
+ struct {
+ uint32_t fpu:1; /* Bit 0 */
+ uint32_t vme:1;
+ uint32_t de:1;
+ uint32_t pse:1;
+ uint32_t tsc:1;
+ uint32_t msr:1;
+ uint32_t pae:1;
+ uint32_t mce:1;
+ uint32_t cx8:1;
+ uint32_t apic:1;
+ uint32_t reserved10:1;
+ uint32_t sep:1;
+ uint32_t mtrr:1;
+ uint32_t pge:1;
+ uint32_t mca:1;
+ uint32_t cmov:1;
+ uint32_t pat:1;
+ uint32_t pse36:1;
+ uint32_t psn:1;
+ uint32_t cflush:1;
+ uint32_t reserved20:1;
+ uint32_t ds:1;
+ uint32_t acpi:1;
+ uint32_t mmx:1;
+ uint32_t fxsr:1;
+ uint32_t sse:1;
+ uint32_t sse2:1;
+ uint32_t ss:1;
+ uint32_t htt:1;
+ uint32_t tm:1;
+ uint32_t reserved30:1;
+ uint32_t pbe:1; /* Bit 31 */
+ uint32_t sse3:1; /* Bit 32 */
+ uint32_t reserved3433:2;
+ uint32_t monitor:1;
+ uint32_t dscpl:1;
+ uint32_t reserved3937:3;
+ uint32_t tm2:1;
+ uint32_t reserved41:1;
+ uint32_t cnxtid:1;
+ uint32_t reserved4443:2;
+ uint32_t cmpxchg16b:1;
+ uint32_t reserved6346:18; /* Bit 63 */
+ } bits;
+} cpuid_feature_flags_t;
+
+/* Feature flags returned by extended CPUID node function 8000_0001. */
+typedef union {
+ uint64_t flat;
+ uint32_t uint32_array[2];
+ struct {
+ uint32_t fpu:1; /* Bit 0 */
+ uint32_t vme:1;
+ uint32_t de:1;
+ uint32_t pse:1;
+ uint32_t tsc:1;
+ uint32_t msr:1;
+ uint32_t pae:1;
+ uint32_t mce:1;
+ uint32_t cx8:1;
+ uint32_t apic:1;
+ uint32_t reserved10:1;
+ uint32_t sep:1;
+ uint32_t mtrr:1;
+ uint32_t pge:1;
+ uint32_t mca:1;
+ uint32_t cmov:1;
+ uint32_t pat:1;
+ uint32_t pse36:1;
+ uint32_t reserved1918:2;
+ uint32_t nx:1;
+ uint32_t reserved21:1;
+ uint32_t mmxamd:1;
+ uint32_t mmx:1;
+ uint32_t fxsr:1;
+ uint32_t ffxsr:1;
+ uint32_t reserved26:1;
+ uint32_t rdtscp:1;
+ uint32_t reserved28:1;
+ uint32_t lm:1;
+ uint32_t threedeenowext:1;
+ uint32_t threedeenow:1; /* Bit 31 */
+ uint32_t lahf:1; /* Bit 32 */
+ uint32_t cmplegacy:1;
+ uint32_t reserved3534:2;
+ uint32_t cr8avail:1;
+ uint32_t reserved6337:27; /* Bit 63 */
+ } bits;
+} cpuid_ext_feature_flags_t;
+
+void cpuid_get(unsigned n, cpuid_t *data);
+cpuid_vendor_string_t cpuid_get_vendor_string(void);
+cpuid_version_t cpuid_get_version(void);
+cpuid_feature_flags_t cpuid_get_feature_flags(void);
+bool cpuid_get_ext_feature_flags(cpuid_ext_feature_flags_t *f);
+bool cpuid_is_vendor_amd(void);
+bool cpuid_is_vendor_intel(void);
+bool cpuid_is_family_p6(void);
+bool cpuid_is_family_p4(void);
+bool cpuid_is_family_opteron(void);
+void cpuid_init(void);
+
+#endif
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/defs.h
^
|
| @@ -13,7 +13,6 @@
* so the build process should be more robust.
*/
#define LOW_TEST_ADR 0x00002000 /* Final adrs for test code */
-#define HIGH_TEST_ADR 0x00200000 /* Relocation base address */
#define BOOTSEG 0x07c0 /* Segment adrs for inital boot */
#define INITSEG 0x9000 /* Segment adrs for relocated boot */
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/dmi.c
^
|
| @@ -5,8 +5,7 @@
*
* Release under the GPL version 2
* ----------------------------------------------------
- * Memtest86+ V1.70 - Added compliance with SMBIOS Spec V2.5
- * - Support for FB-DIMM
+ * Memtest86+ V4.00 - Added compliance with SMBIOS Spec V2.6.1
*/
@@ -14,9 +13,6 @@
#include <stdint.h>
-#define DMI_SEARCH_START 0x0000F000
-#define DMI_SEARCH_LENGTH 0x000F0FFF
-#define MAX_DMI_MEMDEVS 32
#define round_up(x,y) (((x) + (y) - 1) & ~((y)-1))
#define round_down(x,y) ((x) & ~((y)-1))
@@ -92,11 +88,13 @@
"SODIMM", "SRIMM", "FB-DIMM"
};
+
static char *memory_types[] = {
"?",
"Other", "Unknown", "DRAM", "EDRAM", "VRAM", "SRAM", "RAM",
"ROM", "FLASH", "EEPROM", "FEPROM", "EPROM", "CDRAM", "3DRAM",
- "SDRAM", "SGRAM", "RDRAM", "DDR", "DDR2", "DDR2 FB"
+ "SDRAM", "SGRAM", "RDRAM", "DDR", "DDR2", "DDR2 FB", "RSVD",
+ "RSVD","RSVD","DDR3","FBD2"
};
@@ -104,8 +102,8 @@
int mem_devs_count=0;
struct md_map * md_maps[MAX_DMI_MEMDEVS];
int md_maps_count=0;
-int bad_devs[MAX_DMI_MEMDEVS];
-int dmi_initialized=0;
+int dmi_err_cnts[MAX_DMI_MEMDEVS];
+short dmi_initialized=0;
int strlen(char * string){
int i=0;
@@ -176,7 +174,9 @@
struct tstruct_header *header = (struct tstruct_header *)dmi;
if (header->type == 17)
mem_devs[mem_devs_count++]=(struct mem_dev *)dmi;
- if (header->type == 20)
+
+ // Need fix (SMBIOS/DDR3)
+ if (header->type == 20 || header->type == 1)
md_maps[md_maps_count++]=(struct md_map *)dmi;
dmi+=header->length;
while( ! (*dmi == 0 && *(dmi+1) == 0 ) )
@@ -192,7 +192,7 @@
void init_dmi(void){
int i;
for(i=0; i < MAX_DMI_MEMDEVS; i++)
- bad_devs[i]=0;
+ dmi_err_cnts[i]=0;
open_dmi();
dmi_initialized=1;
}
@@ -271,7 +271,7 @@
of += 12;
}
if (!mapped)
- cprint(yof+1, POP2_X+17, "No mapping (unused device)");
+ cprint(yof+1, POP2_X+17, "No mapping (Interleaved Device)");
}
@@ -296,10 +296,10 @@
for(j=0; j < mem_devs_count; j++){
if (mem_devs[j]->header.handle != md_maps[i]->md_handle)
continue;
- if (bad_devs[j]){
+ if (dmi_err_cnts[j]){
found=0;
}else{
- found = bad_devs[j] = 1;
+ found = dmi_err_cnts[j] = 1;
}
}
}
@@ -316,7 +316,7 @@
cprint(v->msg_line, 0,"Bad Memory Devices: ");
of=20;
for ( i=count=0; i < MAX_DMI_MEMDEVS; i++){
- if (!bad_devs[i])
+ if (!dmi_err_cnts[i])
continue;
struct mem_dev *md = mem_devs[i];
if(count++){
|
|
[-]
[+]
|
Added |
memtest86+-4.20.tar.bz2/error.c
^
|
| @@ -0,0 +1,561 @@
+
+/* error.c - MemTest-86 Version 3.4
+ *
+ * Released under version 2 of the Gnu Public License.
+ * By Chris Brady, cbrady@sgi.com
+ * ----------------------------------------------------
+ * MemTest86+ V4.00 Specific code (GPL V2.0)
+ * By Samuel DEMEULEMEESTER, sdemeule@memtest.org
+ * http://www.canardpc.com - http://www.memtest.org
+ */
+
+#include "test.h"
+#include "config.h"
+#include <sys/io.h>
+#include "dmi.h"
+#define NULL 0
+
+extern int test_ticks, nticks, beepmode;
+extern struct tseq tseq[];
+extern int dmi_err_cnts[MAX_DMI_MEMDEVS];
+extern short dmi_initialized;
+void poll_errors();
+
+static void update_err_counts(void);
+static void print_err_counts(void);
+static int syn, chan, len=1;
+
+/*
+ * Print an individual error
+ */
+void common_err( ulong *adr, ulong good, ulong bad, ulong xor, int type)
+{
+ int i, n, x, j, flag=0;
+ ulong page, offset;
+ int patnchg;
+ ulong mb;
+
+ update_err_counts();
+ add_dmi_err((ulong)adr);
+
+ switch(v->printmode) {
+ case PRINTMODE_SUMMARY:
+ /* Don't do anything for a parity error. */
+ if (type == 3) {
+ return;
+ }
+
+ /* Address error */
+ if (type == 1) {
+ xor = good ^ bad;
+ }
+
+ /* Ecc correctable errors */
+ if (type == 2) {
+ /* the bad value is the corrected flag */
+ if (bad) {
+ v->erri.cor_err++;
+ }
+ page = (ulong)adr;
+ offset = good;
+ } else {
+ page = page_of(adr);
+ offset = (ulong)adr & 0xFFF;
+ }
+
+ /* Calc upper and lower error addresses */
+ if (v->erri.low_addr.page > page) {
+ v->erri.low_addr.page = page;
+ v->erri.low_addr.offset = offset;
+ flag++;
+ } else if (v->erri.low_addr.page == page &&
+ v->erri.low_addr.offset > offset) {
+ v->erri.low_addr.offset = offset;
+ v->erri.high_addr.offset = offset;
+ flag++;
+ } else if (v->erri.high_addr.page < page) {
+ v->erri.high_addr.page = page;
+ flag++;
+ }
+ if (v->erri.high_addr.page == page &&
+ v->erri.high_addr.offset < offset) {
+ v->erri.high_addr.offset = offset;
+ flag++;
+ }
+
+ /* Calc bits in error */
+ for (i=0, n=0; i<32; i++) {
+ if (xor>>i & 1) {
+ n++;
+ }
+ }
+ v->erri.tbits += n;
+ if (n > v->erri.max_bits) {
+ v->erri.max_bits = n;
+ flag++;
+ }
+ if (n < v->erri.min_bits) {
+ v->erri.min_bits = n;
+ flag++;
+ }
+ if (v->erri.ebits ^ xor) {
+ flag++;
+ }
+ v->erri.ebits |= xor;
+
+ /* Calc max contig errors */
+ len = 1;
+ if ((ulong)adr == (ulong)v->erri.eadr+4 ||
+ (ulong)adr == (ulong)v->erri.eadr-4 ) {
+ len++;
+ }
+ if (len > v->erri.maxl) {
+ v->erri.maxl = len;
+ flag++;
+ }
+ v->erri.eadr = (ulong)adr;
+
+ if (v->erri.hdr_flag == 0) {
+ clear_scroll();
+ cprint(LINE_HEADER+0, 1, "Error Confidence Value:");
+ cprint(LINE_HEADER+1, 1, " Lowest Error Address:");
+ cprint(LINE_HEADER+2, 1, " Highest Error Address:");
+ cprint(LINE_HEADER+3, 1, " Bits in Error Mask:");
+ cprint(LINE_HEADER+4, 1, " Bits in Error - Total:");
+ cprint(LINE_HEADER+4, 29, "Min: Max: Avg:");
+ cprint(LINE_HEADER+5, 1, " Max Contiguous Errors:");
+ cprint(LINE_HEADER+6, 1, "ECC Correctable Errors:");
+ cprint(LINE_HEADER+7, 1, "Errors per Memory Slot:");
+ x = 24;
+ if (dmi_initialized) {
+ for ( i=0; i < MAX_DMI_MEMDEVS;){
+ n = LINE_HEADER+7;
+ for (j=0; j<4; j++) {
+ if (dmi_err_cnts[i] >= 0) {
+ dprint(n, x, i, 2, 0);
+ cprint(n, x+2, ": 0");
+ }
+ i++;
+ n++;
+ }
+ x += 10;
+ }
+ }
+
+ cprint(LINE_HEADER+0, 64, "Test Errors");
+ v->erri.hdr_flag++;
+ }
+ if (flag) {
+ /* Calc bits in error */
+ for (i=0, n=0; i<32; i++) {
+ if (v->erri.ebits>>i & 1) {
+ n++;
+ }
+ }
+ page = v->erri.low_addr.page;
+ offset = v->erri.low_addr.offset;
+ mb = page >> 8;
+ hprint(LINE_HEADER+1, 25, page);
+ hprint2(LINE_HEADER+1, 33, offset, 3);
+ cprint(LINE_HEADER+1, 36, " - . MB");
+ dprint(LINE_HEADER+1, 39, mb, 5, 0);
+ dprint(LINE_HEADER+1, 45, ((page & 0xFF)*10)/256, 1, 0);
+ page = v->erri.high_addr.page;
+ offset = v->erri.high_addr.offset;
+ mb = page >> 8;
+ hprint(LINE_HEADER+2, 25, page);
+ hprint2(LINE_HEADER+2, 33, offset, 3);
+ cprint(LINE_HEADER+2, 36, " - . MB");
+ dprint(LINE_HEADER+2, 39, mb, 5, 0);
+ dprint(LINE_HEADER+2, 45, ((page & 0xFF)*10)/256, 1, 0);
+ hprint(LINE_HEADER+3, 25, v->erri.ebits);
+ dprint(LINE_HEADER+4, 25, n, 2, 1);
+ dprint(LINE_HEADER+4, 34, v->erri.min_bits, 2, 1);
+ dprint(LINE_HEADER+4, 42, v->erri.max_bits, 2, 1);
+ dprint(LINE_HEADER+4, 50, v->erri.tbits/v->ecount, 2, 1);
+ dprint(LINE_HEADER+5, 25, v->erri.maxl, 7, 1);
+ x = 28;
+ for ( i=0; i < MAX_DMI_MEMDEVS;){
+ n = LINE_HEADER+7;
+ for (j=0; j<4; j++) {
+ if (dmi_err_cnts[i] > 0) {
+ dprint (n, x, dmi_err_cnts[i], 7, 1);
+ }
+ i++;
+ n++;
+ }
+ x += 10;
+ }
+
+ for (i=0; tseq[i].msg != NULL; i++) {
+ dprint(LINE_HEADER+1+i, 66, i, 2, 0);
+ dprint(LINE_HEADER+1+i, 68, tseq[i].errors, 8, 0);
+ }
+ }
+ if (v->erri.cor_err) {
+ dprint(LINE_HEADER+6, 25, v->erri.cor_err, 8, 1);
+ }
+ break;
+
+ case PRINTMODE_ADDRESSES:
+ /* Don't display duplicate errors */
+ if ((ulong)adr == (ulong)v->erri.eadr &&
+ xor == v->erri.exor) {
+ return;
+ }
+ if (v->erri.hdr_flag == 0) {
+ clear_scroll();
+ cprint(LINE_HEADER, 0,
+"Tst Pass Failing Address Good Bad Err-Bits Count Chan");
+ cprint(LINE_HEADER+1, 0,
+"--- ---- ----------------------- -------- -------- -------- ----- ----");
+ v->erri.hdr_flag++;
+ }
+ /* Check for keyboard input */
+ check_input();
+ scroll();
+
+ if ( type == 2 || type == 3) {
+ page = (ulong)adr;
+ offset = good;
+ } else {
+ page = page_of(adr);
+ offset = ((unsigned long)adr) & 0xFFF;
+ }
+ mb = page >> 8;
+ dprint(v->msg_line, 0, v->test, 3, 0);
+ dprint(v->msg_line, 4, v->pass, 5, 0);
+ hprint(v->msg_line, 11, page);
+ hprint2(v->msg_line, 19, offset, 3);
+ cprint(v->msg_line, 22, " - . MB");
+ dprint(v->msg_line, 25, mb, 5, 0);
+ dprint(v->msg_line, 31, ((page & 0xFF)*10)/256, 1, 0);
+
+ if (type == 3) {
+ /* ECC error */
+ cprint(v->msg_line, 36,
+ bad?"corrected ": "uncorrected ");
+ hprint2(v->msg_line, 60, syn, 4);
+ cprint(v->msg_line, 68, "ECC");
+ dprint(v->msg_line, 74, chan, 2, 0);
+ } else if (type == 2) {
+ cprint(v->msg_line, 36, "Parity error detected ");
+ } else {
+ hprint(v->msg_line, 36, good);
+ hprint(v->msg_line, 46, bad);
+ hprint(v->msg_line, 56, xor);
+ dprint(v->msg_line, 66, v->ecount, 5, 0);
+ v->erri.exor = xor;
+ }
+ v->erri.eadr = (ulong)adr;
+ print_err_counts();
+ break;
+
+ case PRINTMODE_PATTERNS:
+ if (v->erri.hdr_flag == 0) {
+ clear_scroll();
+ v->erri.hdr_flag++;
+ }
+ /* Do not do badram patterns from test 0 or 5 */
+ if (v->test == 0 || v->test == 5) {
+ return;
+ }
+ /* Only do patterns for data errors */
+ if ( type != 0) {
+ return;
+ }
+ /* Process the address in the pattern administration */
+ patnchg=insertaddress ((ulong) adr);
+ if (patnchg) {
+ printpatn();
+ }
+ break;
+
+ case PRINTMODE_NONE:
+ if (v->erri.hdr_flag == 0) {
+ clear_scroll();
+ v->erri.hdr_flag++;
+ }
+ break;
+ }
+}
+
+/*
+ * Display data error message. Don't display duplicate errors.
+ */
+void error(ulong *adr, ulong good, ulong bad)
+{
+ ulong xor;
+
+ xor = good ^ bad;
+#ifdef USB_WAR
+ /* Skip any errrors that appear to be due to the BIOS using location
+ * 0x4e0 for USB keyboard support. This often happens with Intel
+ * 810, 815 and 820 chipsets. It is possible that we will skip
+ * a real error but the odds are very low.
+ */
+ if ((ulong)adr == 0x4e0 || (ulong)adr == 0x410) {
+ return;
+ }
+#endif
+ common_err(adr, good, bad, xor, 0);
+}
+
+/*
+ * Display address error message.
+ * Since this is strictly an address test, trying to create BadRAM
+ * patterns does not make sense. Just report the error.
+ */
+void ad_err1(ulong *adr1, ulong *mask, ulong bad, ulong good)
+{
+ common_err(adr1, good, bad, (ulong)mask, 1);
+}
+
+/*
+ * Display address error message.
+ * Since this type of address error can also report data errors go
+ * ahead and generate BadRAM patterns.
+ */
+void ad_err2(ulong *adr, ulong bad)
+{
+ common_err(adr, (ulong)adr, bad, ((ulong)adr) ^ bad, 0);
+}
+
+static void update_err_counts(void)
+{
+ if (beepmode){
+ beep(600);
+ beep(1000);
+ }
+
+ if (v->pass && v->ecount == 0) {
+ cprint(LINE_MSG, COL_MSG,
+ " ");
+ }
+ ++(v->ecount);
+ tseq[v->test].errors++;
+
+}
+
+static void print_err_counts(void)
+{
+ int i;
+ char *pp;
+
+ if ((v->ecount > 4096) && (v->ecount % 256 != 0)) return;
+
+ dprint(LINE_INFO, COL_ERR, v->ecount, 6, 0);
+ dprint(LINE_INFO, COL_ECC_ERR, v->ecc_ecount, 6, 0);
+
+ /* Paint the error messages on the screen red to provide a vivid */
+ /* indicator that an error has occured */
+ if ((v->printmode == PRINTMODE_ADDRESSES ||
+ v->printmode == PRINTMODE_PATTERNS) &&
+ v->msg_line < 24) {
+ for(i=0, pp=(char *)((SCREEN_ADR+v->msg_line*160+1));
+ i<76; i++, pp+=2) {
+ *pp = 0x47;
+ }
+ }
+}
+
+
+/*
+ * Print an ecc error
+ */
+void print_ecc_err(unsigned long page, unsigned long offset,
+ int corrected, unsigned short syndrome, int channel)
+{
+ ++(v->ecc_ecount);
+ syn = syndrome;
+ chan = channel;
+ common_err((ulong *)page, offset, corrected, 0, 2);
+}
+
+#ifdef PARITY_MEM
+/*
+ * Print a parity error message
+ */
+void parity_err( unsigned long edi, unsigned long esi)
+{
+ unsigned long addr;
+
+ if (v->test == 5) {
+ addr = esi;
+ } else {
+ addr = edi;
+ }
+ common_err((ulong *)addr, addr & 0xFFF, 0, 0, 3);
+}
+#endif
+
+/*
+ * Print the pattern array as a LILO boot option addressing BadRAM support.
+ */
+void printpatn (void)
+{
+ int idx=0;
+ int x;
+
+ /* Check for keyboard input */
+ check_input();
+
+ if (v->numpatn == 0)
+ return;
+
+ scroll();
+
+ cprint (v->msg_line, 0, "badram=");
+ x=7;
+
+ for (idx = 0; idx < v->numpatn; idx++) {
+
+ if (x > 80-22) {
+ scroll();
+ x=7;
+ }
+ cprint (v->msg_line, x, "0x");
+ hprint (v->msg_line, x+2, v->patn[idx].adr );
+ cprint (v->msg_line, x+10, ",0x");
+ hprint (v->msg_line, x+13, v->patn[idx].mask);
+ if (idx+1 < v->numpatn)
+ cprint (v->msg_line, x+21, ",");
+ x+=22;
+ }
+}
+
+/*
+ * Show progress by displaying elapsed time and update bar graphs
+ */
+void do_tick(void)
+{
+ int i, n, pct;
+ ulong h, l, t;
+
+ /* FIXME only print serial error messages from the tick handler */
+ if (v->ecount) {
+ print_err_counts();
+ }
+
+ nticks++;
+ v->total_ticks++;
+
+ if (test_ticks) {
+ pct = 100*nticks/test_ticks;
+ if (pct > 100) {
+ pct = 100;
+ }
+ } else {
+ pct = 0;
+ }
+
+ dprint(1, COL_MID+4, pct, 3, 0);
+ i = (BAR_SIZE * pct) / 100;
+ while (i > v->tptr) {
+ if (v->tptr >= BAR_SIZE) {
+ break;
+ }
+ cprint(1, COL_MID+9+v->tptr, "#");
+ v->tptr++;
+ }
+
+ if (v->pass_ticks) {
+ pct = 100*v->total_ticks/v->pass_ticks;
+ if (pct > 100) { pct = 100; }
+ } else {
+ pct = 0;
+ }
+ dprint(0, COL_MID+4, pct, 3, 0);
+ i = (BAR_SIZE * pct) / 100;
+ while (i > v->pptr) {
+ if (v->pptr >= BAR_SIZE) {
+ break;
+ }
+ cprint(0, COL_MID+9+v->pptr, "#");
+ v->pptr++;
+ }
+
+ if (v->ecount && v->printmode == PRINTMODE_SUMMARY) {
+ /* Compute confidence score */
+ pct = 0;
+
+ /* If there are no errors within 1mb of start - end addresses */
+ h = v->pmap[v->msegs - 1].end - 0x100;
+ if (v->erri.low_addr.page > 0x100 &&
+ v->erri.high_addr.page < h) {
+ pct += 8;
+ }
+
+ /* Errors for only some tests */
+ if (v->pass) {
+ for (i=0, n=0; tseq[i].msg != NULL; i++) {
+ if (tseq[i].errors == 0) {
+ n++;
+ }
+ }
+ pct += n*3;
+ } else {
+ for (i=0, n=0; i<v->test; i++) {
+ if (tseq[i].errors == 0) {
+ n++;
+ }
+ }
+ pct += n*2;
+
+ }
+
+ /* Only some bits in error */
+ n = 0;
+ if (v->erri.ebits & 0xf) n++;
+ if (v->erri.ebits & 0xf0) n++;
+ if (v->erri.ebits & 0xf00) n++;
+ if (v->erri.ebits & 0xf000) n++;
+ if (v->erri.ebits & 0xf0000) n++;
+ if (v->erri.ebits & 0xf00000) n++;
+ if (v->erri.ebits & 0xf000000) n++;
+ if (v->erri.ebits & 0xf0000000) n++;
+ pct += (8-n)*2;
+
+ /* Adjust the score */
+ pct = pct*100/22;
+/*
+ if (pct > 100) {
+ pct = 100;
+ }
+*/
+ dprint(LINE_HEADER+0, 25, pct, 3, 1);
+ }
+
+
+ /* We can't do the elapsed time unless the rdtsc instruction
+ * is supported
+ */
+ if (v->rdtsc) {
+ asm __volatile__(
+ "rdtsc":"=a" (l),"=d" (h));
+ asm __volatile__ (
+ "subl %2,%0\n\t"
+ "sbbl %3,%1"
+ :"=a" (l), "=d" (h)
+ :"g" (v->startl), "g" (v->starth),
+ "0" (l), "1" (h));
+ t = h * ((unsigned)0xffffffff / v->clks_msec) / 1000;
+ t += (l / v->clks_msec) / 1000;
+ i = t % 60;
+ dprint(LINE_TIME, COL_TIME+9, i%10, 1, 0);
+ dprint(LINE_TIME, COL_TIME+8, i/10, 1, 0);
+ t /= 60;
+ i = t % 60;
+ dprint(LINE_TIME, COL_TIME+6, i % 10, 1, 0);
+ dprint(LINE_TIME, COL_TIME+5, i / 10, 1, 0);
+ t /= 60;
+ dprint(LINE_TIME, COL_TIME, t, 4, 0);
+ }
+
+
+ /* Check for keyboard input */
+ check_input();
+
+ /* Poll for ECC errors */
+ poll_errors();
+}
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/head.S
^
|
| @@ -30,6 +30,23 @@
#define X86_CACHE 24
#define X86_PWRCAP 40
#define X86_EXT 44
+#define X86_FFL 48
+#define X86_DCACHE0_EAX 52
+#define X86_DCACHE0_EBX 56
+#define X86_DCACHE0_ECX 60
+#define X86_DCACHE0_EDX 64
+#define X86_DCACHE1_EAX 68
+#define X86_DCACHE1_EBX 72
+#define X86_DCACHE1_ECX 76
+#define X86_DCACHE1_EDX 80
+#define X86_DCACHE2_EAX 84
+#define X86_DCACHE2_EBX 88
+#define X86_DCACHE2_ECX 92
+#define X86_DCACHE2_EDX 96
+#define X86_DCACHE3_EAX 100
+#define X86_DCACHE3_EBX 104
+#define X86_DCACHE3_ECX 108
+#define X86_DCACHE3_EDX 112
.code32
.globl startup_32
@@ -345,7 +362,8 @@
# CDH end
#
- movl %eax, X86_EXT(%esi) #save complete extended CPUID to X86_EXT
+ movl %eax, X86_EXT(%esi) # save complete extended CPUID to X86_EXT
+ movl %ecx, X86_FFL(%esi) # save ECX Feature Flags to X86_FFL
movb %al, %cl # save reg for future use
andb $0x0f, %ah # mask processor family
movb %ah, X86(%esi)
@@ -371,6 +389,37 @@
movl %ebx, X86_CACHE+4(%esi)
movl %ecx, X86_CACHE+8(%esi)
movl %edx, X86_CACHE+12(%esi)
+# Grab deterministic cache information (for 32nm Intel CPU)
+ cmpw $0x0000,%dx
+ jne id_done
+ movl $4, %eax
+ movl $0, %ecx
+ cpuid
+ movl %eax, X86_DCACHE0_EAX(%esi)
+ movl %ebx, X86_DCACHE0_EBX(%esi)
+ movl %ecx, X86_DCACHE0_ECX(%esi)
+ movl %edx, X86_DCACHE0_EDX(%esi)
+ movl $4, %eax
+ movl $1, %ecx
+ cpuid
+ movl %eax, X86_DCACHE1_EAX(%esi)
+ movl %ebx, X86_DCACHE1_EBX(%esi)
+ movl %ecx, X86_DCACHE1_ECX(%esi)
+ movl %edx, X86_DCACHE1_EDX(%esi)
+ movl $4, %eax
+ movl $2, %ecx
+ cpuid
+ movl %eax, X86_DCACHE2_EAX(%esi)
+ movl %ebx, X86_DCACHE2_EBX(%esi)
+ movl %ecx, X86_DCACHE2_ECX(%esi)
+ movl %edx, X86_DCACHE2_EDX(%esi)
+ movl $4, %eax
+ movl $3, %ecx
+ cpuid
+ movl %eax, X86_DCACHE3_EAX(%esi)
+ movl %ebx, X86_DCACHE3_EBX(%esi)
+ movl %ecx, X86_DCACHE3_ECX(%esi)
+ movl %edx, X86_DCACHE3_EDX(%esi)
jmp id_done
not_intel:
@@ -385,6 +434,7 @@
movl $0x80000006,%eax # Use the CPUID instruction to get cache info
cpuid
movl %ecx,X86_CACHE+8(%esi)
+ movl %edx,X86_CACHE+12(%esi)
movl $0x80000007,%eax # Use the CPUID instruction to get AMD Powercap
cpuid
movl %edx,X86_PWRCAP(%esi)
@@ -977,6 +1027,6 @@
.bss
.balign 16
stack:
- . = . + 4096
+ . = . + 8192
stack_top:
.previous
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/init.c
^
|
| @@ -3,9 +3,9 @@
* Released under version 2 of the Gnu Public License.
* By Chris Brady, cbrady@sgi.com
* ----------------------------------------------------
- * MemTest86+ V1.70 Specific code (GPL V2.0)
+ * MemTest86+ V4.20 Specific code (GPL V2.0)
* By Samuel DEMEULEMEESTER, sdemeule@memtest.org
- * http://www.x86-secret.com - http://www.memtest.org
+ * http://www.canardpc.com - http://www.memtest.org
*/
#include "test.h"
@@ -14,21 +14,81 @@
#include "controller.h"
#include "pci.h"
#include "io.h"
+#include "spd.h"
+#define rdmsr(msr,val1,val2) \
+ __asm__ __volatile__("rdmsr" \
+ : "=a" (val1), "=d" (val2) \
+ : "c" (msr))
+
+extern struct tseq tseq[];
extern short memsz_mode;
extern short firmware;
-int beepmode;
+extern short dmi_initialized;
+extern int dmi_err_cnts[MAX_DMI_MEMDEVS];
struct cpu_ident cpu_id;
ulong st_low, st_high;
ulong end_low, end_high;
ulong cal_low, cal_high;
ulong extclock;
+unsigned long imc_type = 0;
+
+int l1_cache, l2_cache, l3_cache;
+int tsc_invariable = 0;
-static ulong memspeed(ulong src, ulong len, int iter);
+ulong memspeed(ulong src, ulong len, int iter, int type);
static void cpu_type(void);
static void cacheable(void);
static int cpuspeed(void);
+int beepmode, fail_safe;
+
+/* Failsafe function */
+/* msec: number of ms to wait - scs: scancode expected to stop */
+void failsafe(int msec, int scs)
+{
+ int ip;
+ ulong sh, sl, l, h, t;
+ unsigned char c;
+
+ cprint(18, 22, "Press *F1* to enter Fail-Safe Mode");
+
+ ip = 0;
+ /* save the starting time */
+ asm __volatile__(
+ "rdtsc":"=a" (sl),"=d" (sh));
+
+ /* loop for n seconds */
+ while (1) {
+ asm __volatile__(
+ "rdtsc":"=a" (l),"=d" (h));
+ asm __volatile__ (
+ "subl %2,%0\n\t"
+ "sbbl %3,%1"
+ :"=a" (l), "=d" (h)
+ :"g" (sl), "g" (sh),
+ "0" (l), "1" (h));
+
+ t = h * ((unsigned)0xffffffff / v->clks_msec);
+ t += (l / v->clks_msec);
+
+ /* Is the time up? */
+ if (t >= msec) {
+ cprint(18, 22, " ");
+ break;
+ }
+
+ /* Is expected Scan code pressed? */
+ c = get_key();
+ c &= 0x7f;
+
+ if(c == scs) {
+ fail_safe = 1;
+ cprint(18, 22, " ");
+ break;
+ }
+ }
+}
static void display_init(void)
{
@@ -52,7 +112,7 @@
for(i=0, pp=(char *)(SCREEN_ADR+1); i<TITLE_WIDTH; i++, pp+=2) {
*pp = 0x20;
}
- cprint(0, 0, " Memtest86 v1.70 ");
+ cprint(0, 0, " Memtest86 v4.20 ");
for(i=0, pp=(char *)(SCREEN_ADR+1); i<2; i++, pp+=30) {
*pp = 0xA4;
@@ -73,7 +133,7 @@
void init(void)
{
int i;
-
+
outb(0x8, 0x3f2); /* Kill Floppy Motor */
/* Turn on cache */
@@ -81,6 +141,7 @@
/* Setup the display */
display_init();
+
/* Determine the memory map */
if ((firmware == FIRMWARE_UNKNOWN) &&
@@ -102,21 +163,55 @@
beepmode = BEEP_MODE;
v->test = 0;
+ v->pass = 0;
+ v->msg_line = 0;
+ v->ecount = 0;
+ v->ecc_ecount = 0;
v->testsel = -1;
v->msg_line = LINE_SCROLL-1;
v->scroll_start = v->msg_line * 160;
+ v->erri.low_addr.page = 0x7fffffff;
+ v->erri.low_addr.offset = 0xfff;
+ v->erri.high_addr.page = 0;
+ v->erri.high_addr.offset = 0;
+ v->erri.min_bits = 32;
+ v->erri.max_bits = 0;
+ v->erri.min_bits = 32;
+ v->erri.max_bits = 0;
+ v->erri.maxl = 0;
+ v->erri.cor_err = 0;
+ v->erri.ebits = 0;
+ v->erri.hdr_flag = 0;
+ v->erri.tbits = 0;
+ for (i=0; tseq[i].msg != 0; i++) {
+ tseq[i].errors = 0;
+ }
+ if (dmi_initialized) {
+ for (i=0; i < MAX_DMI_MEMDEVS; i++){
+ if (dmi_err_cnts[i] > 0) {
+ dmi_err_cnts[i] = 0;
+ }
+ }
+ }
cprint(LINE_CPU+1, 0, "L1 Cache: Unknown ");
cprint(LINE_CPU+2, 0, "L2 Cache: Unknown ");
- cprint(LINE_CPU+3, 0, "Memory : ");
- aprint(LINE_CPU+3, 10, v->test_pages);
- cprint(LINE_CPU+4, 0, "Chipset : ");
+ cprint(LINE_CPU+3, 0, "L3 Cache: None ");
+ cprint(LINE_CPU+4, 0, "Memory : |-------------------------------------------------");
+ aprint(LINE_CPU+4, 10, v->test_pages);
+ cprint(LINE_CPU+5, 0, "Chipset : ");
cpu_type();
- /* Find the memory controller (inverted from standard) */
+ /* Check fail safe */
+ failsafe(2000, 0x3B);
+
+ /* Find the memory controller */
find_controller();
+ /* Find Memory Specs */
+ if(fail_safe == 0) { get_spd_spec(); }
+
if (v->rdtsc) {
cacheable();
cprint(LINE_TIME, COL_TIME+4, ": :");
@@ -132,14 +227,17 @@
cprint(LINE_INFO, COL_PASS, " 0");
cprint(LINE_INFO, COL_ERR, " 0");
cprint(LINE_INFO+1, 0, " -----------------------------------------------------------------------------");
+
for(i=0; i < 5; i++) {
cprint(i, COL_MID-2, "| ");
}
footer();
+ // Default Print Mode
+ // v->printmode=PRINTMODE_SUMMARY;
v->printmode=PRINTMODE_ADDRESSES;
v->numpatn=0;
- find_ticks();
+
}
#define FLAT 0
@@ -283,7 +381,7 @@
void cpu_type(void)
{
int i, off=0;
- int l1_cache=0, l2_cache=0;
+ int l1_cache=0, l2_cache=0, l3_cache=0;
ulong speed;
v->rdtsc = 0;
@@ -400,6 +498,14 @@
l2_cache = (cpu_id.cache_info[11] << 8);
l2_cache += cpu_id.cache_info[10];
break;
+ case 10:
+ cprint(LINE_CPU, 0, "AMD Geode LX");
+ off = 12;
+ l1_cache = cpu_id.cache_info[3];
+ l1_cache += cpu_id.cache_info[7];
+ l2_cache = (cpu_id.cache_info[11] << 8);
+ l2_cache += cpu_id.cache_info[10];
+ break;
case 13:
cprint(LINE_CPU, 0, "AMD K6-III+");
off = 11;
@@ -466,55 +572,86 @@
break;
case 15:
l1_cache = cpu_id.cache_info[3];
- l1_cache += cpu_id.cache_info[7];
l2_cache = (cpu_id.cache_info[11] << 8);
l2_cache += cpu_id.cache_info[10];
- switch(cpu_id.model) {
- default:
- cprint(LINE_CPU, 0, "AMD K8");
- off = 6;
- break;
- case 1:
- case 5:
- if (((cpu_id.ext >> 16) & 0xF) != 0) {
- cprint(LINE_CPU, 0, "AMD Opteron (0.09)");
- } else {
- cprint(LINE_CPU, 0, "AMD Opteron (0.13)");
- }
- off = 18;
- break;
- case 3:
- case 11:
- cprint(LINE_CPU, 0, "Athlon 64 X2");
- off = 12;
- break;
- case 8:
- cprint(LINE_CPU, 0, "Turion 64 X2");
- off = 12;
- break;
- case 4:
- case 7:
- case 9:
- case 12:
- case 14:
- case 15:
- if (((cpu_id.ext >> 16) & 0xF) != 0) {
- if (l2_cache > 256) {
- cprint(LINE_CPU, 0, "Athlon 64 (0.09)");
+ imc_type = 0x0100;
+ if(((cpu_id.ext >> 16) & 0xFF) < 0x10) {
+ // Here if CPUID.EXT < 0x10h (old K8/K10)
+ switch(cpu_id.model) {
+ default:
+ cprint(LINE_CPU, 0, "AMD K8");
+ off = 6;
+ break;
+ case 1:
+ case 5:
+ if (((cpu_id.ext >> 16) & 0xF) != 0) {
+ cprint(LINE_CPU, 0, "AMD Opteron (0.09)");
} else {
- cprint(LINE_CPU, 0, "Sempron (0.09)");
+ cprint(LINE_CPU, 0, "AMD Opteron (0.13)");
}
- } else {
- if (l2_cache > 256) {
- cprint(LINE_CPU, 0, "Athlon 64 (0.13)");
+ off = 18;
+ break;
+ case 3:
+ case 11:
+ cprint(LINE_CPU, 0, "Athlon 64 X2");
+ off = 12;
+ break;
+ case 8:
+ cprint(LINE_CPU, 0, "Turion 64 X2");
+ off = 12;
+ break;
+ case 4:
+ case 7:
+ case 12:
+ case 14:
+ case 15:
+ if (((cpu_id.ext >> 16) & 0xF) != 0) {
+ if (l2_cache > 256) {
+ cprint(LINE_CPU, 0, "Athlon 64 (0.09)");
+ } else {
+ cprint(LINE_CPU, 0, "Sempron (0.09)");
+ }
} else {
- cprint(LINE_CPU, 0, "Sempron (0.13)");
- }
+ if (l2_cache > 256) {
+ cprint(LINE_CPU, 0, "Athlon 64 (0.13)");
+ } else {
+ cprint(LINE_CPU, 0, "Sempron (0.13)");
+ }
+ }
+ off = 16;
+ break;
}
- off = 16;
break;
+ } else {
+ // Here if CPUID.EXT >= 0x10h (new K10)
+ l3_cache = (cpu_id.cache_info[15] << 8);
+ l3_cache += (cpu_id.cache_info[14] >> 2);
+ l3_cache *= 512;
+ switch(cpu_id.model) {
+ case 1:
+ imc_type = 0x0102;
+ cprint(LINE_CPU, 0, "AMD Fusion @");
+ off = 12;
+ break;
+ default:
+ case 2:
+ imc_type = 0x0101;
+ cprint(LINE_CPU, 0, "AMD K10 (65nm) @");
+ off = 16;
+ break;
+ case 4:
+ imc_type = 0x0101;
+ cprint(LINE_CPU, 0, "AMD K10 (45nm) @");
+ off = 16;
+ break;
+ case 9:
+ imc_type = 0x0101;
+ cprint(LINE_CPU, 0, "AMD Magny-Cours");
+ off = 15;
+ break;
+ }
+ break;
}
- break;
}
break;
@@ -580,18 +717,20 @@
case 0x6:
case 0xa:
case 0x66:
- l1_cache += 8;
+ l1_cache = 8;
break;
case 0x8:
case 0xc:
case 0x67:
case 0x60:
- l1_cache += 16;
+ l1_cache = 16;
break;
+ case 0x9:
+ case 0xd:
case 0x68:
case 0x2c:
case 0x30:
- l1_cache += 32;
+ l1_cache = 32;
break;
case 0x40:
l2_cache = 0;
@@ -605,10 +744,12 @@
case 0x3a:
l2_cache = 192;
break;
+ case 0x21:
case 0x42:
case 0x7a:
case 0x82:
case 0x3c:
+ case 0x3f:
l2_cache = 256;
break;
case 0x3d:
@@ -620,6 +761,7 @@
case 0x86:
case 0x3e:
case 0x7f:
+ case 0x80:
l2_cache = 512;
break;
case 0x44:
@@ -634,11 +776,100 @@
case 0x85:
l2_cache = 2048;
break;
+ case 0x48:
+ l2_cache = 3072;
+ break;
case 0x49:
l2_cache = 4096;
break;
+ case 0x4e:
+ l2_cache = 6144;
+ break;
+ case 0x22:
+ case 0xd0:
+ l3_cache = 512;
+ case 0x23:
+ case 0xd1:
+ case 0xd6:
+ l3_cache = 1024;
+ break;
+ case 0xdc:
+ l3_cache = 1536;
+ break;
+ case 0x25:
+ case 0xd2:
+ case 0xd7:
+ case 0xe2:
+ l3_cache = 2048;
+ break;
+ case 0xdd:
+ l3_cache = 3072;
+ break;
+ case 0x29:
+ case 0x46:
+ case 0xd8:
+ case 0xe3:
+ l3_cache = 4096;
+ break;
+ case 0x4a:
+ case 0xde:
+ l3_cache = 6144;
+ break;
+ case 0x47:
+ case 0x4b:
+ case 0xe4:
+ l3_cache = 8192;
+ break;
+ case 0x4c:
+ case 0xea:
+ l3_cache = 12288;
+ break;
+ case 0x4d:
+ l3_cache = 16374;
+ break;
+ case 0xeb:
+ l3_cache = 18432;
+ break;
+ case 0xec:
+ l3_cache = 24576;
+ break;
}
}
+
+ // If no cache found, check if deterministic cache info are available
+ if(l1_cache == 0 && ((cpu_id.dcache0_eax >> 5) & 7) == 1)
+ {
+
+ long dcache[] = { cpu_id.dcache0_eax, cpu_id.dcache0_ebx, cpu_id.dcache0_ecx, cpu_id.dcache0_edx,
+ cpu_id.dcache1_eax, cpu_id.dcache1_ebx, cpu_id.dcache1_ecx, cpu_id.dcache1_edx,
+ cpu_id.dcache2_eax, cpu_id.dcache2_ebx, cpu_id.dcache2_ecx, cpu_id.dcache2_edx,
+ cpu_id.dcache3_eax, cpu_id.dcache3_ebx, cpu_id.dcache3_ecx, cpu_id.dcache3_edx
+ };
+
+ for(i=0; i<4; i++)
+ {
+ switch((dcache[i*4] >> 5) & 7)
+ {
+ case 1:
+ // We don't want L1 I-Cache, only L1 D-Cache
+ if((dcache[i*4] & 3) != 2)
+ {
+ l1_cache = (((dcache[i*4+1] >> 22) & 0x3FF) + 1) * (((dcache[i*4+1] >> 12) & 0x3FF) + 1);
+ l1_cache *= ((dcache[i*4+1] & 0xFFF) + 1) * (dcache[i*4+2] + 1) / 1024;
+ }
+ break;
+ case 2:
+ l2_cache = (((dcache[i*4+1] >> 22) & 0x3FF) + 1) * (((dcache[i*4+1] >> 12) & 0x3FF) + 1);
+ l2_cache *= ((dcache[i*4+1] & 0xFFF) + 1) * (dcache[i*4+2] + 1) / 1024;
+ break;
+ case 3:
+ l3_cache = (((dcache[i*4+1] >> 22) & 0x3FF) + 1) * (((dcache[i*4+1] >> 12) & 0x3FF) + 1);
+ l3_cache *= ((dcache[i*4+1] & 0xFFF) + 1) * (dcache[i*4+2] + 1) / 1024;
+ break;
+ }
+ }
+ }
+
switch(cpu_id.type) {
case 5:
@@ -676,6 +907,18 @@
off = 10;
break;
case 5:
+ if ((cpu_id.ext >> 16) & 0xF) {
+ if(((cpu_id.ext >> 16) & 0xF) > 1) {
+ cprint(LINE_CPU, 0, "Intel Core i3/i5");
+ tsc_invariable = 1;
+ imc_type = 0x0003;
+ off = 16;
+ } else {
+ cprint(LINE_CPU, 0, "Intel EP80579");
+ if (l2_cache == 0) { l2_cache = 256; }
+ off = 13;
+ }
+ } else {
if (l2_cache == 0) {
cprint(LINE_CPU, 0, "Celeron");
off = 7;
@@ -683,26 +926,37 @@
cprint(LINE_CPU, 0, "Pentium II");
off = 10;
}
+ }
break;
case 6:
- if (l2_cache == 128) {
- cprint(LINE_CPU, 0, "Celeron");
- off = 7;
- } else {
- cprint(LINE_CPU, 0, "Pentium II");
- off = 10;
- }
+ if (l2_cache == 128) {
+ cprint(LINE_CPU, 0, "Celeron");
+ off = 7;
+ } else {
+ cprint(LINE_CPU, 0, "Pentium II");
+ off = 10;
+ }
break;
case 7:
case 8:
- case 10:
case 11:
- if (l2_cache == 128) {
- cprint(LINE_CPU, 0, "Celeron");
- off = 7;
+ if (((cpu_id.ext >> 16) & 0xF) != 0) {
+ tsc_invariable = 1;
+ if (l2_cache < 1024) {
+ cprint(LINE_CPU, 0, "Celeron");
+ off = 7;
+ } else {
+ cprint(LINE_CPU, 0, "Intel Core 2");
+ off = 12;
+ }
} else {
- cprint(LINE_CPU, 0, "Pentium III");
- off = 11;
+ if (l2_cache == 128) {
+ cprint(LINE_CPU, 0, "Celeron");
+ off = 7;
+ } else {
+ cprint(LINE_CPU, 0, "Pentium III");
+ off = 11;
+ }
}
break;
case 9:
@@ -713,6 +967,35 @@
}
off = 16;
break;
+ case 10:
+ if (((cpu_id.ext >> 16) & 0xF) != 0) {
+ tsc_invariable = 1;
+ if(((cpu_id.ext >> 16) & 0xF) > 1) {
+ cprint(LINE_CPU, 0, "Intel Core Gen2");
+ imc_type = 0x0004;
+ off = 15;
+ } else {
+ imc_type = 0x0001;
+ cprint(LINE_CPU, 0, "Intel Core i7");
+ off = 13;
+ }
+ } else {
+ cprint(LINE_CPU, 0, "Pentium III Xeon");
+ off = 16;
+ }
+ break;
+ case 12:
+ if (((cpu_id.ext >> 16) & 0xF) > 1) {
+ cprint(LINE_CPU, 0, "Core i7 (32nm)");
+ tsc_invariable = 1;
+ imc_type = 0x0002;
+ off = 14;
+ } else {
+ l1_cache = 24;
+ cprint(LINE_CPU, 0, "Atom (0.045)");
+ off = 12;
+ }
+ break;
case 13:
if (l2_cache == 1024) {
cprint(LINE_CPU, 0, "Celeron M (0.09)");
@@ -722,12 +1005,25 @@
off = 16;
break;
case 14:
- cprint(LINE_CPU, 0, "Intel Core");
- off = 10;
+ if (((cpu_id.ext >> 16) & 0xF) != 0) {
+ tsc_invariable = 1;
+ imc_type = 0x0001;
+ cprint(LINE_CPU, 0, "Intel Core i5/i7");
+ off = 16;
+ } else {
+ cprint(LINE_CPU, 0, "Intel Core");
+ off = 10;
+ }
break;
case 15:
- cprint(LINE_CPU, 0, "Intel Core 2");
- off = 12;
+ if (l2_cache == 1024) {
+ cprint(LINE_CPU, 0, "Pentium E");
+ off = 9;
+ } else {
+ cprint(LINE_CPU, 0, "Intel Core 2");
+ off = 12;
+ }
+ tsc_invariable = 1;
break;
}
break;
@@ -800,23 +1096,44 @@
/* VIA/Cyrix/Centaur Processors with CPUID */
case 'C':
if ( cpu_id.vend_id[1] == 'e' ) { /* CentaurHauls */
+ l1_cache = cpu_id.cache_info[3] + cpu_id.cache_info[7];
+ l2_cache = cpu_id.cache_info[11];
switch(cpu_id.type){
case 5:
cprint(LINE_CPU, 0, "Centaur 5x86");
off = 12;
break;
case 6: // VIA C3
- if (cpu_id.step < 8) {
- cprint(LINE_CPU, 0, "VIA C3 Samuel2");
- off = 14;
- } else {
- cprint(LINE_CPU, 0, "Via C3 Eden");
- off = 11;
+ switch(cpu_id.model){
+ default:
+ if (cpu_id.step < 8) {
+ cprint(LINE_CPU, 0, "VIA C3 Samuel2");
+ off = 14;
+ } else {
+ cprint(LINE_CPU, 0, "VIA C3 Eden");
+ off = 11;
+ }
+ break;
+ case 10:
+ cprint(LINE_CPU, 0, "VIA C7 (C5J)");
+ l1_cache = 64;
+ l2_cache = 128;
+ off = 16;
+ break;
+ case 13:
+ cprint(LINE_CPU, 0, "VIA C7 (C5R)");
+ l1_cache = 64;
+ l2_cache = 128;
+ off = 12;
+ break;
+ case 15:
+ cprint(LINE_CPU, 0, "VIA Isaiah (CN)");
+ l1_cache = 64;
+ l2_cache = 1024;
+ off = 15;
+ break;
}
- break;
}
- l1_cache = cpu_id.cache_info[3] + cpu_id.cache_info[7];
- l2_cache = cpu_id.cache_info[11];
} else { /* CyrixInstead */
switch(cpu_id.type) {
case 5:
@@ -899,12 +1216,11 @@
/* To measure L1 cache speed we use a block size that is 1/4th */
/* of the total L1 cache size since half of it is for instructions */
if (l1_cache) {
- cprint(LINE_CPU+1, 10, " K ");
+ cprint(LINE_CPU+1, 0, "L1 Cache: K ");
dprint(LINE_CPU+1, 11, l1_cache, 3, 0);
- if ((speed=memspeed((ulong)mapping(0x100),
- (l1_cache / 4) * 1024, 50))) {
- cprint(LINE_CPU+1, 15, " MB/s");
- dprint(LINE_CPU+1, 15, speed, 6, 0);
+ if ((speed=memspeed((ulong)mapping(0x100), (l1_cache / 4) * 1024, 200, MS_COPY))) {
+ cprint(LINE_CPU+1, 16, " MB/s");
+ dprint(LINE_CPU+1, 16, speed, 6, 0);
}
}
@@ -913,8 +1229,8 @@
/* the size of the L1 cache. We have to fudge if the L1 */
/* cache is bigger than the L2 */
if (l2_cache) {
- cprint(LINE_CPU+2, 9, " K ");
- cprint(LINE_CPU+2, 0, "L2 Cache: ?K");
+ cprint(LINE_CPU+2, 0, "L2 Cache: K ");
+ dprint(LINE_CPU+2, 10, l2_cache, 4, 0);
dprint(LINE_CPU+2, 10, l2_cache, 4, 0);
if (l2_cache < l1_cache) {
@@ -922,23 +1238,41 @@
} else {
i = l1_cache;
}
- if ((speed=memspeed((ulong)mapping(0x100), i*1024, 50))) {
- cprint(LINE_CPU+2, 15, " MB/s");
- dprint(LINE_CPU+2, 15, speed, 6, 0);
+ if ((speed=memspeed((ulong)mapping(0x100), i*1024, 200, MS_COPY))) {
+ cprint(LINE_CPU+2, 16, " MB/s");
+ dprint(LINE_CPU+2, 16, speed, 6, 0);
+ }
+ }
+
+ /* Print out L3 cache info */
+ /* We measure the L3 cache speed by using a block size that is */
+ /* the size of the L2 cache. */
+
+ if (l3_cache) {
+ cprint(LINE_CPU+3, 0, "L3 Cache: K ");
+ dprint(LINE_CPU+3, 10, l3_cache, 4, 0);
+ dprint(LINE_CPU+3, 10, l3_cache, 4, 0);
+
+ i = l2_cache*2;
+
+ if ((speed=memspeed((ulong)mapping(0x100), i*1024, 150, MS_COPY))) {
+ cprint(LINE_CPU+3, 16, " MB/s");
+ dprint(LINE_CPU+3, 16, speed, 6, 0);
}
}
- /* Determine memory speed. To find the memory spped we use */
- /* A block size that is 5x the sum of the L1 and L2 caches */
- i = (l2_cache + l1_cache) * 5;
+ /* Determine memory speed. To find the memory speed we use */
+ /* A block size that is 5x the sum of the L1, L2 & L3 caches */
+ i = (l3_cache + l2_cache + l1_cache) * 5;
+
/* Make sure that we have enough memory to do the test */
if ((1 + (i * 2)) > (v->plim_upper << 2)) {
i = ((v->plim_upper <<2) - 1) / 2;
}
- if((speed = memspeed((ulong)mapping(0x100), i*1024, 40))) {
- cprint(LINE_CPU+3, 15, " MB/s");
- dprint(LINE_CPU+3, 15, speed, 6, 0);
+ if((speed = memspeed((ulong)mapping(0x100), i*1024, 50, MS_COPY))) {
+ cprint(LINE_CPU+4, 16, " MB/s");
+ dprint(LINE_CPU+4, 16, speed, 6, 0);
}
/* Record the starting time */
@@ -976,7 +1310,7 @@
}
/* Map the range and perform the test */
map_page(paddr);
- speed = memspeed((ulong)mapping(paddr), 32*4096, 1);
+ speed = memspeed((ulong)mapping(paddr), 32*4096, 1, MS_READ);
if (pspeed) {
if (speed < pspeed) {
cached -= 32;
@@ -1025,13 +1359,16 @@
if (loops < 4 || end_low < 50000) {
return(-1);
}
- v->clks_msec = end_low/50;
+
+ if(tsc_invariable){ end_low = correct_tsc(end_low); }
+
+ v->clks_msec = end_low/50;
return(v->clks_msec);
}
/* Measure cache/memory speed by copying a block of memory. */
/* Returned value is kbytes/second */
-static ulong memspeed(ulong src, ulong len, int iter)
+ulong memspeed(ulong src, ulong len, int iter, int type)
{
ulong dst;
ulong wlen;
@@ -1045,11 +1382,11 @@
for (i=0; i<iter; i++) {
asm __volatile__ (
"movl %0,%%esi\n\t" \
- "movl %1,%%edi\n\t" \
- "movl %2,%%ecx\n\t" \
- "cld\n\t" \
- "rep\n\t" \
- "movsl\n\t" \
+ "movl %1,%%edi\n\t" \
+ "movl %2,%%ecx\n\t" \
+ "cld\n\t" \
+ "rep\n\t" \
+ "movsl\n\t" \
:: "g" (src), "g" (dst), "g" (0)
: "esi", "edi", "ecx"
);
@@ -1065,33 +1402,78 @@
"0" (cal_low), "1" (cal_high)
);
- /* Do the first copy to prime the cache */
- asm __volatile__ (
- "movl %0,%%esi\n\t" \
- "movl %1,%%edi\n\t" \
- "movl %2,%%ecx\n\t" \
- "cld\n\t" \
- "rep\n\t" \
- "movsl\n\t" \
- :: "g" (src), "g" (dst), "g" (wlen)
- : "esi", "edi", "ecx"
- );
/* Now measure the speed */
- asm __volatile__ ("rdtsc":"=a" (st_low),"=d" (st_high));
- for (i=0; i<iter; i++) {
+ switch (type) {
+ case MS_COPY:
+ /* Do the first copy to prime the cache */
asm __volatile__ (
"movl %0,%%esi\n\t" \
"movl %1,%%edi\n\t" \
- "movl %2,%%ecx\n\t" \
- "cld\n\t" \
- "rep\n\t" \
- "movsl\n\t" \
- :: "g" (src), "g" (dst), "g" (wlen)
+ "movl %2,%%ecx\n\t" \
+ "cld\n\t" \
+ "rep\n\t" \
+ "movsl\n\t" \
+ :: "g" (src), "g" (dst), "g" (wlen)
: "esi", "edi", "ecx"
);
+ asm __volatile__ ("rdtsc":"=a" (st_low),"=d" (st_high));
+ for (i=0; i<iter; i++) {
+ asm __volatile__ (
+ "movl %0,%%esi\n\t" \
+ "movl %1,%%edi\n\t" \
+ "movl %2,%%ecx\n\t" \
+ "cld\n\t" \
+ "rep\n\t" \
+ "movsl\n\t" \
+ :: "g" (src), "g" (dst), "g" (wlen)
+ : "esi", "edi", "ecx"
+ );
+ }
+ asm __volatile__ ("rdtsc":"=a" (end_low),"=d" (end_high));
+ break;
+ case MS_WRITE:
+ asm __volatile__ ("rdtsc":"=a" (st_low),"=d" (st_high));
+ for (i=0; i<iter; i++) {
+ asm __volatile__ (
+ "movl %0,%%ecx\n\t" \
+ "movl %1,%%edi\n\t" \
+ "movl %2,%%eax\n\t" \
+ "rep\n\t" \
+ "stosl\n\t"
+ :: "g" (wlen), "g" (dst), "g" (0)
+ : "edi", "ecx", "eax"
+ );
+ }
+ asm __volatile__ ("rdtsc":"=a" (end_low),"=d" (end_high));
+ break;
+ case MS_READ:
+ asm __volatile__ (
+ "movl %0,%%esi\n\t" \
+ "movl %1,%%ecx\n\t" \
+ "cld\n\t" \
+ "L1:\n\t" \
+ "lodsl\n\t" \
+ "loop L1\n\t" \
+ :: "g" (src), "g" (wlen)
+ : "esi", "ecx"
+ );
+ asm __volatile__ ("rdtsc":"=a" (st_low),"=d" (st_high));
+ for (i=0; i<iter; i++) {
+ asm __volatile__ (
+ "movl %0,%%esi\n\t" \
+ "movl %1,%%ecx\n\t" \
+ "cld\n\t" \
+ "L2:\n\t" \
+ "lodsl\n\t" \
+ "loop L2\n\t" \
+ :: "g" (src), "g" (wlen)
+ : "esi", "ecx", "eax"
+ );
+ }
+ asm __volatile__ ("rdtsc":"=a" (end_low),"=d" (end_high));
+ break;
}
- asm __volatile__ ("rdtsc":"=a" (end_low),"=d" (end_high));
/* Compute the elapsed time */
asm __volatile__ (
@@ -1115,8 +1497,10 @@
return(0);
}
- /* Since a copy does both a read & write we need to adjuect the time */
- end_low /= 2;
+ /* If this was a copy adjust the time */
+ if (type == MS_COPY) {
+ end_low /= 2;
+ }
/* Convert to clocks/KB */
end_low /= len;
@@ -1126,6 +1510,43 @@
return(0);
}
+ if(tsc_invariable){ end_low = correct_tsc(end_low); }
+
/* Convert to kbytes/sec */
return((v->clks_msec)/end_low);
}
+
+ulong correct_tsc(ulong el_org)
+{
+
+ float coef_now, coef_max;
+ int msr_lo, msr_hi, is_xe;
+
+ rdmsr(0x198, msr_lo, msr_hi);
+ is_xe = (msr_lo >> 31) & 0x1;
+
+ if(is_xe){
+ rdmsr(0x198, msr_lo, msr_hi);
+ coef_max = ((msr_hi >> 8) & 0x1F);
+ if ((msr_hi >> 14) & 0x1) { coef_max = coef_max + 0.5f; }
+ } else {
+ rdmsr(0x17, msr_lo, msr_hi);
+ coef_max = ((msr_lo >> 8) & 0x1F);
+ if ((msr_lo >> 14) & 0x1) { coef_max = coef_max + 0.5f; }
+ }
+
+ if((cpu_id.feature_flag >> 7) & 1) {
+ rdmsr(0x198, msr_lo, msr_hi);
+ coef_now = ((msr_lo >> 8) & 0x1F);
+ if ((msr_lo >> 14) & 0x1) { coef_now = coef_now + 0.5f; }
+ } else {
+ rdmsr(0x2A, msr_lo, msr_hi);
+ coef_now = (msr_lo >> 22) & 0x1F;
+ }
+
+ if(coef_max && coef_now) { el_org = (ulong)(el_org * coef_now / coef_max); }
+
+ return el_org;
+
+}
+
|
|
[-]
[+]
|
Added |
memtest86+-4.20.tar.bz2/jedec_id.h
^
|
| @@ -0,0 +1,887 @@
+/* MemTest86+ V4.00 Specific code (GPL V2.0)
+ * By Samuel DEMEULEMEESTER, sdemeule@memtest.org
+ * http://www.canardpc.com - http://www.memtest.org
+ */
+
+struct spd_jedec_manufacturer {
+ unsigned cont_code;
+ unsigned hex_byte;
+ char *name;
+};
+
+struct spd_jedec_manufacturer jep106[] = {
+ { 0, 0x01, "AMD"},
+ { 0, 0x02, "AMI"},
+ { 0, 0x83, "Fairchild"},
+ { 0, 0x04, "Fujitsu"},
+ { 0, 0x85, "GTE"},
+ { 0, 0x86, "Harris"},
+ { 0, 0x07, "Hitachi"},
+ { 0, 0x08, "Inmos"},
+ { 0, 0x89, "Intel"},
+ { 0, 0x8a, "I.T.T."},
+ { 0, 0x0b, "Intersil"},
+ { 0, 0x8c, "Monolithic Memories"},
+ { 0, 0x0d, "Mostek"},
+ { 0, 0x0e, "Freescale (Motorola)"},
+ { 0, 0x8f, "National"},
+ { 0, 0x10, "NEC"},
+ { 0, 0x91, "RCA"},
+ { 0, 0x92, "Raytheon"},
+ { 0, 0x13, "Conexant (Rockwell)"},
+ { 0, 0x94, "Seeq"},
+ { 0, 0x15, "NXP (Philips)"},
+ { 0, 0x16, "Synertek"},
+ { 0, 0x97, "Texas Instruments"},
+ { 0, 0x98, "Toshiba"},
+ { 0, 0x19, "Xicor"},
+ { 0, 0x1a, "Zilog"},
+ { 0, 0x9b, "Eurotechnique"},
+ { 0, 0x1c, "Mitsubishi"},
+ { 0, 0x9d, "Lucent (AT&T)"},
+ { 0, 0x9e, "Exel"},
+ { 0, 0x1f, "Atmel"},
+ { 0, 0x20, "SGS/Thomson"},
+ { 0, 0xa1, "Lattice Semi."},
+ { 0, 0xa2, "NCR"},
+ { 0, 0x23, "Wafer Scale Integration"},
+ { 0, 0xa4, "IBM"},
+ { 0, 0x25, "Tristar"},
+ { 0, 0x26, "Visic"},
+ { 0, 0xa7, "Intl. CMOS Technology"},
+ { 0, 0xa8, "SSSI"},
+ { 0, 0x29, "MicrochipTechnology"},
+ { 0, 0x2a, "Ricoh"},
+ { 0, 0xab, "VLSI"},
+ { 0, 0x2c, "Micron Technology"},
+ { 0, 0xad, "Hynix Semiconductor"},
+ { 0, 0xae, "OKI Semiconductor"},
+ { 0, 0x2f, "ACTEL"},
+ { 0, 0xb0, "Sharp"},
+ { 0, 0x31, "Catalyst"},
+ { 0, 0x32, "Panasonic"},
+ { 0, 0xb3, "IDT"},
+ { 0, 0x34, "Cypress"},
+ { 0, 0xb5, "DEC"},
+ { 0, 0xb6, "LSI Logic"},
+ { 0, 0x37, "Zarlink (Plessey)"},
+ { 0, 0x38, "UTMC"},
+ { 0, 0xb9, "Thinking Machine"},
+ { 0, 0xba, "Thomson CSF"},
+ { 0, 0x3b, "Integrated CMOS (Vertex)"},
+ { 0, 0xbc, "Honeywell"},
+ { 0, 0x3d, "Tektronix"},
+ { 0, 0x3e, "Sun Microsystems"},
+ { 0, 0xbf, "SST"},
+ { 0, 0x40, "ProMos/Mosel Vitelic"},
+ { 0, 0xc1, "Infineon (Siemens)"},
+ { 0, 0xc2, "Macronix"},
+ { 0, 0x43, "Xerox"},
+ { 0, 0xc4, "Plus Logic"},
+ { 0, 0x45, "SanDisk"},
+ { 0, 0x46, "Elan Circuit Tech."},
+ { 0, 0xc7, "European Silicon Str."},
+ { 0, 0xc8, "Apple Computer"},
+ { 0, 0x49, "Xilinx"},
+ { 0, 0x4a, "Compaq"},
+ { 0, 0xcb, "Protocol Engines"},
+ { 0, 0x4c, "SCI"},
+ { 0, 0xcd, "Seiko Instruments"},
+ { 0, 0xce, "Samsung"},
+ { 0, 0x4f, "I3 Design System"},
+ { 0, 0xd0, "Klic"},
+ { 0, 0x51, "Crosspoint Solutions"},
+ { 0, 0x52, "Alliance Semiconductor"},
+ { 0, 0xd3, "Tandem"},
+ { 0, 0x54, "Hewlett-Packard"},
+ { 0, 0xd5, "Intg. Silicon Solutions"},
+ { 0, 0xd6, "Brooktree"},
+ { 0, 0x57, "New Media"},
+ { 0, 0x58, "MHS Electronic"},
+ { 0, 0xd9, "Performance Semi."},
+ { 0, 0xda, "Winbond Electronic"},
+ { 0, 0x5b, "Kawasaki Steel"},
+ { 0, 0xdc, "Bright Micro"},
+ { 0, 0x5d, "TECMAR"},
+ { 0, 0x5e, "Exar"},
+ { 0, 0xdf, "PCMCIA"},
+ { 0, 0xe0, "LG Semi (Goldstar)"},
+ { 0, 0x61, "Northern Telecom"},
+ { 0, 0x62, "Sanyo"},
+ { 0, 0xe3, "Array Microsystems"},
+ { 0, 0x64, "Crystal Semiconductor"},
+ { 0, 0xe5, "Analog Devices"},
+ { 0, 0xe6, "PMC-Sierra"},
+ { 0, 0x67, "Asparix"},
+ { 0, 0x68, "Convex Computer"},
+ { 0, 0xe9, "Quality Semiconductor"},
+ { 0, 0xea, "Nimbus Technology"},
+ { 0, 0x6b, "Transwitch"},
+ { 0, 0xec, "Micronas (ITT Intermetall)"},
+ { 0, 0x6d, "Cannon"},
+ { 0, 0x6e, "Altera"},
+ { 0, 0xef, "NEXCOM"},
+ { 0, 0x70, "QUALCOMM"},
+ { 0, 0xf1, "Sony"},
+ { 0, 0xf2, "Cray Research"},
+ { 0, 0x73, "AMS(Austria Micro)"},
+ { 0, 0xf4, "Vitesse"},
+ { 0, 0x75, "Aster Electronics"},
+ { 0, 0x76, "Bay Networks (Synoptic)"},
+ { 0, 0xf7, "Zentrum/ZMD"},
+ { 0, 0xf8, "TRW"},
+ { 0, 0x79, "Thesys"},
+ { 0, 0x7a, "Solbourne Computer"},
+ { 0, 0xfb, "Allied-Signal"},
+ { 0, 0x7c, "Dialog"},
+ { 0, 0xfd, "Media Vision"},
+ { 0, 0xfe, "Numonyx"},
+ { 1, 0x01, "Cirrus Logic"},
+ { 1, 0x02, "National Instruments"},
+ { 1, 0x83, "ILC Data Device"},
+ { 1, 0x04, "Alcatel Mietec"},
+ { 1, 0x85, "Micro Linear"},
+ { 1, 0x86, "Univ. of NC"},
+ { 1, 0x07, "JTAG Technologies"},
+ { 1, 0x08, "BAE Systems (Loral)"},
+ { 1, 0x89, "Nchip"},
+ { 1, 0x8a, "Galileo Tech"},
+ { 1, 0x0b, "Bestlink Systems"},
+ { 1, 0x8c, "Graychip"},
+ { 1, 0x0d, "GENNUM"},
+ { 1, 0x0e, "VideoLogic"},
+ { 1, 0x8f, "Robert Bosch"},
+ { 1, 0x10, "Chip Express"},
+ { 1, 0x91, "DATARAM"},
+ { 1, 0x92, "United Microelectronics Corp."},
+ { 1, 0x13, "TCSI"},
+ { 1, 0x94, "Smart Modular"},
+ { 1, 0x15, "Hughes Aircraft"},
+ { 1, 0x16, "Lanstar Semiconductor"},
+ { 1, 0x97, "Qlogic"},
+ { 1, 0x98, "Kingston"},
+ { 1, 0x19, "Music Semi"},
+ { 1, 0x1a, "Ericsson Components"},
+ { 1, 0x9b, "SpaSE"},
+ { 1, 0x1c, "Eon Silicon Devices"},
+ { 1, 0x9d, "Programmable Micro Corp"},
+ { 1, 0x9e, "DoD"},
+ { 1, 0x1f, "Integ. Memories Tech."},
+ { 1, 0x20, "Corollary"},
+ { 1, 0xa1, "Dallas Semiconductor"},
+ { 1, 0xa2, "Omnivision"},
+ { 1, 0x23, "EIV(Switzerland)"},
+ { 1, 0xa4, "Novatel Wireless"},
+ { 1, 0x25, "Zarlink (Mitel)"},
+ { 1, 0x26, "Clearpoint"},
+ { 1, 0xa7, "Cabletron"},
+ { 1, 0xa8, "STEC (Silicon Tech)"},
+ { 1, 0x29, "Vanguard"},
+ { 1, 0x2a, "Hagiwara Sys-Com"},
+ { 1, 0xab, "Vantis"},
+ { 1, 0x2c, "Celestica"},
+ { 1, 0xad, "Century"},
+ { 1, 0xae, "Hal Computers"},
+ { 1, 0x2f, "Rohm Company"},
+ { 1, 0xb0, "Juniper Networks"},
+ { 1, 0x31, "Libit Signal Processing"},
+ { 1, 0x32, "Mushkin Enhanced Memory"},
+ { 1, 0xb3, "Tundra Semiconductor"},
+ { 1, 0x34, "Adaptec"},
+ { 1, 0xb5, "LightSpeed Semi."},
+ { 1, 0xb6, "ZSP Corp."},
+ { 1, 0x37, "AMIC Technology"},
+ { 1, 0x38, "Adobe Systems"},
+ { 1, 0xb9, "Dynachip"},
+ { 1, 0xba, "PNY Electronics"},
+ { 1, 0x3b, "Newport Digital"},
+ { 1, 0xbc, "MMC Networks"},
+ { 1, 0x3d, "T Square"},
+ { 1, 0x3e, "Seiko Epson"},
+ { 1, 0xbf, "Broadcom"},
+ { 1, 0x40, "Viking Components"},
+ { 1, 0xc1, "V3 Semiconductor"},
+ { 1, 0xc2, "Flextronics (Orbit Semiconductor)"},
+ { 1, 0x43, "Suwa Electronics"},
+ { 1, 0xc4, "Transmeta"},
+ { 1, 0x45, "Micron CMS"},
+ { 1, 0x46, "American Computer & Digital Components"},
+ { 1, 0xc7, "Enhance 3000"},
+ { 1, 0xc8, "Tower Semiconductor"},
+ { 1, 0x49, "CPU Design"},
+ { 1, 0x4a, "Price Point"},
+ { 1, 0xcb, "Maxim Integrated Product"},
+ { 1, 0x4c, "Tellabs"},
+ { 1, 0xcd, "Centaur Technology"},
+ { 1, 0xce, "Unigen"},
+ { 1, 0x4f, "Transcend Information"},
+ { 1, 0xd0, "Memory Card Technology"},
+ { 1, 0x51, "CKD"},
+ { 1, 0x52, "Capital Instruments"},
+ { 1, 0xd3, "Aica Kogyo"},
+ { 1, 0x54, "Linvex Technology"},
+ { 1, 0xd5, "MSC Vertriebs"},
+ { 1, 0xd6, "AKM Company"},
+ { 1, 0x57, "Dynamem"},
+ { 1, 0x58, "NERA ASA"},
+ { 1, 0xd9, "GSI Technology"},
+ { 1, 0xda, "Dane-Elec (C Memory)"},
+ { 1, 0x5b, "Acorn Computers"},
+ { 1, 0xdc, "Lara Technology"},
+ { 1, 0x5d, "Oak Technology"},
+ { 1, 0x5e, "Itec Memory"},
+ { 1, 0xdf, "Tanisys Technology"},
+ { 1, 0xe0, "Truevision"},
+ { 1, 0x61, "Wintec Industries"},
+ { 1, 0x62, "Super PC Memory"},
+ { 1, 0xe3, "MGV Memory"},
+ { 1, 0x64, "Galvantech"},
+ { 1, 0xe5, "Gadzoox Networks"},
+ { 1, 0xe6, "Multi Dimensional Cons."},
+ { 1, 0x67, "GateField"},
+ { 1, 0x68, "Integrated Memory System"},
+ { 1, 0xe9, "Triscend"},
+ { 1, 0xea, "XaQti"},
+ { 1, 0x6b, "Goldenram"},
+ { 1, 0xec, "Clear Logic"},
+ { 1, 0x6d, "Cimaron Communications"},
+ { 1, 0x6e, "Nippon Steel Semi. Corp."},
+ { 1, 0xef, "Advantage Memory"},
+ { 1, 0x70, "AMCC"},
+ { 1, 0xf1, "LeCroy"},
+ { 1, 0xf2, "Yamaha"},
+ { 1, 0x73, "Digital Microwave"},
+ { 1, 0xf4, "NetLogic Microsystems"},
+ { 1, 0x75, "MIMOS Semiconductor"},
+ { 1, 0x76, "Advanced Fibre"},
+ { 1, 0xf7, "BF Goodrich Data."},
+ { 1, 0xf8, "Epigram"},
+ { 1, 0x79, "Acbel Polytech"},
+ { 1, 0x7a, "Apacer Technology"},
+ { 1, 0xfb, "Admor Memory"},
+ { 1, 0x7c, "FOXCONN"},
+ { 1, 0xfd, "Quadratics Superconductor"},
+ { 1, 0xfe, "3COM"},
+ { 2, 0x01, "Camintonn"},
+ { 2, 0x02, "ISOA"},
+ { 2, 0x83, "Agate Semiconductor"},
+ { 2, 0x04, "ADMtek"},
+ { 2, 0x85, "HYPERTEC"},
+ { 2, 0x86, "Adhoc Technologies"},
+ { 2, 0x07, "MOSAID Technologies"},
+ { 2, 0x08, "Ardent Technologies"},
+ { 2, 0x89, "Switchcore"},
+ { 2, 0x8a, "Cisco Systems"},
+ { 2, 0x0b, "Allayer Technologies"},
+ { 2, 0x8c, "WorkX AG (Wichman)"},
+ { 2, 0x0d, "Oasis Semiconductor"},
+ { 2, 0x0e, "Novanet Semiconductor"},
+ { 2, 0x8f, "E-M Solutions"},
+ { 2, 0x10, "Power General"},
+ { 2, 0x91, "Advanced Hardware Arch."},
+ { 2, 0x92, "Inova Semiconductors"},
+ { 2, 0x13, "Telocity"},
+ { 2, 0x94, "Delkin Devices"},
+ { 2, 0x15, "Symagery Microsystems"},
+ { 2, 0x16, "C-Port"},
+ { 2, 0x97, "SiberCore Technologies"},
+ { 2, 0x98, "Southland Microsystems"},
+ { 2, 0x19, "Malleable Technologies"},
+ { 2, 0x1a, "Kendin Communications"},
+ { 2, 0x9b, "Great Technology Microcomputer"},
+ { 2, 0x1c, "Sanmina"},
+ { 2, 0x9d, "HADCO"},
+ { 2, 0x9e, "Corsair"},
+ { 2, 0x1f, "Actrans System"},
+ { 2, 0x20, "ALPHA Technologies"},
+ { 2, 0xa1, "Silicon Laboratories (Cygnal)"},
+ { 2, 0xa2, "Artesyn Technologies"},
+ { 2, 0x23, "Align Manufacturing"},
+ { 2, 0xa4, "Peregrine Semiconductor"},
+ { 2, 0x25, "Chameleon Systems"},
+ { 2, 0x26, "Aplus Flash Technology"},
+ { 2, 0xa7, "MIPS Technologies"},
+ { 2, 0xa8, "Chrysalis ITS"},
+ { 2, 0x29, "ADTEC"},
+ { 2, 0x2a, "Kentron Technologies"},
+ { 2, 0xab, "Win Technologies"},
+ { 2, 0x2c, "Tachyon Semiconductor (ASIC)"},
+ { 2, 0xad, "Extreme Packet Devices"},
+ { 2, 0xae, "RF Micro Devices"},
+ { 2, 0x2f, "Siemens AG"},
+ { 2, 0xb0, "Sarnoff"},
+ { 2, 0x31, "Itautec SA"},
+ { 2, 0x32, "Radiata"},
+ { 2, 0xb3, "Benchmark Elect. (AVEX)"},
+ { 2, 0x34, "Legend"},
+ { 2, 0xb5, "SpecTek"},
+ { 2, 0xb6, "Hi/fn"},
+ { 2, 0x37, "Enikia"},
+ { 2, 0x38, "SwitchOn Networks"},
+ { 2, 0xb9, "AANetcom"},
+ { 2, 0xba, "Micro Memory Bank"},
+ { 2, 0x3b, "ESS Technology"},
+ { 2, 0xbc, "Virata"},
+ { 2, 0x3d, "Excess Bandwidth"},
+ { 2, 0x3e, "West Bay Semiconductor"},
+ { 2, 0xbf, "DSP Group"},
+ { 2, 0x40, "Newport Communications"},
+ { 2, 0xc1, "Chip2Chip"},
+ { 2, 0xc2, "Phobos"},
+ { 2, 0x43, "Intellitech"},
+ { 2, 0xc4, "Nordic VLSI ASA"},
+ { 2, 0x45, "Ishoni Networks"},
+ { 2, 0x46, "Silicon Spice"},
+ { 2, 0xc7, "Alchemy Semiconductor"},
+ { 2, 0xc8, "Agilent Technologies"},
+ { 2, 0x49, "Centillium Communications"},
+ { 2, 0x4a, "W.L. Gore"},
+ { 2, 0xcb, "HanBit Electronics"},
+ { 2, 0x4c, "GlobeSpan"},
+ { 2, 0xcd, "Element 14"},
+ { 2, 0xce, "Pycon"},
+ { 2, 0x4f, "Saifun Semiconductors"},
+ { 2, 0xd0, "Sibyte,"},
+ { 2, 0x51, "MetaLink Technologies"},
+ { 2, 0x52, "Feiya Technology"},
+ { 2, 0xd3, "I & C Technology"},
+ { 2, 0x54, "Shikatronics"},
+ { 2, 0xd5, "Elektrobit"},
+ { 2, 0xd6, "Megic"},
+ { 2, 0x57, "Com-Tier"},
+ { 2, 0x58, "Malaysia Micro Solutions"},
+ { 2, 0xd9, "Hyperchip"},
+ { 2, 0xda, "Gemstone Communications"},
+ { 2, 0x5b, "Anadigm (Anadyne)"},
+ { 2, 0xdc, "3ParData"},
+ { 2, 0x5d, "Mellanox Technologies"},
+ { 2, 0x5e, "Tenx Technologies"},
+ { 2, 0xdf, "Helix AG"},
+ { 2, 0xe0, "Domosys"},
+ { 2, 0x61, "Skyup Technology"},
+ { 2, 0x62, "HiNT"},
+ { 2, 0xe3, "Chiaro"},
+ { 2, 0x64, "MDT Technologies"},
+ { 2, 0xe5, "Exbit Technology A/S"},
+ { 2, 0xe6, "Integrated Technology Express"},
+ { 2, 0x67, "AVED Memory"},
+ { 2, 0x68, "Legerity"},
+ { 2, 0xe9, "Jasmine Networks"},
+ { 2, 0xea, "Caspian Networks"},
+ { 2, 0x6b, "nCUBE"},
+ { 2, 0xec, "Silicon Access Networks"},
+ { 2, 0x6d, "FDK"},
+ { 2, 0x6e, "High Bandwidth Access"},
+ { 2, 0xef, "MultiLink Technology"},
+ { 2, 0x70, "BRECIS"},
+ { 2, 0xf1, "World Wide Packets"},
+ { 2, 0xf2, "APW"},
+ { 2, 0x73, "Chicory Systems"},
+ { 2, 0xf4, "Xstream Logic"},
+ { 2, 0x75, "Fast-Chip"},
+ { 2, 0x76, "Zucotto Wireless"},
+ { 2, 0xf7, "Realchip"},
+ { 2, 0xf8, "Galaxy Power"},
+ { 2, 0x79, "eSilicon"},
+ { 2, 0x7a, "Morphics Technology"},
+ { 2, 0xfb, "Accelerant Networks"},
+ { 2, 0x7c, "Silicon Wave"},
+ { 2, 0xfd, "SandCraft"},
+ { 2, 0xfe, "Elpida"},
+ { 3, 0x01, "Solectron"},
+ { 3, 0x02, "Optosys Technologies"},
+ { 3, 0x83, "Buffalo (Formerly Melco)"},
+ { 3, 0x04, "TriMedia Technologies"},
+ { 3, 0x85, "Cyan Technologies"},
+ { 3, 0x86, "Global Locate"},
+ { 3, 0x07, "Optillion"},
+ { 3, 0x08, "Terago Communications"},
+ { 3, 0x89, "Ikanos Communications"},
+ { 3, 0x8a, "Preton Technology"},
+ { 3, 0x0b, "Nanya Technology"},
+ { 3, 0x8c, "Elite Flash Storage"},
+ { 3, 0x0d, "Mysticom"},
+ { 3, 0x0e, "LightSand Communications"},
+ { 3, 0x8f, "ATI Technologies"},
+ { 3, 0x10, "Agere Systems"},
+ { 3, 0x91, "NeoMagic"},
+ { 3, 0x92, "AuroraNetics"},
+ { 3, 0x13, "Golden Empire"},
+ { 3, 0x94, "Mushkin"},
+ { 3, 0x15, "Tioga Technologies"},
+ { 3, 0x16, "Netlist"},
+ { 3, 0x97, "TeraLogic"},
+ { 3, 0x98, "Cicada Semiconductor"},
+ { 3, 0x19, "Centon Electronics"},
+ { 3, 0x1a, "Tyco Electronics"},
+ { 3, 0x9b, "Magis Works"},
+ { 3, 0x1c, "Zettacom"},
+ { 3, 0x9d, "Cogency Semiconductor"},
+ { 3, 0x9e, "Chipcon AS"},
+ { 3, 0x1f, "Aspex Technology"},
+ { 3, 0x20, "F5 Networks"},
+ { 3, 0xa1, "Programmable Silicon Solutions"},
+ { 3, 0xa2, "ChipWrights"},
+ { 3, 0x23, "Acorn Networks"},
+ { 3, 0xa4, "Quicklogic"},
+ { 3, 0x25, "Kingmax Semiconductor"},
+ { 3, 0x26, "BOPS"},
+ { 3, 0xa7, "Flasys"},
+ { 3, 0xa8, "BitBlitz Communications"},
+ { 3, 0x29, "eMemory Technology"},
+ { 3, 0x2a, "Procket Networks"},
+ { 3, 0xab, "Purple Ray"},
+ { 3, 0x2c, "Trebia Networks"},
+ { 3, 0xad, "Delta Electronics"},
+ { 3, 0xae, "Onex Communications"},
+ { 3, 0x2f, "Ample Communications"},
+ { 3, 0xb0, "Memory Experts Intl"},
+ { 3, 0x31, "Astute Networks"},
+ { 3, 0x32, "Azanda Network Devices"},
+ { 3, 0xb3, "Dibcom"},
+ { 3, 0x34, "Tekmos"},
+ { 3, 0xb5, "API NetWorks"},
+ { 3, 0xb6, "Bay Microsystems"},
+ { 3, 0x37, "Firecron"},
+ { 3, 0x38, "Resonext Communications"},
+ { 3, 0xb9, "Tachys Technologies"},
+ { 3, 0xba, "Equator Technology"},
+ { 3, 0x3b, "Concept Computer"},
+ { 3, 0xbc, "SILCOM"},
+ { 3, 0x3d, "3Dlabs"},
+ { 3, 0x3e, "c?t Magazine"},
+ { 3, 0xbf, "Sanera Systems"},
+ { 3, 0x40, "Silicon Packets"},
+ { 3, 0xc1, "Viasystems Group"},
+ { 3, 0xc2, "Simtek"},
+ { 3, 0x43, "Semicon Devices Singapore"},
+ { 3, 0xc4, "Satron Handelsges"},
+ { 3, 0x45, "Improv Systems"},
+ { 3, 0x46, "INDUSYS"},
+ { 3, 0xc7, "Corrent"},
+ { 3, 0xc8, "Infrant Technologies"},
+ { 3, 0x49, "Ritek Corp"},
+ { 3, 0x4a, "empowerTel Networks"},
+ { 3, 0xcb, "Hypertec"},
+ { 3, 0x4c, "Cavium Networks"},
+ { 3, 0xcd, "PLX Technology"},
+ { 3, 0xce, "Massana Design"},
+ { 3, 0x4f, "Intrinsity"},
+ { 3, 0xd0, "Valence Semiconductor"},
+ { 3, 0x51, "Terawave Communications"},
+ { 3, 0x52, "IceFyre Semiconductor"},
+ { 3, 0xd3, "Primarion"},
+ { 3, 0x54, "Picochip Designs"},
+ { 3, 0xd5, "Silverback Systems"},
+ { 3, 0xd6, "Jade Star Technologies"},
+ { 3, 0x57, "Pijnenburg Securealink"},
+ { 3, 0x58, "takeMS International AG"},
+ { 3, 0xd9, "Cambridge Silicon Radio"},
+ { 3, 0xda, "Swissbit"},
+ { 3, 0x5b, "Nazomi Communications"},
+ { 3, 0xdc, "eWave System"},
+ { 3, 0x5d, "Rockwell Collins"},
+ { 3, 0x5e, "Picocel Co. (Paion)"},
+ { 3, 0xdf, "Alphamosaic"},
+ { 3, 0xe0, "Sandburst"},
+ { 3, 0x61, "SiCon Video"},
+ { 3, 0x62, "NanoAmp Solutions"},
+ { 3, 0xe3, "Ericsson Technology"},
+ { 3, 0x64, "PrairieComm"},
+ { 3, 0xe5, "Mitac International"},
+ { 3, 0xe6, "Layer N Networks"},
+ { 3, 0x67, "MtekVision (Atsana)"},
+ { 3, 0x68, "Allegro Networks"},
+ { 3, 0xe9, "Marvell Semiconductors"},
+ { 3, 0xea, "Netergy Microelectronic"},
+ { 3, 0x6b, "NVIDIA"},
+ { 3, 0xec, "Internet Machines"},
+ { 3, 0x6d, "Peak Electronics"},
+ { 3, 0x6e, "Litchfield Communication"},
+ { 3, 0xef, "Accton Technology"},
+ { 3, 0x70, "Teradiant Networks"},
+ { 3, 0xf1, "Scaleo Chip"},
+ { 3, 0xf2, "Cortina Systems"},
+ { 3, 0x73, "RAM Components"},
+ { 3, 0xf4, "Raqia Networks"},
+ { 3, 0x75, "ClearSpeed"},
+ { 3, 0x76, "Matsushita Battery"},
+ { 3, 0xf7, "Xelerated"},
+ { 3, 0xf8, "SimpleTech"},
+ { 3, 0x79, "Utron Technology"},
+ { 3, 0x7a, "Astec International"},
+ { 3, 0xfb, "AVM"},
+ { 3, 0x7c, "Redux Communications"},
+ { 3, 0xfd, "Dot Hill Systems"},
+ { 3, 0xfe, "TeraChip"},
+ { 4, 0x01, "T-RAM"},
+ { 4, 0x02, "Innovics Wireless"},
+ { 4, 0x83, "Teknovus"},
+ { 4, 0x04, "KeyEye Communications"},
+ { 4, 0x85, "Runcom Technologies"},
+ { 4, 0x86, "RedSwitch"},
+ { 4, 0x07, "Dotcast"},
+ { 4, 0x08, "Silicon Mountain Memory"},
+ { 4, 0x89, "Signia Technologies"},
+ { 4, 0x8a, "Pixim"},
+ { 4, 0x0b, "Galazar Networks"},
+ { 4, 0x8c, "White Electronic Designs"},
+ { 4, 0x0d, "Patriot Scientific"},
+ { 4, 0x0e, "Neoaxiom"},
+ { 4, 0x8f, "3Y Power Technology"},
+ { 4, 0x10, "Scaleo Chip"},
+ { 4, 0x91, "Potentia Power Systems"},
+ { 4, 0x92, "C-guys"},
+ { 4, 0x13, "Digital Communications Technology"},
+ { 4, 0x94, "Silicon-Based Technology"},
+ { 4, 0x15, "Fulcrum Microsystems"},
+ { 4, 0x16, "Positivo Informatica"},
+ { 4, 0x97, "XIOtech"},
+ { 4, 0x98, "PortalPlayer"},
+ { 4, 0x19, "Zhiying Software"},
+ { 4, 0x1a, "ParkerVision"},
+ { 4, 0x9b, "Phonex Broadband"},
+ { 4, 0x1c, "Skyworks Solutions"},
+ { 4, 0x9d, "Entropic Communications"},
+ { 4, 0x9e, "Pacific Force Technology"},
+ { 4, 0x1f, "Zensys A/S"},
+ { 4, 0x20, "Legend Silicon Corp."},
+ { 4, 0xa1, "Sci-worx"},
+ { 4, 0xa2, "SMSC (Standard Microsystems)"},
+ { 4, 0x23, "Renesas Technology"},
+ { 4, 0xa4, "Raza Microelectronics"},
+ { 4, 0x25, "Phyworks"},
+ { 4, 0x26, "MediaTek"},
+ { 4, 0xa7, "Non-cents Productions"},
+ { 4, 0xa8, "US Modular"},
+ { 4, 0x29, "Wintegra"},
+ { 4, 0x2a, "Mathstar"},
+ { 4, 0xab, "StarCore"},
+ { 4, 0x2c, "Oplus Technologies"},
+ { 4, 0xad, "Mindspeed"},
+ { 4, 0xae, "Just Young Computer"},
+ { 4, 0x2f, "Radia Communications"},
+ { 4, 0xb0, "OCZ"},
+ { 4, 0x31, "Emuzed"},
+ { 4, 0x32, "LOGIC Devices"},
+ { 4, 0xb3, "Inphi"},
+ { 4, 0x34, "Quake Technologies"},
+ { 4, 0xb5, "Vixel"},
+ { 4, 0xb6, "SolusTek"},
+ { 4, 0x37, "Kongsberg Maritime"},
+ { 4, 0x38, "Faraday Technology"},
+ { 4, 0xb9, "Altium"},
+ { 4, 0xba, "Insyte"},
+ { 4, 0x3b, "ARM"},
+ { 4, 0xbc, "DigiVision"},
+ { 4, 0x3d, "Vativ Technologies"},
+ { 4, 0x3e, "Endicott Interconnect Technologies"},
+ { 4, 0xbf, "Pericom"},
+ { 4, 0x40, "Bandspeed"},
+ { 4, 0xc1, "LeWiz Communications"},
+ { 4, 0xc2, "CPU Technology"},
+ { 4, 0x43, "Ramaxel Technology"},
+ { 4, 0xc4, "DSP Group"},
+ { 4, 0x45, "Axis Communications"},
+ { 4, 0x46, "Legacy Electronics"},
+ { 4, 0xc7, "Chrontel"},
+ { 4, 0xc8, "Powerchip Semiconductor"},
+ { 4, 0x49, "MobilEye Technologies"},
+ { 4, 0x4a, "Excel Semiconductor"},
+ { 4, 0xcb, "A-DATA Technology"},
+ { 4, 0x4c, "VirtualDigm"},
+ { 4, 0xcd, "G Skill Intl"},
+ { 4, 0xce, "Quanta Computer"},
+ { 4, 0x4f, "Yield Microelectronics"},
+ { 4, 0xd0, "Afa Technologies"},
+ { 4, 0x51, "KINGBOX Technology Co."},
+ { 4, 0x52, "Ceva"},
+ { 4, 0xd3, "iStor Networks"},
+ { 4, 0x54, "Advance Modules"},
+ { 4, 0xd5, "Microsoft"},
+ { 4, 0xd6, "Open-Silicon"},
+ { 4, 0x57, "Goal Semiconductor"},
+ { 4, 0x58, "ARC International"},
+ { 4, 0xd9, "Simmtec"},
+ { 4, 0xda, "Metanoia"},
+ { 4, 0x5b, "Key Stream"},
+ { 4, 0xdc, "Lowrance Electronics"},
+ { 4, 0x5d, "Adimos"},
+ { 4, 0x5e, "SiGe Semiconductor"},
+ { 4, 0xdf, "Fodus Communications"},
+ { 4, 0xe0, "Credence Systems Corp."},
+ { 4, 0x61, "Genesis Microchip"},
+ { 4, 0x62, "Vihana"},
+ { 4, 0xe3, "WIS Technologies"},
+ { 4, 0x64, "GateChange Technologies"},
+ { 4, 0xe5, "High Density Devices AS"},
+ { 4, 0xe6, "Synopsys"},
+ { 4, 0x67, "Gigaram"},
+ { 4, 0x68, "Enigma Semiconductor"},
+ { 4, 0xe9, "Century Micro"},
+ { 4, 0xea, "Icera Semiconductor"},
+ { 4, 0x6b, "Mediaworks Integrated Systems"},
+ { 4, 0xec, "O'Neil Product Development"},
+ { 4, 0x6d, "Supreme Top Technology"},
+ { 4, 0x6e, "MicroDisplay"},
+ { 4, 0xef, "Team Group"},
+ { 4, 0x70, "Sinett"},
+ { 4, 0xf1, "Toshiba"},
+ { 4, 0xf2, "Tensilica"},
+ { 4, 0x73, "SiRF Technology"},
+ { 4, 0xf4, "Bacoc"},
+ { 4, 0x75, "SMaL Camera Technologies"},
+ { 4, 0x76, "Thomson SC"},
+ { 4, 0xf7, "Airgo Networks"},
+ { 4, 0xf8, "Wisair"},
+ { 4, 0x79, "SigmaTel"},
+ { 4, 0x7a, "Arkados"},
+ { 4, 0xfb, "Compete IT Co. KG"},
+ { 4, 0x7c, "Eudar Technology"},
+ { 4, 0xfd, "Focus Enhancements"},
+ { 4, 0xfe, "Xyratex"},
+ { 5, 0x01, "Specular Networks"},
+ { 5, 0x02, "Patriot Memory (PDP Systems)"},
+ { 5, 0x83, "U-Chip Technology Corp."},
+ { 5, 0x04, "Silicon Optix"},
+ { 5, 0x85, "Greenfield Networks"},
+ { 5, 0x86, "CompuRAM"},
+ { 5, 0x07, "Stargen"},
+ { 5, 0x08, "NetCell"},
+ { 5, 0x89, "Excalibrus Technologies"},
+ { 5, 0x8a, "SCM Microsystems"},
+ { 5, 0x0b, "Xsigo Systems"},
+ { 5, 0x8c, "CHIPS & Systems"},
+ { 5, 0x0d, "Tier"},
+ { 5, 0x0e, "CWRL Labs"},
+ { 5, 0x8f, "Teradici"},
+ { 5, 0x10, "Gigaram"},
+ { 5, 0x91, "g2 Microsystems"},
+ { 5, 0x92, "PowerFlash Semiconductor"},
+ { 5, 0x13, "P.A. Semi"},
+ { 5, 0x94, "NovaTech Solutions, S.A."},
+ { 5, 0x15, "c2 Microsystems"},
+ { 5, 0x16, "Level5 Networks"},
+ { 5, 0x97, "COS Memory AG"},
+ { 5, 0x98, "Innovasic Semiconductor"},
+ { 5, 0x19, "02IC Co."},
+ { 5, 0x1a, "Tabula,"},
+ { 5, 0x9b, "Crucial Technology"},
+ { 5, 0x1c, "Chelsio Communications"},
+ { 5, 0x9d, "Solarflare Communications"},
+ { 5, 0x9e, "Xambala"},
+ { 5, 0x1f, "EADS Astrium"},
+ { 5, 0x20, "Terra Semiconductor"},
+ { 5, 0xa1, "Imaging Works"},
+ { 5, 0xa2, "Astute Networks"},
+ { 5, 0x23, "Tzero"},
+ { 5, 0xa4, "Emulex"},
+ { 5, 0x25, "Power-One"},
+ { 5, 0x26, "Pulse~LINK"},
+ { 5, 0xa7, "Hon Hai Precision Industry"},
+ { 5, 0xa8, "White Rock Networks"},
+ { 5, 0x29, "Telegent Systems USA"},
+ { 5, 0x2a, "Atrua Technologies"},
+ { 5, 0xab, "Acbel Polytech"},
+ { 5, 0x2c, "eRide"},
+ { 5, 0xad, "ULi Electronics"},
+ { 5, 0xae, "Magnum Semiconductor"},
+ { 5, 0x2f, "neoOne Technology"},
+ { 5, 0xb0, "Connex Technology"},
+ { 5, 0x31, "Stream Processors"},
+ { 5, 0x32, "Focus Enhancements"},
+ { 5, 0xb3, "Telecis Wireless"},
+ { 5, 0x34, "uNav Microelectronics"},
+ { 5, 0xb5, "Tarari"},
+ { 5, 0xb6, "Ambric"},
+ { 5, 0x37, "Newport Media"},
+ { 5, 0x38, "VMTS"},
+ { 5, 0xb9, "Enuclia Semiconductor"},
+ { 5, 0xba, "Virtium Technology"},
+ { 5, 0x3b, "Solid State System Co."},
+ { 5, 0xbc, "Kian Tech LLC"},
+ { 5, 0x3d, "Artimi"},
+ { 5, 0x3e, "Power Quotient International"},
+ { 5, 0xbf, "Avago Technologies"},
+ { 5, 0x40, "ADTechnology"},
+ { 5, 0xc1, "Sigma Designs"},
+ { 5, 0xc2, "SiCortex"},
+ { 5, 0x43, "Ventura Technology Group"},
+ { 5, 0xc4, "eASIC"},
+ { 5, 0x45, "M.H.S. SAS"},
+ { 5, 0x46, "Micro Star International"},
+ { 5, 0xc7, "Rapport"},
+ { 5, 0xc8, "Makway International"},
+ { 5, 0x49, "Broad Reach Engineering Co."},
+ { 5, 0x4a, "Semiconductor Mfg Intl Corp"},
+ { 5, 0xcb, "SiConnect"},
+ { 5, 0x4c, "FCI USA"},
+ { 5, 0xcd, "Validity Sensors"},
+ { 5, 0xce, "Coney Technology Co."},
+ { 5, 0x4f, "Spans Logic"},
+ { 5, 0xd0, "Neterion"},
+ { 5, 0x51, "Qimonda"},
+ { 5, 0x52, "New Japan Radio Co."},
+ { 5, 0xd3, "Velogix"},
+ { 5, 0x54, "Montalvo Systems"},
+ { 5, 0xd5, "iVivity"},
+ { 5, 0xd6, "Walton Chaintech"},
+ { 5, 0x57, "AENEON"},
+ { 5, 0x58, "Lorom Industrial Co."},
+ { 5, 0xd9, "Radiospire Networks"},
+ { 5, 0xda, "Sensio Technologies"},
+ { 5, 0x5b, "Nethra Imaging"},
+ { 5, 0xdc, "Hexon Technology Pte"},
+ { 5, 0x5d, "CompuStocx (CSX)"},
+ { 5, 0x5e, "Methode Electronics"},
+ { 5, 0xdf, "Connect One"},
+ { 5, 0xe0, "Opulan Technologies"},
+ { 5, 0x61, "Septentrio NV"},
+ { 5, 0x62, "Goldenmars Technology"},
+ { 5, 0xe3, "Kreton"},
+ { 5, 0x64, "Cochlear"},
+ { 5, 0xe5, "Altair Semiconductor"},
+ { 5, 0xe6, "NetEffect"},
+ { 5, 0x67, "Spansion"},
+ { 5, 0x68, "Taiwan Semiconductor Mfg"},
+ { 5, 0xe9, "Emphany Systems"},
+ { 5, 0xea, "ApaceWave Technologies"},
+ { 5, 0x6b, "Mobilygen"},
+ { 5, 0xec, "Tego"},
+ { 5, 0x6d, "Cswitch"},
+ { 5, 0x6e, "Haier (Beijing) IC Design Co."},
+ { 5, 0xef, "MetaRAM"},
+ { 5, 0x70, "Axel Electronics Co."},
+ { 5, 0xf1, "Tilera"},
+ { 5, 0xf2, "Aquantia"},
+ { 5, 0x73, "Vivace Semiconductor"},
+ { 5, 0xf4, "Redpine Signals"},
+ { 5, 0x75, "Octalica"},
+ { 5, 0x76, "InterDigital Communications"},
+ { 5, 0xf7, "Avant Technology"},
+ { 5, 0xf8, "Asrock"},
+ { 5, 0x79, "Availink"},
+ { 5, 0x7a, "Quartics"},
+ { 5, 0xfb, "Element CXI"},
+ { 5, 0x7c, "Innovaciones Microelectronicas"},
+ { 5, 0xfd, "VeriSilicon Microelectronics"},
+ { 5, 0xfe, "W5 Networks"},
+ { 6, 0x01, "MOVEKING"},
+ { 6, 0x02, "Mavrix Technology"},
+ { 6, 0x83, "CellGuide"},
+ { 6, 0x04, "Faraday Technology"},
+ { 6, 0x85, "Diablo Technologies"},
+ { 6, 0x86, "Jennic"},
+ { 6, 0x07, "Octasic"},
+ { 6, 0x08, "Molex"},
+ { 6, 0x89, "3Leaf Networks"},
+ { 6, 0x8a, "Bright Micron Technology"},
+ { 6, 0x0b, "Netxen"},
+ { 6, 0x8c, "NextWave Broadband"},
+ { 6, 0x0d, "DisplayLink"},
+ { 6, 0x0e, "ZMOS Technology"},
+ { 6, 0x8f, "Tec-Hill"},
+ { 6, 0x10, "Multigig"},
+ { 6, 0x91, "Amimon"},
+ { 6, 0x92, "Euphonic Technologies"},
+ { 6, 0x13, "BRN Phoenix"},
+ { 6, 0x94, "InSilica"},
+ { 6, 0x15, "Ember"},
+ { 6, 0x16, "Avexir Technologies"},
+ { 6, 0x97, "Echelon"},
+ { 6, 0x98, "Edgewater Computer Systems"},
+ { 6, 0x19, "XMOS Semiconductor"},
+ { 6, 0x1a, "GENUSION"},
+ { 6, 0x9b, "Memory Corp NV"},
+ { 6, 0x1c, "SiliconBlue Technologies"},
+ { 6, 0x9d, "Rambus"},
+ { 6, 0x9e, "Andes Technology"},
+ { 6, 0x1f, "Coronis Systems"},
+ { 6, 0x20, "Achronix Semiconductor"},
+ { 6, 0xa1, "Siano Mobile Silicon"},
+ { 6, 0xa2, "Semtech"},
+ { 6, 0x23, "Pixelworks"},
+ { 6, 0xa4, "Gaisler Research AB"},
+ { 6, 0x25, "Teranetics"},
+ { 6, 0x26, "Toppan Printing Co."},
+ { 6, 0xa7, "Kingxcon"},
+ { 6, 0xa8, "Silicon Integrated Systems"},
+ { 6, 0x29, "I-O Data Device"},
+ { 6, 0x2a, "NDS Americas"},
+ { 6, 0xab, "Solomon Systech Limited"},
+ { 6, 0x2c, "On Demand Microelectronics"},
+ { 6, 0xad, "Amicus Wireless"},
+ { 6, 0xae, "SMARDTV SNC"},
+ { 6, 0x2f, "Comsys Communication"},
+ { 6, 0xb0, "Movidia"},
+ { 6, 0x31, "Javad GNSS"},
+ { 6, 0x32, "Montage Technology Group"},
+ { 6, 0xb3, "Trident Microsystems"},
+ { 6, 0x34, "Super Talent"},
+ { 6, 0xb5, "Optichron"},
+ { 6, 0xb6, "Future Waves UK"},
+ { 6, 0x37, "SiBEAM"},
+ { 6, 0x38, "Inicore,"},
+ { 6, 0xb9, "Virident Systems"},
+ { 6, 0xba, "M2000"},
+ { 6, 0x3b, "ZeroG Wireless"},
+ { 6, 0xbc, "Gingle Technology Co."},
+ { 6, 0x3d, "Space Micro"},
+ { 6, 0x3e, "Wilocity"},
+ { 6, 0xbf, "Novafora, Ic."},
+ { 6, 0x40, "iKoa"},
+ { 6, 0xc1, "ASint Technology"},
+ { 6, 0xc2, "Ramtron"},
+ { 6, 0x43, "Plato Networks"},
+ { 6, 0xc4, "IPtronics AS"},
+ { 6, 0x45, "Infinite-Memories"},
+ { 6, 0x46, "Parade Technologies"},
+ { 6, 0xc7, "Dune Networks"},
+ { 6, 0xc8, "GigaDevice Semiconductor"},
+ { 6, 0x49, "Modu"},
+ { 6, 0x4a, "CEITEC"},
+ { 6, 0xcb, "Northrop Grumman"},
+ { 6, 0x4c, "XRONET"},
+ { 6, 0xcd, "Sicon Semiconductor AB"},
+ { 6, 0xce, "Atla Electronics Co."},
+ { 6, 0x4f, "TOPRAM Technology"},
+ { 6, 0xd0, "Silego Technology"},
+ { 6, 0x51, "Kinglife"},
+ { 6, 0x52, "Ability Industries"},
+ { 6, 0xd3, "Silicon Power Computer & Communications"},
+ { 6, 0x54, "Augusta Technology"},
+ { 6, 0xd5, "Nantronics Semiconductors"},
+ { 6, 0xd6, "Hilscher Gesellschaft"},
+ { 6, 0x57, "Quixant"},
+ { 6, 0x58, "Percello"},
+ { 6, 0xd9, "NextIO"},
+ { 6, 0xda, "Scanimetrics"},
+ { 6, 0x5b, "FS-Semi Company"},
+ { 6, 0xdc, "Infinera"},
+ { 6, 0x5d, "SandForce"},
+ { 6, 0x5e, "Lexar Media"},
+ { 6, 0xdf, "Teradyne"},
+ { 6, 0xe0, "Memory Exchange Corp."},
+ { 6, 0x61, "Suzhou Smartek Electronics"},
+ { 6, 0x62, "Avantium"},
+ { 6, 0xe3, "ATP Electronics"},
+ { 6, 0x64, "Valens Semiconductor"},
+ { 6, 0xe5, "Agate Logic"},
+ { 6, 0xe6, "Netronome"},
+ { 6, 0x67, "Zenverge"},
+ { 6, 0x68, "N-trig"},
+ { 6, 0xe9, "SanMax Technologies"},
+ { 6, 0xea, "Contour Semiconductor"},
+ { 6, 0x6b, "TwinMOS"},
+ { 6, 0xec, "Silicon Systems"},
+ { 6, 0x6d, "V-Color Technology"},
+ { 6, 0x6e, "Certicom"},
+ { 6, 0xef, "JSC ICC Milandr"},
+ { 6, 0x70, "PhotoFast Global"},
+ { 6, 0xf1, "InnoDisk"},
+ { 6, 0xf2, "Muscle Power"},
+ { 6, 0x73, "Energy Micro"},
+ { 6, 0xf4, "Innofidei"},
+ { 9, 0xff, ""}
+};
+
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/lib.c
^
|
| @@ -2,17 +2,37 @@
*
* Released under version 2 of the Gnu Public License.
* By Chris Brady, cbrady@sgi.com
- */
+ * ----------------------------------------------------
+ * MemTest86+ V4.00 Specific code (GPL V2.0)
+ * By Samuel DEMEULEMEESTER, memtest@memtest.org
+ * http://www.canardplus.com - http://www.memtest.org
+*/
+
#include "io.h"
#include "serial.h"
#include "test.h"
#include "config.h"
#include "screen_buffer.h"
+#include "smp.h"
-extern int fast_mode;
+#define NULL 0
int slock = 0, lsr = 0;
short serial_cons = SERIAL_CONSOLE_DEFAULT;
+
+#if SERIAL_TTY != 0 && SERIAL_TTY != 1
+#error Bad SERIAL_TTY. Only ttyS0 and ttyS1 are supported.
+#endif
+short serial_tty = SERIAL_TTY;
+const short serial_base_ports[] = {0x3f8, 0x2f8, 0x3e8, 0x2e8};
+
+#if ((115200%SERIAL_BAUD_RATE) != 0)
+#error Bad default baud rate
+#endif
+int serial_baud_rate = SERIAL_BAUD_RATE;
+unsigned char serial_parity = 0;
+unsigned char serial_bits = 8;
+
char buf[18];
struct ascii_map_str {
@@ -44,6 +64,8 @@
};
struct eregs {
+ ulong ss;
+ ulong ds;
ulong esp;
ulong ebp;
ulong esi;
@@ -71,6 +93,33 @@
return 0;
}
+void memcpy (void *dst, void *src, int len)
+{
+ char *s = (char*)src;
+ char *d = (char*)dst;
+ int i;
+
+ if (len <= 0) {
+ return;
+ }
+ for (i = 0 ; i < len; i++) {
+ *d++ = *s++;
+ }
+}
+int strncmp(const char *s1, const char *s2, ulong n) {
+ signed char res = 0;
+ while (n) {
+ res = *s1 - *s2;
+ if (res != 0)
+ return res;
+ if (*s1 == '\0')
+ return 0;
+ ++s1, ++s2;
+ --n;
+ }
+ return res;
+}
+
void *memmove(void *dest, const void *src, ulong n)
{
long i;
@@ -89,6 +138,52 @@
}
return dest;
}
+
+char toupper(char c)
+{
+ if (c >= 'a' && c <= 'z')
+ return c + 'A' -'a';
+ else
+ return c;
+}
+
+int isdigit(char c)
+{
+ return c >= '0' && c <= '9';
+}
+
+int isxdigit(char c)
+{
+ return isdigit(c) || (toupper(c) >= 'A' && toupper(c) <= 'F'); }
+
+unsigned long simple_strtoul(const char *cp, char **endp, unsigned int base) {
+ unsigned long result = 0, value;
+
+ if (!base) {
+ base = 10;
+ if (*cp == '0') {
+ base = 8;
+ cp++;
+ if (toupper(*cp) == 'X' && isxdigit(cp[1])) {
+ cp++;
+ base = 16;
+ }
+ }
+ } else if (base == 16) {
+ if (cp[0] == '0' && toupper(cp[1]) == 'X')
+ cp += 2;
+ }
+ while (isxdigit(*cp) &&
+ (value = isdigit(*cp) ? *cp-'0' : toupper(*cp)-'A'+10) < base) {
+ result = result*base + value;
+ cp++;
+ }
+ if (endp)
+ *endp = (char *)cp;
+ return result;
+}
+
+
/*
* Scroll the error message area of the screen as needed
* Starts at line LINE_SCROLL and ends at line 23
@@ -126,6 +221,21 @@
}
/*
+ * Clear scroll region
+ */
+void clear_scroll(void)
+{
+ int i;
+ char *s;
+
+ s = (char*)(SCREEN_ADR+LINE_HEADER*160);
+ for(i=0; i<80*(24-LINE_HEADER); i++) {
+ *s++ = ' ';
+ *s++ = 0x17;
+ }
+}
+
+/*
* Print characters on screen
*/
void cprint(int y, int x, const char *text)
@@ -251,6 +361,25 @@
cprint(y,x,buf);
}
+
+/*
+ * Get_number of digits
+ */
+int getnum(ulong val)
+{
+ int len = 0;
+ int i = 1;
+
+ while(i <= val)
+ {
+ len++;
+ i *= 10;
+ }
+
+ return len;
+
+}
+
/*
* Print a hex number on screen at least digits long
*/
@@ -402,7 +531,10 @@
hprint(line+8, 25, trap_regs->ebp);
cprint(line+9, 20, "esp: ");
hprint(line+9, 25, trap_regs->esp);
-
+ cprint(line+7, 0, " DS: ");
+ hprint(line+7, 7, trap_regs->ds);
+ cprint(line+8, 0, " SS: ");
+ hprint(line+8, 7, trap_regs->ss);
cprint(line+1, 38, "Stack:");
for (i=0; i<12; i++) {
hprint(line+2+i, 38, trap_regs->esp+(4*i));
@@ -611,21 +743,7 @@
shift -= result_shift;
/* Compute our current value */
- val = 0;
- for(i = (base == 16)? 2: 0; i < n; i++) {
- unsigned long digit = 0;
- if ((buf[i] >= '0') && (buf[i] <= '9')) {
- digit = buf[i] - '0';
- }
- else if ((buf[i] >= 'a') && (buf[i] <= 'f')) {
- digit = buf[i] - 'a' + 10;
- }
- else {
- /* It must be a suffix byte */
- break;
- }
- val = (val * base) + digit;
- }
+ val = simple_strtoul(buf, NULL, base);
if (shift > 0) {
if (shift >= 32) {
val = 0xffffffff;
@@ -661,19 +779,11 @@
serial_echo_print(p);
}
-#if defined(SERIAL_BAUD_RATE)
-
-#if ((115200%SERIAL_BAUD_RATE) != 0)
-#error Bad ttys0 baud rate
-#endif
-
-#define SERIAL_DIV (115200/SERIAL_BAUD_RATE)
-
-#endif /* SERIAL_BAUD_RATE */
void serial_echo_init(void)
{
- int comstat, hi, lo;
+ int comstat, hi, lo, serial_div;
+ unsigned char lcr;
/* read the Divisor Latch */
comstat = serial_echo_inb(UART_LCR);
@@ -683,13 +793,14 @@
serial_echo_outb(comstat, UART_LCR);
/* now do hardwired init */
- serial_echo_outb(0x03, UART_LCR); /* No parity, 8 data bits, 1 stop */
-#if defined(SERIAL_BAUD_RATE)
- serial_echo_outb(0x83, UART_LCR); /* Access divisor latch */
- serial_echo_outb(SERIAL_DIV & 0xff, UART_DLL); /* baud rate divisor */
- serial_echo_outb((SERIAL_DIV>> 8) & 0xff, UART_DLM);
- serial_echo_outb(0x03, UART_LCR); /* Done with divisor */
-#endif
+ lcr = serial_parity | (serial_bits - 5);
+ serial_echo_outb(lcr, UART_LCR); /* No parity, 8 data bits, 1 stop */
+ serial_div = 115200 / serial_baud_rate;
+ serial_echo_outb(0x80|lcr, UART_LCR); /* Access divisor latch */
+ serial_echo_outb(serial_div & 0xff, UART_DLL); /* baud rate divisor */
+ serial_echo_outb((serial_div >> 8) & 0xff, UART_DLM);
+ serial_echo_outb(lcr, UART_LCR); /* Done with divisor */
+
/* Prior to disabling interrupts, read the LSR and RBR
* registers */
@@ -914,6 +1025,97 @@
}
}
}
+
+
+/*
+ * Handles "console=<param>" command line option
+ *
+ * Examples of accepted params:
+ * ttyS0
+ * ttyS1
+ * ttyS0,115200
+ * ttyS0,9600e8
+ */
+void serial_console_setup(char *param)
+{
+ char *option, *end;
+ unsigned long tty;
+ unsigned long baud_rate;
+ unsigned char parity, bits;
+
+ if (strncmp(param, "ttyS", 4))
+ return; /* not a serial port */
+
+ param += 4;
+
+ tty = simple_strtoul(param, &option, 10);
+
+ if (option == param)
+ return; /* there were no digits */
+
+ if (tty > 3)
+ return; /* only ttyS0 to ttyS3 supported */
+
+ if (*option == '\0' || *option == ' ')
+ goto save_tty; /* no options given, just ttyS? */
+
+ if (*option != ',')
+ return; /* missing the comma separator */
+
+ /* baud rate must follow */
+ option++;
+ baud_rate = simple_strtoul(option, &end, 10);
+
+ if (end == option)
+ return; /* no baudrate after comma */
+
+ if (baud_rate == 0 || (115200 % baud_rate) != 0)
+ return; /* wrong baud rate */
+
+ if (*end == '\0' || *end == ' ')
+ goto save_baud_rate; /* no more options given */
+
+ switch (toupper(*end)) {
+ case 'N':
+ parity = 0;
+ break;
+ case 'O':
+ parity = UART_LCR_PARITY;
+ break;
+ case 'E':
+ parity = UART_LCR_PARITY | UART_LCR_EPAR;
+ break;
+ default:
+ /* Unknown parity */
+ return;
+ }
+
+ end++;
+ if (*end == '\0' || *end == ' ')
+ goto save_parity;
+
+ /* word length (bits) */
+ if (*end < '7' || *end > '8')
+ return; /* invalid number of bits */
+
+ bits = *end - '0';
+
+ end++;
+
+ if (*end != '\0' && *end != ' ')
+ return; /* garbage at the end */
+
+ serial_bits = bits;
+ save_parity:
+ serial_parity = parity;
+ save_baud_rate:
+ serial_baud_rate = (int) baud_rate;
+ save_tty:
+ serial_tty = (short) tty;
+ serial_cons = 1;
+}
+
+
#ifdef LP
#define DATA 0x00
#define STATUS 0x01
@@ -970,5 +1172,6 @@
outb((LP_PSELECP | LP_PINITP), CONTROL(port));
lp_wait(DELAY);
}
+
#endif
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/linuxbios.c
^
|
| @@ -115,11 +115,22 @@
struct lb_header *head;
struct lb_record *rec;
struct lb_memory *mem;
+ struct lb_forward *forward;
int i, entries;
+
head = find_lb_table();
if (!head) {
return 0;
}
+
+ /* coreboot also can forward the table to the high tables area. */
+ rec = (struct lb_record *)(((char *)head) + sizeof(*head));
+ if (rec->tag == LB_TAG_FORWARD) {
+ forward = (struct lb_forward *)rec;
+ head = (struct lb_header *)(unsigned long)(forward->forward);
+ if (!head) { return 0; }
+ }
+
mem = 0;
for_each_lbrec(head, rec) {
if (rec->tag == LB_TAG_MEMORY) {
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/linuxbios_tables.h
^
|
| @@ -56,6 +56,7 @@
#define LB_TAG_UNUSED 0x0000
#define LB_TAG_MEMORY 0x0001
+#define LB_TAG_FORWARD 0x0011
struct lb_memory_range {
uint64_t start;
@@ -79,4 +80,10 @@
uint64_t hwrpb;
};
+struct lb_forward {
+ uint32_t tag;
+ uint32_t size;
+ uint64_t forward;
+};
+
#endif /* LINUXBIOS_TABLES_H */
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/main.c
^
|
| @@ -3,34 +3,35 @@
* Released under version 2 of the Gnu Public License.
* By Chris Brady
* ----------------------------------------------------
- * MemTest86+ V1.65 Specific code (GPL V2.0)
+ * MemTest86+ V4.00 Specific code (GPL V2.0)
* By Samuel DEMEULEMEESTER, sdemeule@memtest.org
- * http://www.x86-secret.com - http://www.memtest.org
+ * http://www.canardpc.com - http://www.memtest.org
*/
#include "test.h"
#include "defs.h"
+#include "config.h"
#undef TEST_TIMES
-#define DEFTESTS 11
+#define DEFTESTS 9
extern void bzero();
const struct tseq tseq[] = {
- {1, 5, 3, 0, 0, "[Address test, walking ones] "},
- {1, 6, 3, 2, 0, "[Address test, own address] "},
- {1, 0, 3, 14, 0, "[Moving inversions, ones & zeros] "},
- {1, 1, 2, 80, 0, "[Moving inversions, 8 bit pattern] "},
- {1, 10, 60, 300, 0, "[Moving inversions, random pattern] "},
- {1, 7, 64, 66, 0, "[Block move, 64 moves] "},
- {1, 2, 2, 320, 0, "[Moving inversions, 32 bit pattern] "},
- {1, 9, 40, 120, 0, "[Random number sequence] "},
- {1, 3, 4, 240, 0, "[Modulo 20, ones & zeros] "},
- {1, 8, 1, 2, 0, "[Bit fade test, 90 min, 2 patterns] "},
- {0, 4, 3, 2, 0, "[[Moving inversions, 0 & 1, uncached] "},
- {0, 0, 0, 0, 0, NULL}
+ {1, 5, 4, 0, "[Address test, walking ones] "},
+ {1, 6, 4, 0, "[Address test, own address] "},
+ {1, 0, 4, 0, "[Moving inversions, ones & zeros] "},
+ {1, 1, 2, 0, "[Moving inversions, 8 bit pattern] "},
+ {1, 10, 50, 0, "[Moving inversions, random pattern] "},
+ {1, 7, 80, 0, "[Block move, 80 moves] "},
+ {1, 2, 2, 0, "[Moving inversions, 32 bit pattern] "},
+ {1, 9, 30, 0, "[Random number sequence] "},
+ {1, 11, 6, 0, "[Modulo 20, Random pattern] "},
+ {1, 8, 1, 0, "[Bit fade test, 90 min, 2 patterns] "},
+ {0, 0, 0, 0, NULL}
};
char firsttime = 0;
+char cmdline_parsed = 0;
struct vars variables = {};
struct vars * const v = &variables;
@@ -40,13 +41,16 @@
int segs = 0, bail = 0;
int test_ticks;
int nticks;
+ulong high_test_adr = 0x200000;
static int window = 0;
+static int c_iter;
static struct pmap windows[] =
{
- { 0/* Written at startup */, 0x100000 },
- { 0, RES_START >> 12 },
+ { 0, 0x080000 },
+ { 0, 0 },
+ { 0x080000, 0x100000 },
{ 0x100000, 0x180000 },
{ 0x180000, 0x200000 },
@@ -93,19 +97,18 @@
{ 0xF80000, 0x1000000 },
};
-#if (LOW_TEST_ADR >= HIGH_TEST_ADR)
-#error LOW_TEST_ADR and HIGH_TEST_ADR may not overlap
-#endif
+
#if (LOW_TEST_ADR > (640*1024))
#error LOW_TEST_ADR must be below 640K
#endif
-static int find_ticks_for_test(unsigned long chunks, int test);
-static void compute_segments(int win);
+static int find_ticks_for_test(int ch, int test);
+static int compute_segments(int win);
+void find_ticks_for_pass(void);
static void __run_at(unsigned long addr)
{
- /* Copy memtest86 code */
+ /* Copy memtest86+ code */
memmove((void *)addr, &_start, _end - _start);
/* Jump to the start address */
p = (ulong *)(addr + startup_32 - _start);
@@ -125,8 +128,8 @@
if ( ((start < addr) && ((start + len) >= addr)) ||
((addr < start) && ((addr + len) >= start))) {
/* Handle overlap by doing an extra relocation */
- if (addr + len < HIGH_TEST_ADR) {
- __run_at(HIGH_TEST_ADR);
+ if (addr + len < high_test_adr) {
+ __run_at(high_test_adr);
}
else if (start + len < addr) {
__run_at(LOW_TEST_ADR);
@@ -135,12 +138,54 @@
__run_at(run_at_addr);
}
+/* command line passing using the 'old' boot protocol */
+#define MK_PTR(seg,off) ((void*)(((unsigned long)(seg) << 4) + (off)))
+#define OLD_CL_MAGIC_ADDR ((unsigned short*) MK_PTR(INITSEG,0x20))
+#define OLD_CL_MAGIC 0xA33F
+#define OLD_CL_OFFSET_ADDR ((unsigned short*) MK_PTR(INITSEG,0x22))
+
+static void parse_command_line(void)
+{
+ char *cmdline;
+
+ if (cmdline_parsed)
+ return;
+
+ if (*OLD_CL_MAGIC_ADDR != OLD_CL_MAGIC)
+ return;
+
+ unsigned short offset = *OLD_CL_OFFSET_ADDR;
+ cmdline = MK_PTR(INITSEG, offset);
+
+ /* skip leading spaces */
+ while (*cmdline == ' ')
+ cmdline++;
+
+ while (*cmdline) {
+ if (!strncmp(cmdline, "console=", 8)) {
+ cmdline += 8;
+ serial_console_setup(cmdline);
+ }
+
+ /* go to the next parameter */
+ while (*cmdline && *cmdline != ' ')
+ cmdline++;
+ while (*cmdline == ' ')
+ cmdline++;
+ }
+
+ cmdline_parsed = 1;
+}
+
+
void do_test(void)
{
- int i = 0;
+ int i = 0, j = 0;
unsigned long chunks;
unsigned long lo, hi;
+ parse_command_line();
+
/* If we have a partial relocation finish it */
if (run_at_addr == (unsigned long)&_start) {
run_at_addr = 0xffffffff;
@@ -153,9 +198,19 @@
if ((ulong)&_start != LOW_TEST_ADR) {
restart();
}
- windows[0].start =
- ( LOW_TEST_ADR + (_end - _start) + 4095) >> 12;
+
init();
+
+ find_ticks_for_pass();
+
+ windows[0].start =
+ ( LOW_TEST_ADR + (_end - _start) + 4095) >> 12;
+
+ /* Set relocation address at 16Mb if there is enough memory */
+ if (v->pmap[v->msegs-1].end > 0x1100) {
+ high_test_adr = 0x01000000;
+ }
+ windows[1].end = (high_test_adr >> 12);
firsttime = 1;
}
bail = 0;
@@ -170,6 +225,24 @@
goto skip_window;
}
+ if ((ulong)&_start > LOW_TEST_ADR) {
+ /* Relocated so we need to test all selected lower memory */
+ v->map[0].start = mapping(v->plim_lower);
+
+#ifdef USB_WAR
+ /* We must not touch test below 0x500 memory beacuase
+ * BIOS USB support clobbers location 0x410 and 0x4e0
+ */
+ if ((ulong)v->map[0].start < 0x500) {
+ v->map[0].start = (ulong*)0x500;
+ }
+#endif
+
+ cprint(LINE_RANGE, COL_MID+28, " Relocated");
+ } else {
+ cprint(LINE_RANGE, COL_MID+28, " ");
+ }
+
/* Update display of memory segments being tested */
lo = page_of(v->map[0].start);
hi = page_of(v->map[segs -1].end);
@@ -177,8 +250,7 @@
cprint(LINE_RANGE, COL_MID+14, " - ");
aprint(LINE_RANGE, COL_MID+17, hi);
aprint(LINE_RANGE, COL_MID+23, v->selected_pages);
- cprint(LINE_RANGE, COL_MID+28,
- ((ulong)&_start == LOW_TEST_ADR)?" ":" Relocated");
+
#ifdef TEST_TIMES
{
@@ -213,6 +285,13 @@
if (v->testsel >= 0) {
v->test = v->testsel;
}
+
+ if (v->pass == 0) {
+ c_iter = tseq[v->test].iter/2;
+ } else {
+ c_iter = tseq[v->test].iter;
+ }
+
dprint(LINE_TST, COL_MID+6, v->test, 2, 1);
cprint(LINE_TST, COL_MID+9, tseq[v->test].msg);
set_cache(tseq[v->test].cache);
@@ -231,88 +310,128 @@
switch(tseq[v->test].pat) {
/* Now do the testing according to the selected pattern */
- case 0: /* Moving inversions, all ones and zeros */
- case 1: /* Moving inversions, 8 bit wide walking ones and zeros. */
- case 4:
+ case 0: /* Moving inversions, all ones and zeros (test #2) */
+ p1 = 0;
+ p2 = ~p1;
+ movinv1(c_iter,p1,p2);
+ BAILOUT;
- if (tseq[v->test].pat == 1)
- p0 = 0x80808080;
- else
- p0 = 0;
-
- for ( ; ; ) {
- movinv1(tseq[v->test].iter,p0,~p0);
+ /* Switch patterns */
+ p2 = p1;
+ p1 = ~p2;
+ movinv1(c_iter,p1,p2);
+ BAILOUT;
+ break;
+
+ case 1: /* Moving inversions, 8 bit walking ones and zeros (test #3) */
+ p0 = 0x80;
+ for (i=0; i<8; i++, p0=p0>>1) {
+ p1 = p0 | (p0<<8) | (p0<<16) | (p0<<24);
+ p2 = ~p1;
+ movinv1(c_iter,p1,p2);
BAILOUT;
-
+
/* Switch patterns */
- movinv1(tseq[v->test].iter,~p0,p0);
+ p2 = p1;
+ p1 = ~p2;
+ movinv1(c_iter,p1,p2);
BAILOUT
- if ( !((unsigned char)(p0 >>= 1) & 0x7F) )
- break;
}
break;
-
- case 2: /* Moving inversions, 32 bit shifting pattern, very long */
+ case 2: /* Moving inversions, 32 bit shifting pattern (test #6) */
for (i=0, p1=1; p1; p1=p1<<1, i++) {
- movinv32(tseq[v->test].iter,p1, 1, 0x80000000, 0, i);
+ movinv32(c_iter,p1, 1, 0x80000000, 0, i);
BAILOUT
- movinv32(tseq[v->test].iter,~p1, 0xfffffffe, 0x7fffffff, 1, i);
+ movinv32(c_iter,~p1, 0xfffffffe,
+ 0x7fffffff, 1, i);
BAILOUT
}
break;
- case 3: /* Modulo X check, all ones and zeros */
+ case 3: /* Modulo 20 check, all ones and zeros (unused) */
p1=0;
for (i=0; i<MOD_SZ; i++) {
p2 = ~p1;
- modtst(i, tseq[v->test].iter, p1, p2);
+ modtst(i, c_iter, p1, p2);
BAILOUT
/* Switch patterns */
p2 = p1;
p1 = ~p2;
- modtst(i, tseq[v->test].iter, p1,p2);
+ modtst(i, c_iter, p1,p2);
BAILOUT
}
break;
- case 5: /* Address test, walking ones */
+ case 4: /* Modulo 20 check, 8 bit pattern (unused) */
+ p0 = 0x80;
+ for (j=0; j<8; j++, p0=p0>>1) {
+ p1 = p0 | (p0<<8) | (p0<<16) | (p0<<24);
+ for (i=0; i<MOD_SZ; i++) {
+ p2 = ~p1;
+ modtst(i, c_iter, p1, p2);
+ BAILOUT
+
+ /* Switch patterns */
+ p2 = p1;
+ p1 = ~p2;
+ modtst(i, c_iter, p1, p2);
+ BAILOUT
+ }
+ }
+ break;
+ case 5: /* Address test, walking ones (test #0) */
addr_tst1();
BAILOUT;
break;
- case 6: /* Address test, own address */
+ case 6: /* Address test, own address (test #1) */
addr_tst2();
BAILOUT;
break;
- case 7: /* Block move test */
- block_move(tseq[v->test].iter);
+ case 7: /* Block move (test #5) */
+ block_move(c_iter);
BAILOUT;
break;
-
- case 8: /* Bit fade test */
+ case 8: /* Bit fade test (test #9) */
if (window == 0 ) {
bit_fade();
}
BAILOUT;
break;
-
- case 9: /* Random Data Sequence */
- for (i=0; i < tseq[v->test].iter; i++) {
+ case 9: /* Random Data Sequence (test #7) */
+ for (i=0; i < c_iter; i++) {
movinvr();
BAILOUT;
}
break;
- case 10: /* Random Data */
- for (i=0; i < tseq[v->test].iter; i++) {
+ case 10: /* Random Data (test #4) */
+ for (i=0; i < c_iter; i++) {
p1 = rand();
p2 = ~p1;
movinv1(2,p1,p2);
BAILOUT;
}
break;
+
+ case 11: /* Modulo 20 check, Random pattern (test #8) */
+ for (j=0; j<c_iter; j++) {
+ p1 = rand();
+ for (i=0; i<MOD_SZ; i++) {
+ p2 = ~p1;
+ modtst(i, 2, p1, p2);
+ BAILOUT
+
+ /* Switch patterns */
+ p2 = p1;
+ p1 = ~p2;
+ modtst(i, 2, p1, p2);
+ BAILOUT
+ }
+ }
+ break;
}
skip_window:
if (bail) {
@@ -333,15 +452,15 @@
* The lower limit is less than START_ADR
* - There is more than 1 meg of memory
*/
- if (windows[window].start <
- (LOW_TEST_ADR + (_end - _start)) >> 12) {
- if (v->pmap[v->msegs-1].end >
- (((HIGH_TEST_ADR + (_end - _start)) >> 12) +1)) {
+ if (windows[window].start <
+ ((ulong)&_start + (_end - _start)) >> 12) {
+ if (v->pmap[v->msegs-1].end >
+ (((high_test_adr + (_end - _start)) >> 12)+1)) {
/* We need the high copy and we have enough
* memory so use it.
*/
- run_at(HIGH_TEST_ADR);
- } else {
+ run_at(high_test_adr);
+ } else {
/* We can't use this window so skip it */
goto skip_window;
}
@@ -374,8 +493,18 @@
v->pptr = 0;
cprint(0, COL_MID+8,
" ");
+ if (v->ecount == 0 && v->testsel < 0) {
+ cprint(LINE_MSG+5, 0,
+ " *****Pass complete, no errors, press Esc to exit***** ");
+ if(BEEP_END_NO_ERROR) {
+ beep(1000);
+ beep(2000);
+ beep(1000);
+ beep(2000);
+ }
+ }
}
-
+
/* We always start a pass with the low copy */
run_at(LOW_TEST_ADR);
}
@@ -401,9 +530,7 @@
run_at(LOW_TEST_ADR);
}
-
-/* Compute the total number of ticks per pass */
-void find_ticks(void)
+void find_ticks_for_pass(void)
{
int i, j, chunks;
@@ -433,18 +560,62 @@
}
}
-static int find_ticks_for_test(unsigned long chunks, int test)
+
+static int find_ticks_for_test(int ch, int test)
{
- int ticks;
- ticks = chunks * tseq[test].ticks;
- if (tseq[test].pat == 5) {
- /* Address test, walking ones */
+ int ticks=0, c;
+
+ /* Set the number of iterations. We only do half of the iterations */
+ /* on the first pass */
+ if (v->pass == 0 && FIRST_PASS_HALF_ITERATIONS) {
+ c = tseq[test].iter/2;
+ } else {
+ c = tseq[test].iter;
+ }
+
+ switch(tseq[test].pat) {
+ case 0: /* Moving inversions, all ones and zeros (test #2) */
+ ticks = 2 + 4 * c;
+ break;
+ case 1: /* Moving inversions, 8 bit walking ones and zeros (test #3) */
+ ticks = 24 + 24 * c;
+ break;
+ case 2: /* Moving inversions, 32 bit shifting pattern, very long */
+ ticks = (1 + c * 2) * 80;
+ break;
+ case 3: /* Modulo 20 check, all ones and zeros (unused) */
+ ticks = (2 + c) * 40;
+ break;
+ case 4: /* Modulo 20 check, 8 bit pattern (unused) */
+ ticks = (2 + c) * 40 * 8;
+ break;
+ case 5: /* Address test, walking ones (test #0) */
ticks = 4;
+ break;
+ case 6: /* Address test, own address (test #1) */
+ ticks = 2;
+ break;
+ case 7: /* Block move (test #5) */
+ ticks = 2 + c;
+ break;
+ case 8: /* Bit fade test (test #9) */
+ ticks = 1;
+ break;
+ case 9: /* Random Data Sequence (test #7) */
+ ticks = 3 * c;
+ break;
+ case 10: /* Random Data (test #4) */
+ ticks = c + 4 * c;
+ break;
+ case 11: /* Modulo 20 check, Random pattern (test #8) */
+ ticks = 4 * 40 * c;
+ break;
}
- return ticks;
+
+ return ticks*ch;
}
-static void compute_segments(int win)
+static int compute_segments(int win)
{
unsigned long wstart, wend;
int i;
@@ -462,7 +633,7 @@
wend = v->plim_upper;
}
if (wstart >= wend) {
- return;
+ return(0);
}
/* List the segments being tested */
for (i=0; i< v->msegs; i++) {
@@ -508,11 +679,11 @@
cprint(LINE_SCROLL+(2*i+1), 44, "i=");
hprint(LINE_SCROLL+(2*i+1), 46, i);
-
- cprint(LINE_SCROLL+(2*i+2), 0,
+
+ cprint(LINE_SCROLL+(2*i+2), 0,
" "
" ");
- cprint(LINE_SCROLL+(2*i+3), 0,
+ cprint(LINE_SCROLL+(2*i+3), 0,
" "
" ");
#endif
@@ -521,10 +692,12 @@
v->map[segs].start = mapping(start);
v->map[segs].end = emapping(end);
#if 0
- cprint(LINE_SCROLL+(2*i+1), 54, " segs: ");
- hprint(LINE_SCROLL+(2*i+1), 61, segs);
+ cprint(LINE_SCROLL+(2*i+1), 54, " sg: ");
+ hprint(LINE_SCROLL+(2*i+1), 61, sg);
#endif
segs++;
}
}
+ return (segs);
}
+
|
|
[-]
[+]
|
Added |
memtest86+-4.20.tar.bz2/makedos.sh
^
|
| @@ -0,0 +1,10 @@
+#!/bin/bash
+
+if [ -f memtest.bin ]
+then
+CSIZE="$(awk 'NR==16' mt86+_loader.asm | awk '{print $2}')";
+NSIZE="$(ls -l memtest.bin | awk '{print $5}')";
+sed "s/$CSIZE/$NSIZE/" mt86+_loader.asm > mt86+_loader.asm.new;
+mv mt86+_loader.asm.new mt86+_loader.asm;
+nasm mt86+_loader.asm;
+fi
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/makeiso.sh
^
|
| @@ -18,22 +18,28 @@
exit 1
fi
+
# enlarge the size of memtest.bin
SIZE=$(wc -c memtest.bin | awk '{print $1}')
FILL=$((1474560 - $SIZE))
dd if=/dev/zero of=fill.tmp bs=$FILL count=1
-cat memtest.bin fill.tmp >memtest.img
+cat memtest.bin fill.tmp > memtest.img
rm -f fill.tmp
-echo "generating iso image ..."
+echo "Generating iso image ..."
mkdir "cd"
mkdir "cd/boot"
mv memtest.img cd/boot
cd cd
-mkisofs -b boot/memtest.img -c boot/boot.catalog -o memtest.iso .
-mv memtest.iso ..
+
+# Create the cd.README
+echo -e "There is nothing to do here\r\r\nMemtest86+ is located on the bootsector of this CD\r\r\n" > README.TXT
+echo -e "Just boot from this CD and Memtest86+ will launch" >> README.TXT
+
+mkisofs -A "MKISOFS 1.1.2" -p "Memtest86+ 4.20" -publisher "Samuel D. <sdemeule@memtest.org>" -b boot/memtest.img -c boot/boot.catalog -V "MT410" -o memtest.iso .
+mv memtest.iso ../mt420.iso
cd ..
rm -rf cd
-echo "done"
+echo "Done! Memtest86+ 4.20 ISO is mt420.iso"
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/memsize.c
^
|
| @@ -1,4 +1,4 @@
-/* memsize.c - MemTest-86 Version 3.2
+/* memsize.c - MemTest-86 Version 3.3
*
* Released under version 2 of the Gnu Public License.
* By Chris Brady
@@ -21,11 +21,11 @@
static void sort_pmap(void);
static int check_ram(void);
-static void memsize_bios(int res);
-static void memsize_820(int res);
+static void memsize_bios(void);
+static void memsize_820(void);
static void memsize_801(void);
-static int sanitize_e820_map(struct e820entry *orig_map, struct e820entry *new_bios,
- short old_nr, short res);
+static int sanitize_e820_map(struct e820entry *orig_map,
+ struct e820entry *new_bios, short old_nr);
static void memsize_linuxbios();
static void memsize_probe(void);
static int check_ram(void);
@@ -56,16 +56,12 @@
switch (memsz_mode) {
case SZ_MODE_BIOS:
/* Get the memory size from the BIOS */
- memsize_bios(0);
- break;
- case SZ_MODE_BIOS_RES:
- /* Get the memory size from the BIOS, include reserved mem */
- memsize_bios(1);
+ memsize_bios();
break;
case SZ_MODE_PROBE:
/* Probe to find memory */
memsize_probe();
- cprint(LINE_INFO, COL_MMAP, " Probed ");
+ cprint(LINE_INFO, COL_MMAP, "Probed");
break;
}
/* Guarantee that pmap entries are in ascending order */
@@ -77,10 +73,10 @@
aprint(LINE_INFO, COL_RESERVED, v->reserved_pages);
}
-static void memsize_bios(int res)
+static void memsize_bios()
{
if (firmware == FIRMWARE_PCBIOS) {
- memsize_820(res);
+ memsize_820();
}
else if (firmware == FIRMWARE_LINUXBIOS) {
memsize_linuxbios();
@@ -105,7 +101,7 @@
if (i != j) {
struct pmap temp;
temp = v->pmap[i];
- memmove(&v->pmap[j], &v->pmap[j+1],
+ memmove(&v->pmap[j], &v->pmap[j+1],
(i -j)* sizeof(temp));
v->pmap[j] = temp;
}
@@ -129,16 +125,15 @@
n++;
}
v->msegs = n;
- cprint(LINE_INFO, COL_MMAP, "LinuxBIOS");
+ cprint(LINE_INFO, COL_MMAP, "LxBIOS");
}
-static void memsize_820(int res)
+static void memsize_820()
{
int i, n, nr;
struct e820entry nm[E820MAX];
/* Clean up, adjust and copy the BIOS-supplied E820-map. */
- /* If the res arg is true reclassify reserved memory as E820_RAM */
- nr = sanitize_e820_map(e820, nm, e820_nr, res);
+ nr = sanitize_e820_map(e820, nm, e820_nr);
/* If there is not a good 820 map use the BIOS 801/88 info */
if (nr < 1 || nr > E820MAX) {
@@ -149,7 +144,7 @@
/* Build the memory map for testing */
n = 0;
for (i=0; i<nr; i++) {
- if (nm[i].type == E820_RAM) {
+ if (nm[i].type == E820_RAM || nm[i].type == E820_ACPI) {
unsigned long long start;
unsigned long long end;
start = nm[i].addr;
@@ -169,24 +164,14 @@
v->pmap[n].end = end >> 12;
v->test_pages += v->pmap[n].end - v->pmap[n].start;
n++;
- } else {
- /* If this is reserved memory starting at the top
- * of memory then don't count it as reserved, since
- * it is very unlikely to be real memory.
- */
- if (nm[i].addr < 0xff000000) {
- v->reserved_pages += nm[i].size >> 12;
- }
+ } else if (nm[i].type == E820_NVS) {
+ v->reserved_pages += nm[i].size >> 12;
}
}
v->msegs = n;
- if (res) {
- cprint(LINE_INFO, COL_MMAP, "e820-All");
- } else {
- cprint(LINE_INFO, COL_MMAP, "e820-Std");
- }
+ cprint(LINE_INFO, COL_MMAP, " e820");
}
-
+
static void memsize_801(void)
{
ulong mem_size;
@@ -196,10 +181,10 @@
if (alt_mem_k < ext_mem_k) {
mem_size = ext_mem_k;
- cprint(LINE_INFO, COL_MMAP, "e88-Std ");
+ cprint(LINE_INFO, COL_MMAP, " e88");
} else {
mem_size = alt_mem_k;
- cprint(LINE_INFO, COL_MMAP, "e801-Std");
+ cprint(LINE_INFO, COL_MMAP, " e801");
}
/* First we map in the first 640k */
v->pmap[0].start = 0;
@@ -216,12 +201,12 @@
/*
* Sanitize the BIOS e820 map.
*
- * Some e820 responses include overlapping entries. The following
+ * Some e820 responses include overlapping entries. The following
* replaces the original e820 map with a new one, removing overlaps.
*
*/
static int sanitize_e820_map(struct e820entry *orig_map, struct e820entry *new_bios,
- short old_nr, short res)
+ short old_nr)
{
struct change_member {
struct e820entry *pbios; /* pointer to original bios entry */
@@ -284,22 +269,6 @@
for (i=0; i<old_nr; i++) {
if (biosmap[i].addr + biosmap[i].size < biosmap[i].addr)
return 0;
- if (res) {
- /* If we want to test the reserved memory include
- * everything except for reserved segments that start
- * at the the top of memory
- */
- if (biosmap[i].type == E820_RESERVED &&
- biosmap[i].addr > 0xff000000) {
- continue;
- }
- biosmap[i].type = E820_RAM;
- } else {
- /* It is always be safe to test ACPI ram */
- if ( biosmap[i].type == E820_ACPI) {
- biosmap[i].type = E820_RAM;
- }
- }
}
/* create pointers for initial change-point information (for sorting) */
@@ -374,7 +343,7 @@
/* move forward only if the new size was non-zero */
if (new_bios[new_bios_entry].size != 0)
if (++new_bios_entry >= E820MAX)
- break; /* no more space left for new bios entries */
+ break; /* no more space left for new bios entries */
}
if (current_type != 0) {
new_bios[new_bios_entry].addr = change_point[chgidx]->addr;
@@ -397,8 +366,8 @@
* must be limited. The max address is found by checking for
* memory wrap from 1MB to 4GB. */
p1 = (ulong)&magic;
- m_lim = 0xfffffffc;
- for (p2 = 0x100000; p2; p2 <<= 1) {
+ m_lim = 0xfffffffc;
+ for (p2 = 0x100000; p2; p2 <<= 1) {
p = (ulong *)(p1 + p2);
if (*p == 0x1234569) {
m_lim = --p2;
@@ -415,7 +384,7 @@
v->pmap[i].start = ((ulong)&_end + (1 << 12) - 1) >> 12;
p = (ulong *)(v->pmap[i].start << 12);
- /* Limit search for memory to m_lim and make sure we don't
+ /* Limit search for memory to m_lim and make sure we don't
* overflow the 32 bit size of p. */
while ((ulong)p < m_lim && (ulong)p >= (ulong)&_end) {
/*
@@ -482,34 +451,34 @@
* We then check that at least one bit changed in each byte before
* believing that it really is memory. */
-static int check_ram(void)
+static int check_ram(void)
{
- int s;
-
- p1 = *p;
+ int s;
- /* write the complement */
- *p = ~p1;
- p2 = *p;
- s = 0;
+ p1 = *p;
- /* Now make sure a bit changed in each byte */
- if ((0xff & p1) != (0xff & p2)) {
- s++;
- }
- if ((0xff00 & p1) != (0xff00 & p2)) {
- s++;
- }
- if ((0xff0000 & p1) != (0xff0000 & p2)) {
- s++;
- }
- if ((0xff000000 & p1) != (0xff000000 & p2)) {
- s++;
- }
- if (s == 4) {
- /* RAM at this address */
- return 1;
- }
+ /* write the complement */
+ *p = ~p1;
+ p2 = *p;
+ s = 0;
+
+ /* Now make sure a bit changed in each byte */
+ if ((0xff & p1) != (0xff & p2)) {
+ s++;
+ }
+ if ((0xff00 & p1) != (0xff00 & p2)) {
+ s++;
+ }
+ if ((0xff0000 & p1) != (0xff0000 & p2)) {
+ s++;
+ }
+ if ((0xff000000 & p1) != (0xff000000 & p2)) {
+ s++;
+ }
+ if (s == 4) {
+ /* RAM at this address */
+ return 1;
+ }
- return 0;
+ return 0;
}
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/memtest.lds
^
|
| @@ -3,7 +3,7 @@
ENTRY(_start);
SECTIONS {
- . = 0x10000;
+ . = 0x5000;
_start = . ;
.data : {
*(.data)
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/memtest_shared.lds
^
|
| @@ -18,6 +18,7 @@
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.hash : { *(.hash) }
+ .gnu.hash : { *(.gnu.hash) }
.dynamic : { *(.dynamic) }
.rel.text : { *(.rel.text .rel.text.*) }
|
|
|
Changed |
memtest86+-4.20.tar.bz2/mt86+_loader
^
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/mt86+_loader.asm
^
|
| @@ -1,4 +1,4 @@
-; A loader for www.Memtest86.com images, by Eric Auer 2003.
+; A loader for www.memtest.org images, by Eric Auer 2003.
; This assumes that the image starts with the boot sector,
; which has the size of setup.S in sectors in a byte at offset
; 1f1h (497). Further, I assume setup.S directly after the boot
@@ -12,8 +12,8 @@
; The good thing is that you get a single file which can be
; compressed, for example with http://upx.sf.net/ (UPX).
-%define fullsize (99256 + buffer - exeh)
- ; 99256 is the size of memtest86+ V1.70, adjust as needed!
+%define fullsize (164504 + buffer - exeh)
+ ; 164504 is the size of memtest86+ V4.20, adjust as needed!
%define stacksize 2048
%define stackpara ((stacksize + 15) / 16)
@@ -46,6 +46,11 @@
; loaded part begins here (set CS so that IP is 100h here)
start: ; entry point ; if you use obj + linker, use "..start:"
+ mov ah, 01h
+ mov bh, 00h
+ mov cx, 2000h
+ int 10h
+
mov ax,cs ; ***
mov ds,ax ; ***
mov es,ax ; ***
@@ -130,7 +135,7 @@
movzx eax,al
shl eax,9 ; log 2 of sector size
add [cs:buflinear],eax ; linear address of head.S now
- mov ax,[buffer+237h] ; should be jmp far dword (ofs, seg)
+ mov ax,[buffer+251h] ; should be jmp far dword (ofs, seg)
cmp ax,0ea66h
jz foundpatch
patchbug: ; could not patch the jump
@@ -143,7 +148,7 @@
foundpatch:
mov eax,[cs:buflinear]
- mov [buffer+239h],eax ; patch the protected mode entry jump
+ mov [buffer+253h],eax ; patch the protected mode entry jump
; (offset only - segment selector unchanged: flat linear CS)
findgdt:
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/patn.c
^
|
| @@ -7,7 +7,7 @@
*
* By Rick van Rein, vanrein@zonnet.nl
* ----------------------------------------------------
- * MemTest86+ V1.60 Specific code (GPL V2.0)
+ * MemTest86+ V2.00 Specific code (GPL V2.0)
* By Samuel DEMEULEMEESTER, sdemeule@memtest.org
* http://www.x86-secret.com - http://www.memtest.org
*/
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/pci.c
^
|
| @@ -3,7 +3,7 @@
* Released under version 2 of the Gnu Public License.
* By Chris Brady
* ----------------------------------------------------
- * MemTest86+ V1.51 Specific code (GPL V2.0)
+ * MemTest86+ V4.00 Specific code (GPL V2.0)
* By Samuel DEMEULEMEESTER, sdemeule@memtest.org
* http://www.x86-secret.com - http://www.memtest.org
*/
@@ -25,17 +25,24 @@
#define PCI_CONF2_ADDRESS(dev, reg) (unsigned short)(0xC000 | (dev << 8) | reg)
+#define PCI_CONF3_ADDRESS(bus, dev, fn, reg) \
+ (0x80000000 | (((reg >> 8) & 0xF) << 24) | (bus << 16) | ((dev & 0x1F) << 11) | (fn << 8) | (reg & 0xFF))
+
int pci_conf_read(unsigned bus, unsigned dev, unsigned fn, unsigned reg, unsigned len, unsigned long *value)
{
int result;
- if (!value || (bus > 255) || (dev > 31) || (fn > 7) || (reg > 255))
+ if (!value || (bus > 255) || (dev > 31) || (fn > 7) || (reg > 255 && pci_conf_type != PCI_CONF_TYPE_1))
return -1;
result = -1;
switch(pci_conf_type) {
case PCI_CONF_TYPE_1:
- outl(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8);
+ if(reg < 256){
+ outl(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8);
+ }else{
+ outl(PCI_CONF3_ADDRESS(bus, dev, fn, reg), 0xCF8);
+ }
switch(len) {
case 1: *value = inb(0xCFC + (reg & 3)); result = 0; break;
case 2: *value = inw(0xCFC + (reg & 2)); result = 0; break;
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/pci.h
^
|
| @@ -7,6 +7,7 @@
unsigned len, unsigned long value);
int pci_init(void);
+
/*
* Under PCI, each device has 256 bytes of configuration address space,
* of which the first 64 bytes are standardized as follows:
|
|
|
Changed |
memtest86+-4.20.tar.bz2/precomp.bin
^
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/serial.h
^
|
| @@ -136,8 +136,8 @@
*/
#include "io.h"
-#define serial_echo_outb(v,a) outb((v),(a)+0x3f8)
-#define serial_echo_inb(a) inb((a)+0x3f8)
+#define serial_echo_outb(v,a) outb((v),(a)+serial_base_ports[serial_tty])
+#define serial_echo_inb(a) inb((a)+serial_base_ports[serial_tty])
#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
/* Wait for transmitter & holding register to empty */
#define WAIT_FOR_XMITR \
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/setup.S
^
|
| @@ -21,6 +21,7 @@
movb $0x80, %al # disable NMI for the bootup sequence
outb %al, $0x70
+
# The system will move itself to its rightful place.
push %cs
@@ -29,6 +30,33 @@
lgdt gdt_48 - start # load gdt with whatever appropriate
# that was painless, now we enable A20
+# start from grub-a20.patch
+ /*
+ * try to switch gateA20 using PORT92, the "Fast A20 and Init"
+ * register
+ */
+ mov $0x92, %dx
+ inb %dx, %al
+ /* skip the port92 code if it's unimplemented (read returns 0xff) */
+ cmpb $0xff, %al
+ jz alt_a20_done
+
+ /* set or clear bit1, the ALT_A20_GATE bit */
+ movb 4(%esp), %ah
+ testb %ah, %ah
+ jz alt_a20_cont1
+ orb $2, %al
+ jmp alt_a20_cont2
+alt_a20_cont1:
+ and $0xfd, %al
+
+ /* clear the INIT_NOW bit; don't accidently reset the machine */
+alt_a20_cont2:
+ and $0xfe, %al
+ outb %al, %dx
+
+alt_a20_done:
+# end from grub-a20.patch
call empty_8042
@@ -67,6 +95,9 @@
empty_8042:
call delay
inb $0x64, %al # 8042 status port
+ cmpb $0xff, %al # from grub-a20-patch, skip if not impl
+ jz empty_8042_ret
+
testb $1, %al # output buffer?
jz no_output
call delay
@@ -76,6 +107,7 @@
no_output:
testb $2, %al # is input buffer full?
jnz empty_8042 # yes - loop
+empty_8042_ret:
ret
#
# Delay is needed after doing i/o
|
|
[-]
[+]
|
Added |
memtest86+-4.20.tar.bz2/smp.c
^
|
| @@ -0,0 +1,440 @@
+/*
+ * smp.c --
+ *
+ * Implements support for SMP machines. For reasons of
+ * simplicity, we do not handle all possible cases allowed by the
+ * MP spec. For example, we expect an explicit MP configuration
+ * table and do not handle default configurations. We also expect
+ * an on-chip local apic and do not support an external 82489DX
+ * apic controller.
+ *
+ */
+
+#include "stddef.h"
+#include "smp.h"
+#include "cpuid.h"
+#include "test.h"
+#define DELAY_FACTOR 1
+extern void memcpy(void *dst, void *src , int len);
+extern void test_start(void);
+
+typedef struct {
+ bool started;
+} ap_info_t;
+
+volatile apic_register_t *APIC = NULL;
+unsigned number_of_cpus = 1; // There is at least one cpu, the BSP
+/* CPU number to APIC ID mapping table. CPU 0 is the BSP. */
+static unsigned cpu_num_to_apic_id[MAX_CPUS];
+volatile ap_info_t AP[MAX_CPUS];
+
+uint8_t
+checksum(uint8_t *data, unsigned len)
+{
+ uint32_t sum = 0;
+ uint8_t *end = data + len;
+ while (data < end) {
+ sum += *data;
+ data++;
+ }
+ return (uint8_t)(sum % 0x100);
+}
+
+
+bool
+read_mp_config_table(uintptr_t addr)
+{
+ mp_config_table_header_t *mpc = (mp_config_table_header_t*)addr;
+ uint8_t *tab_entry_ptr;
+ uint8_t *mpc_table_end;
+ extern unsigned num_hyper_threads_per_core;
+
+ if (mpc->signature != MPCSignature) {
+ return FALSE;
+ }
+ if (checksum((uint8_t*)mpc, mpc->length) != 0) {
+ return FALSE;
+ }
+
+
+ /* FIXME: the uintptr_t cast here works around a compilation problem on
+ * AMD64, but it ignores the real problem, which is that lapic_addr
+ * is only 32 bits. Maybe that's OK, but it should be investigated.
+ */
+ APIC = (volatile apic_register_t*)(uintptr_t)mpc->lapic_addr;
+
+ tab_entry_ptr = ((uint8_t*)mpc) + sizeof(mp_config_table_header_t);
+ mpc_table_end = ((uint8_t*)mpc) + mpc->length;
+ while (tab_entry_ptr < mpc_table_end) {
+ switch (*tab_entry_ptr) {
+ case MP_PROCESSOR: {
+ mp_processor_entry_t *pe = (mp_processor_entry_t*)tab_entry_ptr;
+
+ if (pe->cpu_flag & CPU_BOOTPROCESSOR) {
+ // BSP is CPU 0
+ cpu_num_to_apic_id[0] = pe->apic_id;
+ } else if (number_of_cpus < MAX_CPUS) {
+ cpu_num_to_apic_id[number_of_cpus] = pe->apic_id;
+ number_of_cpus++;
+ }
+ if (num_hyper_threads_per_core > 1 ) {
+ cpu_num_to_apic_id[number_of_cpus] = pe->apic_id | 1;
+ number_of_cpus++;
+ }
+
+ // we cannot handle non-local 82489DX apics
+ if ((pe->apic_ver & 0xf0) != 0x10) {
+ return 0;
+ }
+
+ // we don't know what to do with disabled cpus
+
+ tab_entry_ptr += sizeof(mp_processor_entry_t);
+ break;
+ }
+ case MP_BUS: {
+ tab_entry_ptr += sizeof(mp_bus_entry_t);
+ break;
+ }
+ case MP_IOAPIC: {
+ tab_entry_ptr += sizeof(mp_io_apic_entry_t);
+ break;
+ }
+ case MP_INTSRC:
+ tab_entry_ptr += sizeof(mp_interrupt_entry_t);
+ case MP_LINTSRC:
+ tab_entry_ptr += sizeof(mp_local_interrupt_entry_t);
+ break;
+ default:
+ return FALSE;
+ }
+ }
+ return TRUE;
+}
+
+
+floating_pointer_struct_t *
+scan_for_floating_ptr_struct(uintptr_t addr, uint32_t length)
+{
+ floating_pointer_struct_t *fp;
+ uintptr_t end = addr + length;
+
+
+ fp = (floating_pointer_struct_t*)addr;
+ while ((uintptr_t)fp < end) {
+ if (fp->signature == FPSignature) {
+ if (fp->length == 1 && checksum((uint8_t*)fp, 16) == 0) {
+ return fp;
+ }
+ }
+ fp++;
+ }
+ return NULL;
+}
+
+void PUT_MEM16(uintptr_t addr, uint16_t val)
+{
+ *((volatile uint16_t *)addr) = val;
+}
+
+void PUT_MEM32(uintptr_t addr, uint32_t val)
+{
+ *((volatile uint32_t *)addr) = val;
+}
+
+static void inline
+APIC_WRITE(unsigned reg, uint32_t val)
+{
+ APIC[reg][0] = val;
+}
+
+static inline uint32_t
+APIC_READ(unsigned reg)
+{
+ return APIC[reg][0];
+}
+
+
+static void
+SEND_IPI(unsigned apic_id, unsigned trigger, unsigned level, unsigned mode,
+ uint8_t vector)
+{
+ uint32_t v;
+
+ v = APIC_READ(APICR_ICRHI) & 0x00ffffff;
+ APIC_WRITE(APICR_ICRHI, v | (apic_id << 24));
+
+ v = APIC_READ(APICR_ICRLO) & ~0xcdfff;
+ v |= (APIC_DEST_DEST << APIC_ICRLO_DEST_OFFSET)
+ | (trigger << APIC_ICRLO_TRIGGER_OFFSET)
+ | (level << APIC_ICRLO_LEVEL_OFFSET)
+ | (mode << APIC_ICRLO_DELMODE_OFFSET)
+ | (vector);
+ APIC_WRITE(APICR_ICRLO, v);
+}
+
+
+// Silly way of busywaiting, but we don't have a timer
+void delay(unsigned us)
+{
+ unsigned freq = 1000; // in MHz, assume 1GHz CPU speed
+ uint64_t cycles = us * freq;
+ uint64_t t0 = RDTSC();
+ uint64_t t1;
+ volatile unsigned k;
+
+ do {
+ for (k = 0; k < 1000; k++) continue;
+ t1 = RDTSC();
+ } while (t1 - t0 < cycles);
+}
+
+static inline void
+memset (void *dst,
+ char value,
+ int len)
+{
+ int i;
+ for (i = 0 ; i < len ; i++ ) {
+ *((char *) dst + i) = value;
+ }
+}
+
+void kick_cpu(unsigned cpu_num)
+{
+ unsigned num_sipi, apic_id;
+ apic_id = cpu_num_to_apic_id[cpu_num];
+
+ // clear the APIC ESR register
+ APIC_WRITE(APICR_ESR, 0);
+ APIC_READ(APICR_ESR);
+
+ // asserting the INIT IPI
+ SEND_IPI(apic_id, APIC_TRIGGER_LEVEL, 1, APIC_DELMODE_INIT, 0);
+ delay(100000 / DELAY_FACTOR);
+
+ // de-assert the INIT IPI
+ SEND_IPI(apic_id, APIC_TRIGGER_LEVEL, 0, APIC_DELMODE_INIT, 0);
+
+ for (num_sipi = 0; num_sipi < 2; num_sipi++) {
+ unsigned timeout;
+ bool send_pending;
+ unsigned err;
+
+ APIC_WRITE(APICR_ESR, 0);
+
+ SEND_IPI(apic_id, 0, 0, APIC_DELMODE_STARTUP, (uint32_t)startup_32 >> 12);
+
+ timeout = 0;
+ do {
+ delay(10);
+ timeout++;
+ send_pending = (APIC_READ(APICR_ICRLO) & APIC_ICRLO_STATUS_MASK) != 0;
+ } while (send_pending && timeout < 1000);
+
+ if (send_pending) {
+ //cprint(LINE_STATUS+1, 0, "SMP: STARTUP IPI was never sent");
+ }
+
+ delay(100000 / DELAY_FACTOR);
+
+ err = APIC_READ(APICR_ESR) & 0xef;
+ if (err) {
+ //cprint(LINE_STATUS+1, 0, "SMP: After STARTUP IPI: err = 0x");
+ //hprint(LINE_STATUS+1, COL_MID, err);
+ }
+ }
+}
+
+// These memory locations are used for the trampoline code and data.
+
+#define BOOTCODESTART 0x9000
+#define GDTPOINTERADDR 0x9100
+#define GDTADDR 0x9110
+
+void boot_ap(unsigned cpu_num)
+{
+ unsigned num_sipi, apic_id;
+ extern uint8_t gdt;
+ extern uint8_t _ap_trampoline_start;
+ extern uint8_t _ap_trampoline_protmode;
+ unsigned len = &_ap_trampoline_protmode - &_ap_trampoline_start;
+ apic_id = cpu_num_to_apic_id[cpu_num];
+
+
+ memcpy((uint8_t*)BOOTCODESTART, &_ap_trampoline_start, len);
+
+ // Fixup the LGDT instruction to point to GDT pointer.
+ PUT_MEM16(BOOTCODESTART + 3, GDTPOINTERADDR);
+
+ // Copy a pointer to the temporary GDT to addr GDTPOINTERADDR.
+ // The temporary gdt is at addr GDTADDR
+ PUT_MEM16(GDTPOINTERADDR, 4 * 8);
+ PUT_MEM32(GDTPOINTERADDR + 2, GDTADDR);
+
+ // Copy the first 4 gdt entries from the currently used GDT to the
+ // temporary GDT.
+ memcpy((uint8_t *)GDTADDR, &gdt, 32);
+
+ // clear the APIC ESR register
+ APIC_WRITE(APICR_ESR, 0);
+ APIC_READ(APICR_ESR);
+
+ // asserting the INIT IPI
+ SEND_IPI(apic_id, APIC_TRIGGER_LEVEL, 1, APIC_DELMODE_INIT, 0);
+ delay(100000 / DELAY_FACTOR);
+
+ // de-assert the INIT IPI
+ SEND_IPI(apic_id, APIC_TRIGGER_LEVEL, 0, APIC_DELMODE_INIT, 0);
+
+ for (num_sipi = 0; num_sipi < 2; num_sipi++) {
+ unsigned timeout;
+ bool send_pending;
+ unsigned err;
+
+ APIC_WRITE(APICR_ESR, 0);
+
+ SEND_IPI(apic_id, 0, 0, APIC_DELMODE_STARTUP, BOOTCODESTART >> 12);
+
+ timeout = 0;
+ do {
+ delay(10);
+ timeout++;
+ send_pending = (APIC_READ(APICR_ICRLO) & APIC_ICRLO_STATUS_MASK) != 0;
+ } while (send_pending && timeout < 1000);
+
+ if (send_pending) {
+ //cprint(LINE_STATUS+1, 0, "SMP: STARTUP IPI was never sent");
+ }
+
+ delay(100000 / DELAY_FACTOR);
+
+ err = APIC_READ(APICR_ESR) & 0xef;
+ if (err) {
+ //cprint(LINE_STATUS+1, 0, "SMP: After STARTUP IPI: err = 0x");
+ // hprint(LINE_STATUS+1, COL_MID, err);
+ }
+ }
+}
+
+void
+smp_init_bsp()
+{
+ floating_pointer_struct_t *fp;
+ /* gets the details about the cpu, the type, the brand
+ * whether it is a multi-core package etc.
+ */
+ cpuid_init();
+
+ memset(&AP, 0, sizeof AP);
+
+ fp = scan_for_floating_ptr_struct(0x0, 0x400);
+ if (fp == NULL) {
+ fp = scan_for_floating_ptr_struct(639*0x400, 0x400);
+ }
+ if (fp == NULL) {
+ fp = scan_for_floating_ptr_struct(0xf0000, 0x10000);
+ }
+ if (fp == NULL) {
+ /*
+ * If it is an SMP machine we should know now, unless the
+ * configuration is in an EISA/MCA bus machine with an
+ * extended bios data area.
+ *
+ * there is a real-mode segmented pointer pointing to the
+ * 4K EBDA area at 0x40E, calculate and scan it here.
+ */
+ unsigned int address = *(unsigned short *)0x40E;
+ address <<= 4;
+ if (address) {
+ fp = scan_for_floating_ptr_struct(address, 0x400);
+ }
+ }
+
+ if (fp != NULL && fp->phys_addr != 0) {
+ if (!read_mp_config_table(fp->phys_addr)) {
+ //cprint(LINE_STATUS+1,0, "SMP: Error while parsing MP config table");
+ }
+ }
+/*
+ if (fp == NULL) {
+ cprint(LINE_STATUS+1,0,"SMP: No floating pointer structure found");
+ }
+*/
+}
+
+void
+smp_init_aps()
+{
+ int cpuNum;
+ for(cpuNum = 0 ; cpuNum < MAX_CPUS ; cpuNum++) {
+ AP[cpuNum].started = FALSE;
+ }
+}
+
+unsigned
+my_apic_id()
+{
+ return (APIC[APICR_ID][0]) >> 24;
+}
+
+void
+smp_ap_booted(unsigned cpu_num)
+{
+ AP[cpu_num].started = TRUE;
+}
+
+void
+smp_boot_ap(unsigned cpu_num)
+{
+ unsigned timeout;
+ extern bool smp_mode;
+ boot_ap(cpu_num);
+ timeout = 0;
+ do {
+ delay(1000 / DELAY_FACTOR);
+ timeout++;
+ } while (!AP[cpu_num].started && timeout < 100000 / DELAY_FACTOR);
+
+ if (!AP[cpu_num].started) {
+ //cprint(LINE_STATUS+1, 0, "SMP: Boot timeout for");
+ //dprint(LINE_STATUS+1, COL_MID, cpu_num,2,1);
+ //cprint(LINE_STATUS+1, 26, "Turning off SMP");
+ smp_mode = FALSE;
+ }
+}
+
+unsigned
+smp_num_cpus()
+{
+ return number_of_cpus;
+}
+
+unsigned
+smp_my_cpu_num()
+{
+ unsigned apicid = my_apic_id();
+ unsigned i;
+
+ for (i = 0; i < MAX_CPUS; i++) {
+ if (apicid == cpu_num_to_apic_id[i]) {
+ break;
+ }
+ }
+ if (i == MAX_CPUS) {
+ i = 0;
+ }
+ return i;
+}
+
+volatile spinlock_t barr_lk={1};
+void barrier(volatile int *barr, int n)
+{
+ spin_lock(&barr_lk);
+ barr++;
+ spin_unlock(&barr_lk);
+ while((uint32_t)barr<n);
+ barr = 0;
+ return;
+}
+
|
|
[-]
[+]
|
Added |
memtest86+-4.20.tar.bz2/smp.h
^
|
| @@ -0,0 +1,265 @@
+/* **********************************************************
+ * Copyright 2002 VMware, Inc. All rights reserved. -- VMware Confidential
+ * **********************************************************/
+
+
+#ifndef _SMP_H_
+#define _SMP_H_
+#include "stdint.h"
+#include "defs.h"
+#define MAX_CPUS 16 // "16 CPUs ought to be enough for everybody."
+
+
+#define FPSignature ('_' | 'M' << 8 | 'P' << 16 | '_' << 24)
+
+typedef struct {
+ uint32_t signature; // "_MP_"
+ uint32_t phys_addr;
+ uint8_t length;
+ uint8_t spec_rev;
+ uint8_t checksum;
+ uint8_t feature[5];
+} floating_pointer_struct_t;
+
+#define MPCSignature ('P' | 'C' << 8 | 'M' << 16 | 'P' << 24)
+typedef struct {
+ uint32_t signature; // "PCMP"
+ uint16_t length;
+ uint8_t spec_rev;
+ uint8_t checksum;
+ char oem[8];
+ char productid[12];
+ uint32_t oem_ptr;
+ uint16_t oem_size;
+ uint16_t oem_count;
+ uint32_t lapic_addr;
+ uint32_t reserved;
+} mp_config_table_header_t;
+
+/* Followed by entries */
+
+#define MP_PROCESSOR 0
+#define MP_BUS 1
+#define MP_IOAPIC 2
+#define MP_INTSRC 3
+#define MP_LINTSRC 4
+
+typedef struct {
+ uint8_t type; /* MP_PROCESSOR */
+ uint8_t apic_id; /* Local APIC number */
+ uint8_t apic_ver; /* Its versions */
+ uint8_t cpu_flag;
+#define CPU_ENABLED 1 /* Processor is available */
+#define CPU_BOOTPROCESSOR 2 /* Processor is the BP */
+ uint32_t cpu_signature;
+#define CPU_STEPPING_MASK 0x0F
+#define CPU_MODEL_MASK 0xF0
+#define CPU_FAMILY_MASK 0xF00
+ uint32_t featureflag; /* CPUID feature value */
+ uint32_t reserved[2];
+} mp_processor_entry_t;
+
+
+typedef struct {
+ uint8_t type; // has value MP_BUS
+ uint8_t busid;
+ char bustype[6];
+} mp_bus_entry_t;
+
+#define BUSTYPE_EISA "EISA"
+#define BUSTYPE_ISA "ISA"
+#define BUSTYPE_INTERN "INTERN"
+#define BUSTYPE_MCA "MCA"
+#define BUSTYPE_VL "VL"
+#define BUSTYPE_PCI "PCI"
+#define BUSTYPE_PCMCIA "PCMCIA"
+
+/* We don't understand the others */
+
+typedef struct {
+ uint8_t type; // set to MP_IOAPIC
+ uint8_t apicid;
+ uint8_t apicver;
+ uint8_t flags;
+#define MPC_APIC_USABLE 0x01
+ uint32_t apicaddr;
+} mp_io_apic_entry_t;
+
+
+typedef struct {
+ uint8_t type;
+ uint8_t irqtype;
+ uint16_t irqflag;
+ uint8_t srcbus;
+ uint8_t srcbusirq;
+ uint8_t dstapic;
+ uint8_t dstirq;
+} mp_interrupt_entry_t;
+
+#define MP_INT_VECTORED 0
+#define MP_INT_NMI 1
+#define MP_INT_SMI 2
+#define MP_INT_EXTINT 3
+
+#define MP_IRQDIR_DEFAULT 0
+#define MP_IRQDIR_HIGH 1
+#define MP_IRQDIR_LOW 3
+
+
+typedef struct {
+ uint8_t type;
+ uint8_t irqtype;
+ uint16_t irqflag;
+ uint8_t srcbusid;
+ uint8_t srcbusirq;
+ uint8_t destapic;
+#define MP_APIC_ALL 0xFF
+ uint8_t destapiclint;
+} mp_local_interrupt_entry_t;
+
+/* APIC definitions */
+/*
+ * APIC registers
+ */
+#define APICR_ID 0x02
+#define APICR_ESR 0x28
+#define APICR_ICRLO 0x30
+#define APICR_ICRHI 0x31
+
+/* APIC destination shorthands */
+#define APIC_DEST_DEST 0
+#define APIC_DEST_LOCAL 1
+#define APIC_DEST_ALL_INC 2
+#define APIC_DEST_ALL_EXC 3
+
+/* APIC IPI Command Register format */
+#define APIC_ICRHI_RESERVED 0x00ffffff
+#define APIC_ICRHI_DEST_MASK 0xff000000
+#define APIC_ICRHI_DEST_OFFSET 24
+
+#define APIC_ICRLO_RESERVED 0xfff32000
+#define APIC_ICRLO_DEST_MASK 0x000c0000
+#define APIC_ICRLO_DEST_OFFSET 18
+#define APIC_ICRLO_TRIGGER_MASK 0x00008000
+#define APIC_ICRLO_TRIGGER_OFFSET 15
+#define APIC_ICRLO_LEVEL_MASK 0x00004000
+#define APIC_ICRLO_LEVEL_OFFSET 14
+#define APIC_ICRLO_STATUS_MASK 0x00001000
+#define APIC_ICRLO_STATUS_OFFSET 12
+#define APIC_ICRLO_DESTMODE_MASK 0x00000800
+#define APIC_ICRLO_DESTMODE_OFFSET 11
+#define APIC_ICRLO_DELMODE_MASK 0x00000700
+#define APIC_ICRLO_DELMODE_OFFSET 8
+#define APIC_ICRLO_VECTOR_MASK 0x000000ff
+#define APIC_ICRLO_VECTOR_OFFSET 0
+
+/* APIC trigger types (edge/level) */
+#define APIC_TRIGGER_EDGE 0
+#define APIC_TRIGGER_LEVEL 1
+
+/* APIC delivery modes */
+#define APIC_DELMODE_FIXED 0
+#define APIC_DELMODE_LOWEST 1
+#define APIC_DELMODE_SMI 2
+#define APIC_DELMODE_NMI 4
+#define APIC_DELMODE_INIT 5
+#define APIC_DELMODE_STARTUP 6
+#define APIC_DELMODE_EXTINT 7
+typedef uint32_t apic_register_t[4];
+
+extern volatile apic_register_t *APIC;
+
+unsigned smp_num_cpus();
+unsigned smp_my_cpu_num();
+
+void smp_init_bsp(void);
+void smp_init_aps(void);
+
+void smp_boot_ap(unsigned cpu_num);
+void smp_ap_booted(unsigned cpu_num);
+
+static inline void
+__GET_CPUID(int ax, uint32_t *regs)
+{
+ __asm__ __volatile__("\t"
+ /* save ebx in case -fPIC is being used */
+ "push %%ebx; cpuid; mov %%ebx, %%edi; pop %%ebx"
+ : "=a" (regs[0]), "=D" (regs[1]), "=c" (regs[2]), "=d" (regs[3])
+ : "a" (ax)
+ : "memory"
+ );
+}
+
+#define GET_CPUID(_ax,_bx,_cx,_dx) { \
+ uint32_t regs[4]; \
+ __GET_CPUID(_ax,regs); \
+ _ax = regs[0]; \
+ _bx = regs[1]; \
+ _cx = regs[2]; \
+ _dx = regs[3]; \
+}
+
+/*
+ * Checked against the Intel manual and GCC --hpreg
+ *
+ * volatile because the tsc always changes without the compiler knowing it.
+ */
+static inline uint64_t
+RDTSC(void)
+{
+ uint64_t tim;
+
+ __asm__ __volatile__(
+ "rdtsc"
+ : "=A" (tim)
+ );
+
+ return tim;
+}
+
+static inline uint64_t __GET_MSR(int cx)
+{
+ uint64_t msr;
+
+ __asm__ __volatile__(
+ "rdmsr"
+ : "=A" (msr)
+ : "c" (cx)
+ );
+
+ return msr;
+}
+
+#define __GCC_OUT(s, s2, port, val) do { \
+ __asm__( \
+ "out" #s " %" #s2 "1, %w0" \
+ : \
+ : "Nd" (port), "a" (val) \
+ ); \
+} while (0)
+#define OUTB(port, val) __GCC_OUT(b, b, port, val)
+
+typedef struct {
+ unsigned int slock;
+} spinlock_t;
+
+static inline void spin_lock(volatile spinlock_t *lock)
+{
+ asm volatile("\n1:\t"
+ " ; lock;decb %0\n\t"
+ "jns 3f\n"
+ "2:\t"
+ "rep;nop\n\t"
+ "cmpb $0,%0\n\t"
+ "jle 2b\n\t"
+ "jmp 1b\n"
+ "3:\n\t"
+ : "+m" (lock->slock) : : "memory");
+}
+static inline void spin_unlock(volatile spinlock_t *lock)
+{
+ asm volatile("movb $1,%0" : "+m" (lock->slock) :: "memory");
+}
+
+
+#endif /* _SMP_H_ */
|
|
[-]
[+]
|
Added |
memtest86+-4.20.tar.bz2/spd.c
^
|
| @@ -0,0 +1,475 @@
+/* Memtest86 SPD extension
+ * added by Reto Sonderegger, 2004, reto@swissbit.com
+ *
+ * Released under version 2 of the Gnu Puclic License
+ * ----------------------------------------------------
+ * MemTest86+ V4.20 Specific code (GPL V2.0)
+ * By Samuel DEMEULEMEESTER, sdemeule@memtest.org
+ * http://www.canardpc.com - http://www.memtest.org
+ */
+
+
+#include "test.h"
+#include "io.h"
+#include "pci.h"
+#include "msr.h"
+#include "spd.h"
+#include "screen_buffer.h"
+#include "jedec_id.h"
+
+#define NULL 0
+
+#define SMBHSTSTS smbusbase
+#define SMBHSTCNT smbusbase + 2
+#define SMBHSTCMD smbusbase + 3
+#define SMBHSTADD smbusbase + 4
+#define SMBHSTDAT smbusbase + 5
+
+extern void wait_keyup();
+
+int smbdev, smbfun;
+unsigned short smbusbase;
+unsigned char spd[256];
+char s[] = {'/', 0, '-', 0, '\\', 0, '|', 0};
+
+static void ich5_get_smb(void)
+{
+ unsigned long x;
+ int result;
+ result = pci_conf_read(0, smbdev, smbfun, 0x20, 2, &x);
+ if (result == 0) smbusbase = (unsigned short) x & 0xFFFE;
+}
+
+unsigned char ich5_smb_read_byte(unsigned char adr, unsigned char cmd)
+{
+ int l1, h1, l2, h2;
+ unsigned long long t;
+ __outb(0x1f, SMBHSTSTS); // reset SMBus Controller
+ __outb(0xff, SMBHSTDAT);
+ while(__inb(SMBHSTSTS) & 0x01); // wait until ready
+ __outb(cmd, SMBHSTCMD);
+ __outb((adr << 1) | 0x01, SMBHSTADD);
+ __outb(0x48, SMBHSTCNT);
+ rdtsc(l1, h1);
+ //cprint(POP2_Y, POP2_X + 16, s + cmd % 8); // progress bar
+ while (!(__inb(SMBHSTSTS) & 0x02)) { // wait til command finished
+ rdtsc(l2, h2);
+ t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / v->clks_msec;
+ if (t > 10) break; // break after 10ms
+ }
+ return __inb(SMBHSTDAT);
+}
+
+static int ich5_read_spd(int dimmadr)
+{
+ int x;
+ spd[0] = ich5_smb_read_byte(0x50 + dimmadr, 0);
+ if (spd[0] == 0xff) return -1; // no spd here
+ for (x = 1; x < 256; x++) {
+ spd[x] = ich5_smb_read_byte(0x50 + dimmadr, (unsigned char) x);
+ }
+ return 0;
+}
+
+static void us15w_get_smb(void)
+{
+ unsigned long x;
+ int result;
+ result = pci_conf_read(0, 0x1f, 0, 0x40, 2, &x);
+ if (result == 0) smbusbase = (unsigned short) x & 0xFFC0;
+}
+
+unsigned char us15w_smb_read_byte(unsigned char adr, unsigned char cmd)
+{
+ int l1, h1, l2, h2;
+ unsigned long long t;
+ //__outb(0x00, smbusbase + 1); // reset SMBus Controller
+ //__outb(0x00, smbusbase + 6);
+ //while((__inb(smbusbase + 1) & 0x08) != 0); // wait until ready
+ __outb(0x02, smbusbase + 0); // Byte read
+ __outb(cmd, smbusbase + 5); // Command
+ __outb(0x07, smbusbase + 1); // Clear status
+ __outb((adr << 1) | 0x01, smbusbase + 4); // DIMM address
+ __outb(0x12, smbusbase + 0); // Start
+ //while (((__inb(smbusbase + 1) & 0x08) == 0)) {} // wait til busy
+ rdtsc(l1, h1);
+ cprint(POP2_Y, POP2_X + 16, s + cmd % 8); // progress bar
+ while (((__inb(smbusbase + 1) & 0x01) == 0) ||
+ ((__inb(smbusbase + 1) & 0x08) != 0)) { // wait til command finished
+ rdtsc(l2, h2);
+ t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / v->clks_msec;
+ if (t > 10) break; // break after 10ms
+ }
+ return __inb(smbusbase + 6);
+}
+
+static int us15w_read_spd(int dimmadr)
+{
+ int x;
+ spd[0] = us15w_smb_read_byte(0x50 + dimmadr, 0);
+ if (spd[0] == 0xff) return -1; // no spd here
+ for (x = 1; x < 256; x++) {
+ spd[x] = us15w_smb_read_byte(0x50 + dimmadr, (unsigned char) x);
+ }
+ return 0;
+}
+
+struct pci_smbus_controller {
+ unsigned vendor;
+ unsigned device;
+ char *name;
+ void (*get_adr)(void);
+ int (*read_spd)(int dimmadr);
+};
+
+static struct pci_smbus_controller smbcontrollers[] = {
+{0x8086, 0x1C22, "Intel P67", ich5_get_smb, ich5_read_spd},
+{0x8086, 0x3B30, "Intel P55", ich5_get_smb, ich5_read_spd},
+{0x8086, 0x3A60, "Intel ICH10B", ich5_get_smb, ich5_read_spd},
+{0x8086, 0x3A30, "Intel ICH10R", ich5_get_smb, ich5_read_spd},
+{0x8086, 0x2930, "Intel ICH9", ich5_get_smb, ich5_read_spd},
+{0x8086, 0x283E, "Intel ICH8", ich5_get_smb, ich5_read_spd},
+{0x8086, 0x27DA, "Intel ICH7", ich5_get_smb, ich5_read_spd},
+{0x8086, 0x266A, "Intel ICH6", ich5_get_smb, ich5_read_spd},
+{0x8086, 0x24D3, "Intel ICH5", ich5_get_smb, ich5_read_spd},
+{0x8086, 0x24C3, "Intel ICH4", ich5_get_smb, ich5_read_spd},
+{0x8086, 0x25A4, "Intel 6300ESB", ich5_get_smb, ich5_read_spd},
+{0x8086, 0x269B, "Intel ESB2", ich5_get_smb, ich5_read_spd},
+{0x8086, 0x8119, "Intel US15W", us15w_get_smb, us15w_read_spd},
+{0x8086, 0x5032, "Intel EP80579", ich5_get_smb, ich5_read_spd},
+{0, 0, "", NULL, NULL}
+};
+
+
+int find_smb_controller(void)
+{
+ int i = 0;
+ unsigned long valuev, valued;
+ for (smbdev = 0; smbdev < 32; smbdev++) {
+ for (smbfun = 0; smbfun < 8; smbfun++) {
+ pci_conf_read(0, smbdev, smbfun, 0, 2, &valuev);
+ if (valuev != 0xFFFF) { // if there is something look what's it..
+ for (i = 0; smbcontrollers[i].vendor > 0; i++) { // check if this is a known smbus controller
+ if (valuev == smbcontrollers[i].vendor) {
+ pci_conf_read(0, smbdev, smbfun, 2, 2, &valued); // read the device id
+ if (valued == smbcontrollers[i].device) {
+ return i;
+ }
+ }
+ }
+ }
+ }
+ }
+ return -1;
+}
+
+
+
+void get_spd_spec(void)
+{
+ int index;
+ int h, i, j, z;
+ int k = 0;
+ int module_size;
+ int curcol;
+ int temp_nbd;
+
+ index = find_smb_controller();
+
+ if (index == -1)
+ {
+ // Unknown SMBUS Controller, exit
+ return;
+ }
+
+ smbcontrollers[index].get_adr();
+ cprint(LINE_SPD-2, 0, "Memory SPD Informations");
+ cprint(LINE_SPD-1, 0, "-----------------------------------");
+
+ for (j = 0; j < 8; j++) {
+ if (smbcontrollers[index].read_spd(j) == 0) {
+ curcol = 1;
+ if(spd[2] == 0x0b){
+ // We are here if DDR3 present
+
+ // First print slot#, module capacity
+ cprint(LINE_SPD+k, curcol, " - Slot :");
+ dprint(LINE_SPD+k, curcol+8, k, 1, 0);
+
+ module_size = get_ddr3_module_size(spd[4] & 0xF, spd[8] & 0x7, spd[7] & 0x7, spd[7] >> 3);
+ temp_nbd = getnum(module_size); curcol += 12;
+ dprint(LINE_SPD+k, curcol, module_size, temp_nbd, 0); curcol += temp_nbd;
+ cprint(LINE_SPD+k, curcol, " MB"); curcol += 4;
+
+ // Then module jedec speed
+ switch(spd[12])
+ {
+ default:
+ case 20:
+ cprint(LINE_SPD+k, curcol, "PC3-6400");
+ curcol += 8;
+ break;
+ case 15:
+ cprint(LINE_SPD+k, curcol, "PC3-8500");
+ curcol += 8;
+ break;
+ case 12:
+ cprint(LINE_SPD+k, curcol, "PC3-10600");
+ curcol += 9;
+ break;
+ case 10:
+ cprint(LINE_SPD+k, curcol, "PC3-12800");
+ curcol += 9;
+ break;
+ case 8:
+ cprint(LINE_SPD+k, curcol, "PC3-15000");
+ curcol += 9;
+ break;
+ case 6:
+ cprint(LINE_SPD+k, curcol, "PC3-16000");
+ curcol += 9;
+ break;
+ }
+
+ curcol++;
+
+ // Then print module infos (manufacturer & part number)
+ spd[117] &= 0x0F; // Parity odd or even
+ for (i = 0; jep106[i].cont_code < 9; i++) {
+ if (spd[117] == jep106[i].cont_code && spd[118] == jep106[i].hex_byte) {
+ // We are here if a Jedec manufacturer is detected
+ cprint(LINE_SPD+k, curcol, "-"); curcol += 2;
+ cprint(LINE_SPD+k, curcol, jep106[i].name);
+ for(z = 0; jep106[i].name[z] != '\0'; z++) { curcol++; }
+ curcol++;
+ // Display module serial number
+ for (h = 128; h < 146; h++) {
+ cprint(16+k, curcol, convert_hex_to_char(spd[h]));
+ curcol++;
+ }
+
+ // Detect XMP Memory
+ if(spd[176] == 0x0C && spd[177] == 0x4A)
+ {
+ cprint(LINE_SPD+k, curcol, "*XMP*");
+ }
+ }
+ }
+ }
+ // We enter this function if DDR2 is detected
+ if(spd[2] == 0x08){
+ // First print slot#, module capacity
+ cprint(LINE_SPD+k, curcol, " - Slot :");
+ dprint(LINE_SPD+k, curcol+8, k, 1, 0);
+
+ module_size = get_ddr2_module_size(spd[31], spd[5]);
+ temp_nbd = getnum(module_size); curcol += 12;
+ dprint(LINE_SPD+k, curcol, module_size, temp_nbd, 0); curcol += temp_nbd;
+ cprint(LINE_SPD+k, curcol, " MB"); curcol += 4;
+
+ // Then module jedec speed
+ float ddr2_speed, byte1, byte2;
+
+ byte1 = (spd[9] >> 4) * 10;
+ byte2 = spd[9] & 0xF;
+
+ ddr2_speed = 1 / (byte1 + byte2) * 10000;
+
+ temp_nbd = getnum(ddr2_speed);
+ cprint(LINE_SPD+k, curcol, "DDR2-"); curcol += 5;
+ dprint(LINE_SPD+k, curcol, ddr2_speed, temp_nbd, 0); curcol += temp_nbd;
+
+ // Then print module infos (manufacturer & part number)
+ int ccode = 0;
+
+ for(i = 64; i < 72; i++)
+ {
+ if(spd[i] == 0x7F) { ccode++; }
+ }
+
+ curcol++;
+
+ for (i = 0; jep106[i].cont_code < 9; i++) {
+ if (ccode == jep106[i].cont_code && spd[64+ccode] == jep106[i].hex_byte) {
+ // We are here if a Jedec manufacturer is detected
+ cprint(LINE_SPD+k, curcol, "-"); curcol += 2;
+ cprint(LINE_SPD+k, curcol, jep106[i].name);
+ for(z = 0; jep106[i].name[z] != '\0'; z++) { curcol++; }
+ curcol++;
+ // Display module serial number
+ for (h = 73; h < 91; h++) {
+ cprint(16+k, curcol, convert_hex_to_char(spd[h]));
+ curcol++;
+ }
+
+ }
+ }
+
+ }
+ k++;
+ }
+ }
+}
+
+
+void show_spd(void)
+{
+ int index;
+ int i, j;
+ int flag = 0;
+ pop2up();
+ wait_keyup();
+ index = find_smb_controller();
+ if (index == -1) {
+ cprint(POP2_Y, POP2_X+1, "SMBus Controller not known");
+ while (!get_key());
+ wait_keyup();
+ pop2down();
+ return;
+ }
+ else cprint(POP2_Y, POP2_X+1, "SPD Data: Slot");
+ smbcontrollers[index].get_adr();
+ for (j = 0; j < 16; j++) {
+ if (smbcontrollers[index].read_spd(j) == 0) {
+ dprint(POP2_Y, POP2_X + 15, j, 2, 0);
+ for (i = 0; i < 256; i++) {
+ hprint2(2 + POP2_Y + i / 16, 3 + POP2_X + (i % 16) * 3, spd[i], 2);
+ }
+ flag = 0;
+ while(!flag) {
+ if (get_key()) flag++;
+ }
+ wait_keyup();
+ }
+ }
+ pop2down();
+}
+
+int get_ddr3_module_size(int sdram_capacity, int prim_bus_width, int sdram_width, int ranks)
+{
+ int module_size;
+
+ switch(sdram_capacity)
+ {
+ case 0:
+ module_size = 256;
+ break;
+ case 1:
+ module_size = 512;
+ break;
+ default:
+ case 2:
+ module_size = 1024;
+ break;
+ case 3:
+ module_size = 2048;
+ break;
+ case 4:
+ module_size = 4096;
+ break;
+ case 5:
+ module_size = 8192;
+ break;
+ case 6:
+ module_size = 16384;
+ break;
+ }
+
+ module_size /= 8;
+
+ switch(prim_bus_width)
+ {
+ case 0:
+ module_size *= 8;
+ break;
+ case 1:
+ module_size *= 16;
+ break;
+ case 2:
+ module_size *= 32;
+ break;
+ case 3:
+ module_size *= 64;
+ break;
+ }
+
+ switch(sdram_width)
+ {
+ case 0:
+ module_size /= 4;
+ break;
+ case 1:
+ module_size /= 8;
+ break;
+ case 2:
+ module_size /= 16;
+ break;
+ case 3:
+ module_size /= 32;
+ break;
+
+ }
+
+ module_size *= (ranks + 1);
+
+ return module_size;
+}
+
+
+int get_ddr2_module_size(int rank_density_byte, int rank_num_byte)
+{
+ int module_size;
+
+ switch(rank_density_byte)
+ {
+ case 1:
+ module_size = 1024;
+ break;
+ case 2:
+ module_size = 2048;
+ break;
+ case 4:
+ module_size = 4096;
+ break;
+ case 8:
+ module_size = 8192;
+ break;
+ case 16:
+ module_size = 16384;
+ break;
+ case 32:
+ module_size = 128;
+ break;
+ case 64:
+ module_size = 256;
+ break;
+ default:
+ case 128:
+ module_size = 512;
+ break;
+ }
+
+ module_size *= (rank_num_byte & 7) + 1;
+
+ return module_size;
+
+}
+
+
+struct ascii_map {
+ unsigned hex_code;
+ char *name;
+};
+
+
+char* convert_hex_to_char(unsigned hex_org) {
+ static char buf[2] = " ";
+ if (hex_org >= 0x20 && hex_org < 0x80) {
+ buf[0] = hex_org;
+ } else {
+ //buf[0] = '\0';
+ buf[0] = ' ';
+ }
+
+ return buf;
+}
\ No newline at end of file
|
|
[-]
[+]
|
Added |
memtest86+-4.20.tar.bz2/spd.h
^
|
| @@ -0,0 +1,13 @@
+/*
+ * MemTest86+ V3.00 Specific code (GPL V2.0)
+ * By Samuel DEMEULEMEESTER, sdemeule@memtest.org
+ * http://www.canardpc.com - http://www.memtest.org
+ */
+
+void get_spd_spec(void);
+int get_ddr2_module_size(int rank_density_byte, int rank_num_byte);
+int get_ddr3_module_size(int sdram_capacity, int prim_bus_width, int sdram_width, int ranks);
+char* convert_hex_to_char(unsigned hex_org);
+#define LINE_SPD 16
+
+
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/stdint.h
^
|
| @@ -48,5 +48,13 @@
typedef long long int intmax_t;
typedef unsigned long long uintmax_t;
+typedef char bool;
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#ifndef TRUE
+#define TRUE 1
+#endif
#endif /* I386_STDINT_H */
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/test.c
^
|
| @@ -4,29 +4,28 @@
* Released under version 2 of the Gnu Public License.
* By Chris Brady, cbrady@sgi.com
* ----------------------------------------------------
- * MemTest86+ V1.70 Specific code (GPL V2.0)
+ * MemTest86+ V3.00 Specific code (GPL V2.0)
* By Samuel DEMEULEMEESTER, sdemeule@memtest.org
- * http://www.x86-secret.com - http://www.memtest.org
+ * http://www.canardpc.com - http://www.memtest.org
*/
#include "test.h"
#include "config.h"
#include <sys/io.h>
#include "dmi.h"
+#include <inttypes.h>
-
-extern int segs, bail, beepmode;
+extern int segs, bail;
extern volatile ulong *p;
extern ulong p1, p2;
extern int test_ticks, nticks;
extern struct tseq tseq[];
+extern void update_err_counts(void);
+extern void print_err_counts(void);
void poll_errors();
int ecount = 0;
-static void update_err_counts(void);
-static void print_err_counts(void);
-
static inline ulong roundup(ulong value, ulong mask)
{
return (value + mask) & ~mask;
@@ -52,19 +51,19 @@
/* Now write pattern compliment */
p1 = ~p1;
end = v->map[segs-1].end;
- for (i=0; i<1000; i++) {
+ for (i=0; i<100; i++) {
mask = 4;
do {
pt = (ulong *)((ulong)p | mask);
- if (pt == p) {
+ if ((uintptr_t)pt == (uintptr_t)p) {
mask = mask << 1;
continue;
}
- if (pt >= end) {
+ if ((uintptr_t)pt >= (uintptr_t)end) {
break;
}
*pt = p1;
- if ((bad = *p) != ~p1) {
+ if ((uintptr_t)(bad = *p) != (uintptr_t)~p1) {
ad_err1((ulong *)p, (ulong *)mask,
bad, ~p1);
i = 1000;
@@ -92,7 +91,7 @@
/* Force start address to be a multiple of 256k */
p = (ulong *)roundup((ulong)p, bank - 1);
end = v->map[j].end;
- while (p < end) {
+ while ((uintptr_t)p < (uintptr_t)end) {
*p = p1;
p1 = ~p1;
@@ -101,15 +100,15 @@
do {
pt = (ulong *)
((ulong)p | mask);
- if (pt == p) {
+ if ((uintptr_t)pt == (uintptr_t)p) {
mask = mask << 1;
continue;
}
- if (pt >= end) {
+ if ((uintptr_t)pt >= (uintptr_t)end) {
break;
}
*pt = p1;
- if ((bad = *p) != ~p1) {
+ if ((uintptr_t)(bad = *p) != (uintptr_t)~p1) {
ad_err1((ulong *)p,
(ulong *)mask,
bad,~p1);
@@ -118,7 +117,7 @@
mask = mask << 1;
} while(mask);
}
- if (p + bank/4 > p) {
+ if ((uintptr_t)(p + bank/4) > (uintptr_t)p) {
p += bank/4;
} else {
p = end;
@@ -152,16 +151,16 @@
done = 0;
do {
/* Check for overflow */
- if (pe + SPINSZ > pe) {
+ if ((uintptr_t)(pe + SPINSZ) > (uintptr_t)pe) {
pe += SPINSZ;
} else {
pe = end;
}
- if (pe >= end) {
+ if ((uintptr_t)pe >= (uintptr_t)end) {
pe = end;
done++;
}
- if (p == pe ) {
+ if ((uintptr_t)p == (uintptr_t)pe) {
break;
}
@@ -196,16 +195,16 @@
done = 0;
do {
/* Check for overflow */
- if (pe + SPINSZ > pe) {
+ if ((uintptr_t)(pe + SPINSZ) > (uintptr_t)pe) {
pe += SPINSZ;
} else {
pe = end;
}
- if (pe >= end) {
+ if ((uintptr_t)pe >= (uintptr_t)end) {
pe = end;
done++;
}
- if (p == pe ) {
+ if ((uintptr_t)p == (uintptr_t)pe ) {
break;
}
/* Original C code replaced with hand tuned assembly code
@@ -262,6 +261,7 @@
volatile ulong *pe;
volatile ulong *start,*end;
ulong num;
+ uintptr_t seg_start;
/* Initialize memory with initial sequence of random numbers. */
if (v->rdtsc) {
@@ -279,19 +279,20 @@
end = v->map[j].end;
pe = start;
p = start;
+ seg_start = (uintptr_t)p;
done = 0;
do {
/* Check for overflow */
- if (pe + SPINSZ > pe) {
+ if ((uintptr_t)(pe + SPINSZ) > (uintptr_t)pe) {
pe += SPINSZ;
} else {
pe = end;
}
- if (pe >= end) {
+ if ((uintptr_t)pe >= (uintptr_t)end) {
pe = end;
done++;
}
- if (p == pe ) {
+ if (seg_start == (uintptr_t)pe) {
break;
}
/* Original C code replaced with hand tuned assembly code */
@@ -312,7 +313,7 @@
"jb L200\n\t"
: "=D" (p)
: "D" (p), "b" (pe)
- : "eax"
+ : "eax", "edx"
);
do_tick();
@@ -330,19 +331,20 @@
end = v->map[j].end;
pe = start;
p = start;
+ seg_start = (uintptr_t)p;
done = 0;
do {
/* Check for overflow */
- if (pe + SPINSZ > pe) {
+ if ((uintptr_t)(pe + SPINSZ) > (uintptr_t)pe) {
pe += SPINSZ;
} else {
pe = end;
}
- if (pe >= end) {
+ if ((uintptr_t)pe >= (uintptr_t)end) {
pe = end;
done++;
}
- if (p == pe ) {
+ if (seg_start == (uintptr_t)pe) {
break;
}
/* Original C code replaced with hand tuned assembly code */
@@ -429,17 +431,17 @@
done = 0;
do {
/* Check for overflow */
- if (pe + SPINSZ > pe) {
+ if ((uintptr_t)(pe + SPINSZ) > (uintptr_t)pe) {
pe += SPINSZ;
} else {
pe = end;
}
- if (pe >= end) {
+ if ((uintptr_t)pe >= (uintptr_t)end) {
pe = end;
done++;
}
len = pe - p;
- if (p == pe ) {
+ if ((uintptr_t)p == (uintptr_t)pe) {
break;
}
/* Original C code replaced with hand tuned assembly code
@@ -470,16 +472,16 @@
done = 0;
do {
/* Check for overflow */
- if (pe + SPINSZ > pe) {
+ if ((uintptr_t)(pe + SPINSZ) > (uintptr_t)pe) {
pe += SPINSZ;
} else {
pe = end;
}
- if (pe >= end) {
+ if ((uintptr_t)pe >= (uintptr_t)end) {
pe = end;
done++;
}
- if (p == pe ) {
+ if ((uintptr_t)p == (uintptr_t)pe) {
break;
}
/* Original C code replaced with hand tuned assembly code
@@ -536,16 +538,16 @@
done = 0;
do {
/* Check for underflow */
- if (pe - SPINSZ < pe) {
+ if ((uintptr_t)(pe - SPINSZ) < (uintptr_t)pe) {
pe -= SPINSZ;
} else {
pe = start;
}
- if (pe <= start) {
+ if ((uintptr_t)pe <= (uintptr_t)start) {
pe = start;
done++;
}
- if (p == pe ) {
+ if ((uintptr_t)p == (uintptr_t)pe) {
break;
}
/* Original C code replaced with hand tuned assembly code
@@ -625,16 +627,16 @@
pat = p1;
do {
/* Check for overflow */
- if (pe + SPINSZ > pe) {
+ if ((uintptr_t)(pe + SPINSZ) > (uintptr_t)pe) {
pe += SPINSZ;
} else {
pe = end;
}
- if (pe >= end) {
+ if ((uintptr_t)pe >= (uintptr_t)end) {
pe = end;
done++;
}
- if (p == pe ) {
+ if ((uintptr_t)p == (uintptr_t)pe) {
break;
}
/* Do a SPINSZ section of memory */
@@ -687,16 +689,16 @@
pat = p1;
do {
/* Check for overflow */
- if (pe + SPINSZ > pe) {
+ if ((uintptr_t)(pe + SPINSZ) > (uintptr_t)pe) {
pe += SPINSZ;
} else {
pe = end;
}
- if (pe >= end) {
+ if ((uintptr_t)pe >= (uintptr_t)end) {
pe = end;
done++;
}
- if (p == pe ) {
+ if ((uintptr_t)p == (uintptr_t)pe) {
break;
}
/* Original C code replaced with hand tuned assembly code
@@ -800,16 +802,16 @@
done = 0;
do {
/* Check for underflow */
- if (pe - SPINSZ < pe) {
+ if ((uintptr_t)(pe - SPINSZ) < (uintptr_t)pe) {
pe -= SPINSZ;
} else {
pe = start;
}
- if (pe <= start) {
+ if ((uintptr_t)pe <= (uintptr_t)start) {
pe = start;
done++;
}
- if (p == pe ) {
+ if ((uintptr_t)p == (uintptr_t)pe) {
break;
}
/* Original C code replaced with hand tuned assembly code
@@ -908,16 +910,16 @@
done = 0;
do {
/* Check for overflow */
- if (pe + SPINSZ > pe) {
+ if ((uintptr_t)(pe + SPINSZ) > (uintptr_t)pe) {
pe += SPINSZ;
} else {
pe = end;
}
- if (pe >= end) {
+ if ((uintptr_t)pe >= (uintptr_t)end) {
pe = end;
done++;
}
- if (p == pe ) {
+ if ((uintptr_t)p == (uintptr_t)pe) {
break;
}
/* Original C code replaced with hand tuned assembly code
@@ -953,16 +955,16 @@
k = 0;
do {
/* Check for overflow */
- if (pe + SPINSZ > pe) {
+ if ((uintptr_t)(pe + SPINSZ) > (uintptr_t)pe) {
pe += SPINSZ;
} else {
pe = end;
}
- if (pe >= end) {
+ if ((uintptr_t)pe >= (uintptr_t)end) {
pe = end;
done++;
}
- if (p == pe ) {
+ if ((uintptr_t)p == (uintptr_t)pe) {
break;
}
/* Original C code replaced with hand tuned assembly code
@@ -1011,16 +1013,17 @@
done = 0;
do {
/* Check for overflow */
- if (pe + SPINSZ > pe) {
+ if ((uintptr_t)(pe + SPINSZ) > (uintptr_t)pe) {
pe += SPINSZ;
} else {
pe = end;
}
- if (pe >= end) {
+ if ((uintptr_t)pe >= (uintptr_t)end) {
+
pe = end;
done++;
}
- if (p == pe ) {
+ if ((uintptr_t)p == (uintptr_t)pe) {
break;
}
/* Original C code replaced with hand tuned assembly code
@@ -1100,16 +1103,18 @@
done = 0;
do {
/* Check for overflow */
- if (pe + SPINSZ*4 > pe) {
+ if ((uintptr_t)(pe + SPINSZ*4) > (uintptr_t)pe) {
pe += SPINSZ*4;
} else {
pe = end;
}
- if (pe >= end) {
+ if ((uintptr_t)pe >= (uintptr_t)end) {
+
pe = end;
done++;
}
- if (p == pe ) {
+ if ((uintptr_t)p == (uintptr_t)pe) {
+
break;
}
len = ((ulong)pe - (ulong)p) / 64;
@@ -1169,16 +1174,16 @@
done = 0;
do {
/* Check for overflow */
- if (pe + SPINSZ*4 > pe) {
+ if ((uintptr_t)(pe + SPINSZ*4) > (uintptr_t)pe) {
pe += SPINSZ*4;
} else {
pe = end;
}
- if (pe >= end) {
+ if ((uintptr_t)pe >= (uintptr_t)end) {
pe = end;
done++;
}
- if (p == pe ) {
+ if ((uintptr_t)p == (uintptr_t)pe) {
break;
}
pp = p + ((pe - p) / 2);
@@ -1236,16 +1241,16 @@
done = 0;
do {
/* Check for overflow */
- if (pe + SPINSZ*4 > pe) {
+ if ((uintptr_t)(pe + SPINSZ*4) > (uintptr_t)pe) {
pe += SPINSZ*4;
} else {
pe = end;
}
- if (pe >= end) {
+ if ((uintptr_t)pe >= (uintptr_t)end) {
pe = end;
done++;
}
- if (p == pe ) {
+ if ((uintptr_t)p == (uintptr_t)pe) {
break;
}
asm __volatile__ (
@@ -1268,7 +1273,7 @@
"pushl 4(%%edi)\n\t"
"pushl %%ecx\n\t"
"pushl %%edi\n\t"
- "call mv_error\n\t"
+ "call error\n\t"
"popl %%edi\n\t"
"addl $8,%%esp\n\t"
"popl %%edx\n\t"
@@ -1311,7 +1316,7 @@
end = v->map[j].end;
pe = start;
p = start;
- for (p=end; p<end; p++) {
+ for (p=start; p<end; p++) {
*p = p1;
}
do_tick();
@@ -1326,7 +1331,7 @@
end = v->map[j].end;
pe = start;
p = start;
- for (p=end; p<end; p++) {
+ for (p=start; p<end; p++) {
if ((bad=*p) != p1) {
error((ulong*)p, p1, bad);
}
@@ -1343,350 +1348,6 @@
}
-/*
- * Display data error message. Don't display duplicate errors.
- */
-void error(ulong *adr, ulong good, ulong bad)
-{
- ulong xor;
- int patnchg,baddevchg;
-
- xor = good ^ bad;
-#ifdef USB_WAR
- /* Skip any errrors that appear to be due to the BIOS using location
- * 0x4e0 for USB keyboard support. This often happens with Intel
- * 810, 815 and 820 chipsets. It is possible that we will skip
- * a real error but the odds are very low.
- */
- if ((ulong)adr == 0x4e0 || (ulong)adr == 0x410) {
- return;
- }
-#endif
-
- /* Process the address in the pattern administration */
- patnchg=insertaddress ((ulong) adr);
- baddevchg=add_dmi_err((ulong) adr );
-
- update_err_counts();
-
- if (v->printmode == PRINTMODE_ADDRESSES) {
-
- /* Don't display duplicate errors */
- if ((ulong)adr == (ulong)v->eadr && xor == v->exor) {
- print_err_counts();
- dprint(v->msg_line, 66, ++ecount, 5, 0);
- return;
- }
- print_err(adr, good, bad, xor);
-
- } else if (v->printmode == PRINTMODE_PATTERNS) {
- print_err_counts();
-
- if (patnchg) {
- printpatn();
- }
- } else if (v->printmode == PRINTMODE_DMI) {
- print_err_counts();
- if (baddevchg==1)
- print_dmi_err();
- }
-}
-
-/*
- * Display data error message from the block move test. The actual failing
- * address is unknown so don't use this failure information to create
- * BadRAM patterns.
- */
-void mv_error(ulong *adr, ulong good, ulong bad)
-{
- ulong xor;
-
- update_err_counts();
- if (v->printmode == PRINTMODE_NONE) {
- return;
- }
- xor = good ^ bad;
- print_err(adr, good, bad, xor);
-}
-
-/*
- * Display address error message.
- * Since this is strictly an address test, trying to create BadRAM
- * patterns does not make sense. Just report the error.
- */
-void ad_err1(ulong *adr1, ulong *adr2, ulong good, ulong bad)
-{
- ulong xor;
- update_err_counts();
- if (v->printmode == PRINTMODE_NONE) {
- return;
- }
- xor = ((ulong)adr1) ^ ((ulong)adr2);
- print_err(adr1, good, bad, xor);
-}
-
-/*
- * Display address error message.
- * Since this type of address error can also report data errors go
- * ahead and generate BadRAM patterns.
- */
-void ad_err2(ulong *adr, ulong bad)
-{
- int patnchg,baddevchg;
-
- /* Process the address in the pattern administration */
- patnchg=insertaddress ((ulong) adr);
- baddevchg=add_dmi_err((ulong) adr );
-
- update_err_counts();
- if (v->printmode == PRINTMODE_ADDRESSES) {
- print_err(adr, (ulong)adr, bad, ((ulong)adr) ^ bad);
- } else if (v->printmode == PRINTMODE_PATTERNS) {
- print_err_counts();
- if (patnchg) {
- printpatn();
- }
- } else if (v->printmode == PRINTMODE_DMI) {
- print_err_counts();
- if (baddevchg==1)
- print_dmi_err();
- }
-}
-void print_hdr(void)
-{
- if ((v->ecount)>1) {
- return;
- }
- cprint(LINE_HEADER, 0, "Tst Pass Failing Address Good Bad Err-Bits Count Chan");
- cprint(LINE_HEADER+1, 0,"--- ---- ----------------------- -------- -------- -------- ----- ----");
-}
-
-static void update_err_counts(void)
-{
- ++(v->ecount);
-
- if (beepmode){
- beep(600);
- beep(1000);
- }
-
- tseq[v->test].errors++;
-}
-
-static void print_err_counts(void)
-{
- int i;
- char *pp;
-
- if ((v->ecount > 1048756) && (v->ecount % 32768 != 0))
- return;
-
- if ((v->ecount > 2048) && (v->ecount % 1024 != 0))
- return;
-
- dprint(LINE_INFO, COL_ERR, v->ecount, 6, 0);
- dprint(LINE_INFO, COL_ECC_ERR, v->ecc_ecount, 6, 0);
-
- /* Paint the error messages on the screen red to provide a vivid */
- /* indicator that an error has occured */
- if (v->msg_line < 24) {
- for(i=0, pp=(char *)((SCREEN_ADR+v->msg_line*160+1));
- i<76; i++, pp+=2) {
- *pp = 0x47;
- }
- }
-
-
-}
-
-static void common_err(ulong page, ulong offset)
-{
- ulong mb;
-
- /* Check for keyboard input */
- print_hdr();
- check_input();
- scroll();
- print_err_counts();
-
- mb = page >> 8;
- dprint(v->msg_line, 0, v->test, 3, 0);
- dprint(v->msg_line, 4, v->pass, 5, 0);
- hprint(v->msg_line, 11, page);
- hprint2(v->msg_line, 19, offset, 3);
- cprint(v->msg_line, 22, " - . MB");
- dprint(v->msg_line, 25, mb, 5, 0);
- dprint(v->msg_line, 31, ((page & 0xF)*10)/16, 1, 0);
-}
-/*
- * Print an individual error
- */
-void print_err( ulong *adr, ulong good, ulong bad, ulong xor)
-{
- ulong page, offset;
-
- page = page_of(adr);
- offset = ((unsigned long)adr) & 0xFFF;
- common_err(page, offset);
-
-
- ecount = 1;
- hprint(v->msg_line, 36, good);
- hprint(v->msg_line, 46, bad);
- hprint(v->msg_line, 56, xor);
- dprint(v->msg_line, 66, ecount, 5, 0);
- v->eadr = adr;
- v->exor = xor;
-}
-
-/*
- * Print an ecc error
- */
-void print_ecc_err(unsigned long page, unsigned long offset,
- int corrected, unsigned short syndrome, int channel)
-{
- if (!corrected) {update_err_counts();}
- ++(v->ecc_ecount);
- if (v->printmode == PRINTMODE_NONE) {
- return;
- }
- common_err(page, offset);
-
- cprint(v->msg_line, 36,
- corrected?"corrected ": "uncorrected ");
- hprint2(v->msg_line, 60, syndrome, 4);
- cprint(v->msg_line, 68, "ECC");
- dprint(v->msg_line, 74, channel, 2, 0);
-}
-
-#ifdef PARITY_MEM
-/*
- * Print a parity error message
- */
-void parity_err( unsigned long edi, unsigned long esi)
-{
- unsigned long addr;
-
- if (v->test == 5) {
- addr = esi;
- } else {
- addr = edi;
- }
- update_err_counts();
- if (v->printmode == PRINTMODE_NONE) {
- return;
- }
- common_err(page_of((void *)addr), addr & 0xFFF);
- cprint(v->msg_line, 36, "Parity error detected ");
-}
-#endif
-
-
-/*
- * Print the pattern array as a LILO boot option addressing BadRAM support.
- */
-void printpatn (void)
-{
- int idx=0;
- int x;
-
- /* Check for keyboard input */
- check_input();
-
- if (v->numpatn == 0)
- return;
-
- scroll();
-
- cprint (v->msg_line, 0, "badram=");
- x=7;
-
- for (idx = 0; idx < v->numpatn; idx++) {
-
- if (x > 80-22) {
- scroll();
- x=7;
- }
- cprint (v->msg_line, x, "0x");
- hprint (v->msg_line, x+2, v->patn[idx].adr );
- cprint (v->msg_line, x+10, ",0x");
- hprint (v->msg_line, x+13, v->patn[idx].mask);
- if (idx+1 < v->numpatn)
- cprint (v->msg_line, x+21, ",");
- x+=22;
- }
-}
-
-/*
- * Show progress by displaying elapsed time and update bar graphs
- */
-void do_tick(void)
-{
- int i, pct;
- ulong h, l, t;
-
- /* FIXME only print serial error messages from the tick handler */
- if (v->ecount) {
- print_err_counts();
- }
-
- nticks++;
- v->total_ticks++;
-
- pct = 100*nticks/test_ticks;
- dprint(1, COL_MID+4, pct, 3, 0);
- i = (BAR_SIZE * pct) / 100;
- while (i > v->tptr) {
- if (v->tptr >= BAR_SIZE) {
- break;
- }
- cprint(1, COL_MID+9+v->tptr, "#");
- v->tptr++;
- }
-
- pct = 100*v->total_ticks/v->pass_ticks;
- dprint(0, COL_MID+4, pct, 3, 0);
- i = (BAR_SIZE * pct) / 100;
- while (i > v->pptr) {
- if (v->pptr >= BAR_SIZE) {
- break;
- }
- cprint(0, COL_MID+9+v->pptr, "#");
- v->pptr++;
- }
-
- /* We can't do the elapsed time unless the rdtsc instruction
- * is supported
- */
- if (v->rdtsc) {
- asm __volatile__(
- "rdtsc":"=a" (l),"=d" (h));
- asm __volatile__ (
- "subl %2,%0\n\t"
- "sbbl %3,%1"
- :"=a" (l), "=d" (h)
- :"g" (v->startl), "g" (v->starth),
- "0" (l), "1" (h));
- t = h * ((unsigned)0xffffffff / v->clks_msec) / 1000;
- t += (l / v->clks_msec) / 1000;
- i = t % 60;
- dprint(LINE_TIME, COL_TIME+9, i%10, 1, 0);
- dprint(LINE_TIME, COL_TIME+8, i/10, 1, 0);
- t /= 60;
- i = t % 60;
- dprint(LINE_TIME, COL_TIME+6, i % 10, 1, 0);
- dprint(LINE_TIME, COL_TIME+5, i / 10, 1, 0);
- t /= 60;
- dprint(LINE_TIME, COL_TIME, t, 4, 0);
- }
-
- /* Check for keyboard input */
- check_input();
-
- /* Poll for ECC errors */
- poll_errors();
-}
-
/* Sleep function */
void sleep(int n, int sms)
|
|
[-]
[+]
|
Changed |
memtest86+-4.20.tar.bz2/test.h
^
|
| @@ -5,17 +5,19 @@
* ----------------------------------------------------
* MemTest86+ V2.00 Specific code (GPL V2.0)
* By Samuel DEMEULEMEESTER, sdemeule@memtest.org
- * http://www.x86-secret.com - http://www.memtest.org
+ * http://www.canardpc.com - http://www.memtest.org
*/
-
+#ifndef _TEST_H_
+#define _TEST_H_
#define E88 0x00
#define E801 0x04
#define E820NR 0x08 /* # entries in E820MAP */
#define E820MAP 0x0c /* our map */
-#define E820MAX 32 /* number of entries in E820MAP */
+#define E820MAX 64 /* number of entries in E820MAP */
#define E820ENTRY_SIZE 20
-#define MEMINFO_SIZE 0x28c
+#define MEMINFO_SIZE (E820MAP + E820MAX * E820ENTRY_SIZE)
+#define MAX_DMI_MEMDEVS 16
#ifndef __ASSEMBLY__
@@ -39,10 +41,15 @@
};
typedef unsigned long ulong;
-#define SPINSZ 0x800000
+#define SPINSZ 0x2000000
#define MOD_SZ 20
#define BAILOUT if (bail) goto skip_test;
#define BAILR if (bail) return;
+#define NULL 0
+
+#define DMI_SEARCH_START 0x0000F000
+#define DMI_SEARCH_LENGTH 0x000F0FFF
+#define MAX_DMI_MEMDEVS 16
#define RES_START 0xa0000
#define RES_END 0x100000
@@ -50,15 +57,15 @@
#define SCREEN_END_ADR (SCREEN_ADR + 80*25*2)
#define TITLE_WIDTH 28
-#define LINE_TIME 10
+#define LINE_TIME 11
#define COL_TIME 0
#define LINE_TST 2
#define LINE_RANGE 3
#define LINE_CPU 1
#define COL_MID 30
-#define LINE_PAT 4
+#define LINE_PAT 4
#define COL_PAT 41
-#define LINE_INFO 10
+#define LINE_INFO 11
#define COL_CACHE_TOP 13
#define COL_RESERVED 22
#define COL_MMAP 29
@@ -68,9 +75,11 @@
#define COL_PASS 56
#define COL_ERR 63
#define COL_ECC_ERR 72
-#define LINE_HEADER 12
-#define LINE_SCROLL 14
+#define LINE_HEADER 13
+#define LINE_SCROLL 15
#define BAR_SIZE (78-COL_MID-9)
+#define LINE_MSG 18
+#define COL_MSG 18
#define POP_W 30
#define POP_H 15
@@ -80,13 +89,12 @@
#define POP2_H 21
#define POP2_X 3
#define POP2_Y 2
-#define NULL 0
+//#define NULL 0
/* memspeed operations */
-#define MS_BCOPY 1
-#define MS_COPY 2
-#define MS_WRITE 3
-#define MS_READ 4
+#define MS_COPY 1
+#define MS_WRITE 2
+#define MS_READ 3
#define SZ_MODE_BIOS 1
#define SZ_MODE_BIOS_RES 2
@@ -94,6 +102,7 @@
#define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
int memcmp(const void *s1, const void *s2, ulong count);
+int strncmp(const char *s1, const char *s2, ulong n);
void *memmove(void *dest, const void *src, ulong n);
int query_linuxbios(void);
int query_pcbios(void);
@@ -102,6 +111,7 @@
void printpatn(void);
void itoa(char s[], int n);
void reverse(char *p);
+void serial_console_setup(char *param);
void serial_echo_init(void);
void serial_echo_print(const char *s);
void ttyprint(int y, int x, const char *s);
@@ -130,6 +140,7 @@
void check_input(void);
void footer(void);
void scroll(void);
+void clear_scroll(void);
void popup(void);
void popdown(void);
void popclear(void);
@@ -144,6 +155,7 @@
void bit_fade(void);
void sleep(int sec, int sms);
void beep(unsigned int frequency);
+int getnum(ulong val);
void block_move(int iter);
void find_ticks(void);
void print_err(ulong *adr, ulong good, ulong bad, ulong xor);
@@ -161,15 +173,19 @@
void start_config(void);
void clear_screen(void);
void paging_off(void);
+void show_spd(void);
int map_page(unsigned long page);
void *mapping(unsigned long page_address);
void *emapping(unsigned long page_address);
unsigned long page_of(void *ptr);
+ulong memspeed(ulong src, ulong len, int iter, int type);
+ulong correct_tsc(ulong el_org);
+#define PRINTMODE_SUMMARY 1
#define PRINTMODE_ADDRESSES 0
-#define PRINTMODE_PATTERNS 1
-#define PRINTMODE_DMI 2
+#define PRINTMODE_PATTERNS 2
#define PRINTMODE_NONE 3
+#define PRINTMODE_DMI 4
#define BADRAM_MAXPATNS 10
@@ -237,7 +253,6 @@
short cache;
short pat;
short iter;
- short ticks;
short errors;
char *msg;
};
@@ -253,14 +268,50 @@
unsigned char cache_info[16];
long pwrcap;
long ext;
+ long feature_flag;
+ long dcache0_eax;
+ long dcache0_ebx;
+ long dcache0_ecx;
+ long dcache0_edx;
+ long dcache1_eax;
+ long dcache1_ebx;
+ long dcache1_ecx;
+ long dcache1_edx;
+ long dcache2_eax;
+ long dcache2_ebx;
+ long dcache2_ecx;
+ long dcache2_edx;
+ long dcache3_eax;
+ long dcache3_ebx;
+ long dcache3_ecx;
+ long dcache3_edx;
+};
+
+struct xadr {
+ ulong page;
+ ulong offset;
};
-#define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */
+struct err_info {
+ struct xadr low_addr;
+ struct xadr high_addr;
+ unsigned long ebits;
+ long tbits;
+ short min_bits;
+ short max_bits;
+ unsigned long maxl;
+ unsigned long eadr;
+ unsigned long exor;
+ unsigned long cor_err;
+ short hdr_flag;
+};
+
+#define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */
#define MAX_MEM_SEGMENTS E820MAX
-/* Define common variables accross relocations of memtest86 */
+/* Define common variables accross relocations of memtest86+ */
struct vars {
- int test;
+ volatile int test;
int pass;
unsigned long *eadr;
unsigned long exor;
@@ -277,6 +328,7 @@
int pptr;
int tptr;
int beepmode;
+ struct err_info erri;
struct pmap pmap[MAX_MEM_SEGMENTS];
struct mmap map[MAX_MEM_SEGMENTS];
ulong plim_lower;
@@ -287,6 +339,7 @@
ulong snaph;
ulong snapl;
ulong extclock;
+ unsigned long imc_type;
int printmode;
int numpatn;
struct pair patn [BADRAM_MAXPATNS];
@@ -305,4 +358,10 @@
extern struct mem_info_t mem_info;
+/* CPU mode types */
+#define CPM_SINGLE 1
+#define CPM_RROBIN 2
+#define CPM_SEQ 3
+
#endif /* __ASSEMBLY__ */
+#endif /* _TEST_H_ */
\ No newline at end of file
|
|
[-]
[+]
|
Changed |
serial-enable
^
|
| @@ -9,26 +9,6 @@
/* SERIAL_TTY - The default serial port to use. 0=ttyS0, 1=ttyS1 */
#define SERIAL_TTY 0
---- memtest86+-2.01/init.c
-+++ memtest86+-2.01/init.c
-@@ -40,6 +40,7 @@
- static void cacheable(void);
- static int cpuspeed(void);
- int beepmode;
-+extern short serial_cons;
-
- static void display_init(void)
- {
-@@ -76,6 +77,9 @@
- }
-
- serial_echo_print("\x1B[0m");
-+
-+ if (!serial_cons && SERIAL_CONSOLE_DEFAULT)
-+ cprint (23, 0, "Timout on serial console: disabled");
- }
-
- /*
--- memtest86+-2.01/serial.h
+++ memtest86+-2.01/serial.h
@@ -140,10 +140,12 @@
@@ -48,3 +28,23 @@
#if 0
static inline void serial_echo(int ch)
+--- memtest86+-4.20/init.c.src 2011-04-17 13:03:02.747309087 +0200
++++ memtest86+-4.20/init.c 2011-04-17 13:05:10.911541871 +0200
+@@ -42,6 +42,7 @@
+ static void cacheable(void);
+ static int cpuspeed(void);
+ int beepmode, fail_safe;
++extern short serial_cons;
+
+ /* Failsafe function */
+ /* msec: number of ms to wait - scs: scancode expected to stop */
+@@ -125,6 +126,9 @@
+ }
+
+ serial_echo_print("\x1B[0m");
++
++ if (!serial_cons && SERIAL_CONSOLE_DEFAULT)
++ cprint (23, 0, "Timout on serial console: disabled");
+ }
+
+ /*
|
