| @@ -0,0 +1,29 @@
+--- boost/detail/sp_counted_base_gcc_ia64.hpp
++++ boost/detail/sp_counted_base_gcc_ia64.hpp
+@@ -34,7 +34,7 @@
+ // release barrier associated with it. We choose release as it should be
+ // cheaper.
+ __asm__ ("fetchadd4.rel %0=%1,1" :
+- "=r"(tmp), "=m"(*pw) :
++ "=r"(tmp), "+m"(*pw) :
+ "m"( *pw ));
+ }
+
+@@ -47,7 +47,7 @@
+ __asm__ (" fetchadd4.rel %0=%1,-1 ;; \n"
+ " cmp.eq p7,p0=1,%0 ;; \n"
+ "(p7) ld4.acq %0=%1 " :
+- "=&r"(rv), "=m"(*pw) :
++ "=&r"(rv), "+m"(*pw) :
+ "m"( *pw ) :
+ "p7");
+
+@@ -71,7 +71,7 @@
+ "(p7) br.cond.spnt 0b \n"
+ " mov %0=%1 ;; \n"
+ "1:" :
+- "=&r"(rv), "=&r"(tmp), "=&r"(tmp2), "=m"(*pw) :
++ "=&r"(rv), "=&r"(tmp), "=&r"(tmp2), "+m"(*pw) :
+ "m"( *pw ) :
+ "ar.ccv", "p7");
+
|
